| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 | 
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| cip_base_pkg.dut_and_edn_rsts | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 4 | 0 | 4 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| resets_trans | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 4 | 0 | 4 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| rst1_start_last_end_first | 1515 | 1 | T3 | 1 | T5 | 2 | T73 | 3 | ||||
| rst1_start_first_end_last | 1393 | 1 | T73 | 1 | T48 | 1 | T50 | 3 | ||||
| rst1_start_last_end_last | 2517 | 1 | T48 | 3 | T50 | 3 | T51 | 5 | ||||
| rst1_start_first_end_first | 2607 | 1 | T3 | 7 | T5 | 10 | T48 | 2 | 
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |