Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T43,T200,T201
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12503	0	0
DisabledNoTrigBkwd_A	2147483647	852723	0	0
DisabledNoTrigFwd_A	2147483647	1379458630	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12503	0	0
T4	923657	0	0	0
T5	639068	0	0	0
T14	372589	0	0	0
T15	593241	0	0	0
T16	524315	0	0	0
T25	28330	0	0	0
T43	3351	659	0	0
T44	17313	0	0	0
T63	40214	0	0	0
T64	44741	0	0	0
T200	0	809	0	0
T201	0	325	0	0
T202	1307	515	0	0
T203	0	654	0	0
T204	0	1243	0	0
T205	0	1117	0	0
T206	0	491	0	0
T207	0	357	0	0
T208	0	128	0	0
T209	0	586	0	0
T210	0	726	0	0
T211	0	198	0	0
T212	0	667	0	0
T213	1453	637	0	0
T214	0	743	0	0
T215	0	808	0	0
T216	0	215	0	0
T217	0	802	0	0
T218	0	823	0	0
T219	35407	0	0	0
T220	26992	0	0	0
T221	114205	0	0	0
T222	163357	0	0	0
T223	20325	0	0	0
T224	10026	0	0	0
T225	902828	0	0	0
T226	544050	0	0	0
T227	125734	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	852723	0	0
T1	7777	25	0	0
T2	502848	4329	0	0
T3	551632	2742	0	0
T4	0	10109	0	0
T5	0	1688	0	0
T6	502668	0	0	0
T10	198560	79	0	0
T11	141904	15	0	0
T12	94768	202	0	0
T13	0	448	0	0
T14	0	2123	0	0
T18	316332	100	0	0
T19	222836	66	0	0
T20	114976	18	0	0
T21	17658	8	0	0
T24	0	2	0	0
T25	0	203	0	0
T43	0	4	0	0
T44	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1379458630	0	0
T1	31108	23629	0	0
T2	502848	273314	0	0
T3	551632	458728	0	0
T6	502668	471674	0	0
T10	198560	63928	0	0
T11	141904	103213	0	0
T12	94768	45764	0	0
T18	316332	28174	0	0
T19	222836	75294	0	0
T20	114976	94844	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T213
1	1	Covered	T2,T3,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T11

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	634428730	637	0	0
DisabledNoTrigBkwd_A	634428730	280784	0	0
DisabledNoTrigFwd_A	634428730	325897362	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	637	0	0
T213	1453	637	0	0
T219	35407	0	0	0
T220	26992	0	0	0
T221	114205	0	0	0
T222	163357	0	0	0
T223	20325	0	0	0
T224	10026	0	0	0
T225	902828	0	0	0
T226	544050	0	0	0
T227	125734	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	280784	0	0
T2	125712	1787	0	0
T3	137908	425	0	0
T4	0	6542	0	0
T6	125667	0	0	0
T10	49640	4	0	0
T11	35476	15	0	0
T12	23692	2	0	0
T18	79083	20	0	0
T19	55709	16	0	0
T20	28744	18	0	0
T21	5886	8	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	325897362	0	0
T1	7777	7681	0	0
T2	125712	10339	0	0
T3	137908	110282	0	0
T6	125667	125657	0	0
T10	49640	35378	0	0
T11	35476	3065	0	0
T12	23692	8413	0	0
T18	79083	582	0	0
T19	55709	31682	0	0
T20	28744	8813	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T11
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T43,T200,T201
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	634428730	3675	0	0
DisabledNoTrigBkwd_A	634428730	201329	0	0
DisabledNoTrigFwd_A	634428730	353879559	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	3675	0	0
T4	923657	0	0	0
T5	639068	0	0	0
T14	372589	0	0	0
T15	593241	0	0	0
T16	524315	0	0	0
T25	28330	0	0	0
T43	3351	659	0	0
T44	17313	0	0	0
T63	40214	0	0	0
T64	44741	0	0	0
T200	0	809	0	0
T201	0	325	0	0
T210	0	726	0	0
T211	0	198	0	0
T214	0	743	0	0
T216	0	215	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	201329	0	0
T1	7777	25	0	0
T2	125712	1	0	0
T3	137908	210	0	0
T6	125667	0	0	0
T10	49640	6	0	0
T11	35476	0	0	0
T12	23692	1	0	0
T14	0	828	0	0
T18	79083	28	0	0
T19	55709	15	0	0
T20	28744	0	0	0
T24	0	2	0	0
T43	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	353879559	0	0
T1	7777	586	0	0
T2	125712	125166	0	0
T3	137908	116369	0	0
T6	125667	125657	0	0
T10	49640	12088	0	0
T11	35476	29370	0	0
T12	23692	17081	0	0
T18	79083	2797	0	0
T19	55709	14415	0	0
T20	28744	28677	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T10

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T202,T203,T207
1	1	Covered	T2,T3,T10

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T10

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	634428730	2995	0	0
DisabledNoTrigBkwd_A	634428730	172925	0	0
DisabledNoTrigFwd_A	634428730	363870915	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	2995	0	0
T81	575036	0	0	0
T84	181109	0	0	0
T191	73386	0	0	0
T192	4040	0	0	0
T193	85823	0	0	0
T202	1307	515	0	0
T203	0	654	0	0
T207	0	357	0	0
T212	0	667	0	0
T217	0	802	0	0
T228	16926	0	0	0
T229	286812	0	0	0
T230	32257	0	0	0
T231	459583	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	172925	0	0
T2	125712	2531	0	0
T3	137908	2044	0	0
T4	0	2170	0	0
T5	0	1529	0	0
T6	125667	0	0	0
T10	49640	25	0	0
T11	35476	0	0	0
T12	23692	1	0	0
T18	79083	52	0	0
T19	55709	10	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T25	0	158	0	0
T44	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	363870915	0	0
T1	7777	7681	0	0
T2	125712	13205	0	0
T3	137908	120036	0	0
T6	125667	125657	0	0
T10	49640	10898	0	0
T11	35476	35389	0	0
T12	23692	11793	0	0
T18	79083	18966	0	0
T19	55709	26977	0	0
T20	28744	28677	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T10

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T204,T205,T206
1	1	Covered	T2,T3,T10

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T10

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	634428730	5196	0	0
DisabledNoTrigBkwd_A	634428730	197685	0	0
DisabledNoTrigFwd_A	634428730	335810794	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	5196	0	0
T88	8775	0	0	0
T102	170623	0	0	0
T204	3584	1243	0	0
T205	0	1117	0	0
T206	0	491	0	0
T208	0	128	0	0
T209	0	586	0	0
T215	0	808	0	0
T218	0	823	0	0
T232	8823	0	0	0
T233	288553	0	0	0
T234	72393	0	0	0
T235	9197	0	0	0
T236	12983	0	0	0
T237	24115	0	0	0
T238	348473	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	197685	0	0
T2	125712	10	0	0
T3	137908	63	0	0
T4	0	1397	0	0
T5	0	159	0	0
T6	125667	0	0	0
T10	49640	44	0	0
T11	35476	0	0	0
T12	23692	198	0	0
T13	0	448	0	0
T14	0	1295	0	0
T18	79083	0	0	0
T19	55709	25	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T25	0	45	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	335810794	0	0
T1	7777	7681	0	0
T2	125712	124604	0	0
T3	137908	112041	0	0
T6	125667	94703	0	0
T10	49640	5564	0	0
T11	35476	35389	0	0
T12	23692	8477	0	0
T18	79083	5829	0	0
T19	55709	2220	0	0
T20	28744	28677	0	0