Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[3].u_esc_timer	97.30	97.03	93.33		100.00	96.15	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	97.03	93.33		100.00	96.15	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.60	97.27	93.33	68.57	100.00	96.43	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.39	100.00	97.78	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T22,T23
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T11
1	0	1	Covered	T2,T18,T24
1	1	0	Covered	T1,T3,T11
1	1	1	Covered	T1,T3,T11

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T3,T10,T12
1	0	Covered	T10,T4,T25

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T11
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T4,T25

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T26,T27,T28
1	1	Covered	T3,T10,T12

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T1,T3,T10

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T12

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T12

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T11

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T11

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T3,T11

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T3,T11
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T5,T29,T30
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T19,T20,T4
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T3,T4,T5
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T4,T5,T31
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T3
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T3,T11
TimeoutSt->Phase0St	172	Covered	T3,T10,T12

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T11
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T12
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T11
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T11
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T29,T30
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T19,T20,T4
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T5,T31
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	793	0	0
CheckAccumTrig0_A	2147483647	2247	0	0
CheckAccumTrig1_A	2147483647	85	0	0
CheckClr_A	2147483647	1042	0	0
CheckEn_A	2147483647	1100725644	0	0
CheckPhase0_A	2147483647	2558	0	0
CheckPhase1_A	2147483647	2504	0	0
CheckPhase2_A	2147483647	2450	0	0
CheckPhase3_A	2147483647	2414	0	0
CheckTimeout0_A	2147483647	7221	0	0
CheckTimeoutSt1_A	2147483647	648401	0	0
CheckTimeoutSt2_A	2147483647	6874	0	0
CheckTimeoutStTrig_A	2147483647	261	0	0
ErrorStAllEscAsserted_A	2147483647	4318	0	0
ErrorStIsTerminal_A	2147483647	3478	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	793	0	0
T7	448620	225	0	0
T8	0	246	0	0
T9	0	105	0	0
T32	0	97	0	0
T33	0	120	0	0
T34	40960	0	0	0
T35	770300	0	0	0
T36	35304	0	0	0
T37	442220	0	0	0
T38	350456	0	0	0
T39	1407160	0	0	0
T40	1003476	0	0	0
T41	243056	0	0	0
T42	302432	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2247	0	0
T1	7777	2	0	0
T2	502848	7	0	0
T3	551632	26	0	0
T4	0	18	0	0
T5	0	10	0	0
T6	502668	0	0	0
T10	198560	2	0	0
T11	141904	1	0	0
T12	94768	4	0	0
T13	0	1	0	0
T14	0	2	0	0
T17	0	2	0	0
T18	316332	3	0	0
T19	222836	3	0	0
T20	114976	3	0	0
T21	17658	2	0	0
T24	0	1	0	0
T25	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	85	0	0
T4	1847314	2	0	0
T5	1917204	0	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T12	23692	0	0	0
T13	512755	0	0	0
T15	1779723	0	0	0
T16	1572945	0	0	0
T17	1197954	2	0	0
T18	79083	0	0	0
T19	55709	0	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T24	13453	0	0	0
T25	84990	2	0	0
T31	0	2	0	0
T43	3351	0	0	0
T44	34626	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	120642	0	0	0
T64	134223	0	0	0
T65	100599	0	0	0
T66	14389	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1042	0	0
T1	7777	1	0	0
T2	377136	1	0	0
T3	551632	14	0	0
T4	0	7	0	0
T5	0	23	0	0
T6	502668	0	0	0
T10	198560	0	0	0
T11	141904	0	0	0
T12	94768	2	0	0
T17	0	3	0	0
T18	316332	0	0	0
T19	222836	0	0	0
T20	114976	2	0	0
T21	17658	1	0	0
T24	13453	1	0	0
T25	0	3	0	0
T47	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1100725644	0	0
T1	31108	23626	0	0
T2	502848	23254	0	0
T3	551632	444515	0	0
T6	502668	471674	0	0
T10	198560	28054	0	0
T11	141904	103210	0	0
T12	94768	19213	0	0
T18	316332	28174	0	0
T19	222836	34273	0	0
T20	114976	94841	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2558	0	0
T1	7777	2	0	0
T2	502848	7	0	0
T3	551632	27	0	0
T4	0	24	0	0
T5	0	13	0	0
T6	502668	0	0	0
T10	198560	4	0	0
T11	141904	1	0	0
T12	94768	6	0	0
T13	0	1	0	0
T14	0	2	0	0
T18	316332	3	0	0
T19	222836	5	0	0
T20	114976	3	0	0
T21	17658	2	0	0
T24	0	1	0	0
T25	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2504	0	0
T1	7777	2	0	0
T2	502848	7	0	0
T3	551632	27	0	0
T4	0	22	0	0
T5	0	13	0	0
T6	502668	0	0	0
T10	198560	4	0	0
T11	141904	1	0	0
T12	94768	6	0	0
T13	0	1	0	0
T14	0	2	0	0
T18	316332	3	0	0
T19	222836	4	0	0
T20	114976	2	0	0
T21	17658	2	0	0
T24	0	1	0	0
T25	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2450	0	0
T1	7777	2	0	0
T2	502848	7	0	0
T3	551632	25	0	0
T4	0	21	0	0
T5	0	12	0	0
T6	502668	0	0	0
T10	198560	4	0	0
T11	141904	1	0	0
T12	94768	6	0	0
T13	0	1	0	0
T14	0	2	0	0
T18	316332	3	0	0
T19	222836	4	0	0
T20	114976	2	0	0
T21	17658	2	0	0
T24	0	1	0	0
T25	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2414	0	0
T1	7777	2	0	0
T2	502848	7	0	0
T3	551632	25	0	0
T4	0	20	0	0
T5	0	12	0	0
T6	502668	0	0	0
T10	198560	4	0	0
T11	141904	1	0	0
T12	94768	6	0	0
T13	0	1	0	0
T14	0	2	0	0
T18	316332	3	0	0
T19	222836	4	0	0
T20	114976	2	0	0
T21	17658	2	0	0
T24	0	1	0	0
T25	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7221	0	0
T1	7777	1	0	0
T2	125712	0	0	0
T3	551632	73	0	0
T4	0	250	0	0
T5	0	63	0	0
T6	502668	0	0	0
T10	198560	2	0	0
T11	141904	1	0	0
T12	94768	3	0	0
T17	0	436	0	0
T18	316332	0	0	0
T19	222836	3	0	0
T20	114976	0	0	0
T21	17658	0	0	0
T24	40359	0	0	0
T25	0	3	0	0
T29	0	1	0	0
T31	0	11	0	0
T47	0	4	0	0
T64	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T69	0	5	0	0
T73	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	648401	0	0
T1	7777	11	0	0
T2	125712	0	0	0
T3	551632	4290	0	0
T4	0	17685	0	0
T5	0	9033	0	0
T6	502668	0	0	0
T10	198560	68	0	0
T11	141904	33	0	0
T12	94768	1293	0	0
T17	0	20710	0	0
T18	316332	0	0	0
T19	222836	1480	0	0
T20	114976	0	0	0
T21	17658	0	0	0
T24	40359	0	0	0
T25	0	14	0	0
T29	0	45	0	0
T31	0	837	0	0
T47	0	499	0	0
T64	0	496	0	0
T66	0	254	0	0
T68	0	14	0	0
T69	0	1028	0	0
T73	0	29	0	0
T74	0	118	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6874	0	0
T1	7777	1	0	0
T2	125712	0	0	0
T3	551632	72	0	0
T4	0	242	0	0
T5	0	44	0	0
T6	502668	0	0	0
T10	198560	0	0	0
T11	141904	1	0	0
T12	94768	1	0	0
T17	0	432	0	0
T18	316332	0	0	0
T19	222836	1	0	0
T20	114976	0	0	0
T21	17658	0	0	0
T24	40359	0	0	0
T25	0	1	0	0
T29	0	1	0	0
T31	0	7	0	0
T47	0	2	0	0
T48	0	5	0	0
T66	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T73	0	5	0	0
T75	0	1	0	0
T76	0	8	0	0
T77	0	19	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	261	0	0
T3	137908	1	0	0
T4	0	5	0	0
T5	639068	16	0	0
T6	251334	0	0	0
T10	0	1	0	0
T12	47384	2	0	0
T13	512755	0	0	0
T14	372589	0	0	0
T15	593241	0	0	0
T16	524315	0	0	0
T17	399318	2	0	0
T18	158166	0	0	0
T19	111418	0	0	0
T20	57488	0	0	0
T21	11772	0	0	0
T24	26906	0	0	0
T25	28330	0	0	0
T27	0	1	0	0
T30	0	1	0	0
T43	3351	0	0	0
T45	377447	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	3	0	0
T53	0	1	0	0
T56	0	1	0	0
T57	0	6	0	0
T63	40214	0	0	0
T64	44741	0	0	0
T65	33533	0	0	0
T66	14389	0	0	0
T69	0	3	0	0
T73	0	1	0	0
T75	0	1	0	0
T78	0	2	0	0
T79	0	1	0	0
T80	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4318	0	0
T7	448620	1289	0	0
T8	0	1161	0	0
T9	0	627	0	0
T32	0	579	0	0
T33	0	662	0	0
T34	40960	0	0	0
T35	770300	0	0	0
T36	35304	0	0	0
T37	442220	0	0	0
T38	350456	0	0	0
T39	1407160	0	0	0
T40	1003476	0	0	0
T41	243056	0	0	0
T42	302432	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3478	0	0
T7	448620	1049	0	0
T8	0	921	0	0
T9	0	507	0	0
T32	0	459	0	0
T33	0	542	0	0
T34	40960	0	0	0
T35	770300	0	0	0
T36	35304	0	0	0
T37	442220	0	0	0
T38	350456	0	0	0
T39	1407160	0	0	0
T40	1003476	0	0	0
T41	243056	0	0	0
T42	302432	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	31108	30724	0	0
T2	502848	502820	0	0
T3	551632	551344	0	0
T6	502668	502628	0	0
T10	198560	198308	0	0
T11	141904	141556	0	0
T12	94768	94480	0	0
T18	316332	315952	0	0
T19	222836	222588	0	0
T20	114976	114708	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	31108	30724	0	0
T2	502848	502820	0	0
T3	551632	551344	0	0
T6	502668	502628	0	0
T10	198560	198308	0	0
T11	141904	141556	0	0
T12	94768	94480	0	0
T18	316332	315952	0	0
T19	222836	222588	0	0
T20	114976	114708	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	98	97.03
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	86	96.63
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	0	1
195	0	1
196	0	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T10

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T10

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T12,T19
1	0	1	Covered	T18,T14,T4
1	1	0	Covered	T1,T3,T11
1	1	1	Covered	T3,T19,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T19,T4
0	1	Covered	T19,T4,T5
1	0	Covered	T5,T31,T81

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T19,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T31,T81

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T19,T4
1	0	Not Covered
1	1	Covered	T19,T4,T5

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T12,T19,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T19,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T10,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T10,T12
1	Covered	T3,T13,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T12,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T10,T19,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T12

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T10
Phase1St	198	Covered	T2,T3,T10
Phase2St	215	Covered	T2,T3,T10
Phase3St	233	Covered	T2,T3,T10
TerminalSt	249	Covered	T2,T3,T10
TimeoutSt	159	Covered	T3,T19,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T2,T3,T10
IdleSt->TimeoutSt	159	Covered	T3,T19,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T72,T81,T82
Phase0St->Phase1St	198	Covered	T2,T3,T10
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T19,T83,T84
Phase1St->Phase2St	215	Covered	T2,T3,T10
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T17,T85,T86
Phase2St->Phase3St	233	Covered	T2,T3,T10
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T4,T31,T81
Phase3St->TerminalSt	249	Covered	T2,T3,T10
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T3,T12
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T19,T4
TimeoutSt->Phase0St	172	Covered	T19,T4,T5

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	25	96.15
CASE	144	22	21	95.45
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T19,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T4,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T19,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T19,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T10
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T10
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T19,T83,T84
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T10
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T10
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T17,T85,T86
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T10
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T31,T81
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T10
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	634428730	243	0	0
CheckAccumTrig0_A	634428730	513	0	0
CheckAccumTrig1_A	634428730	15	0	0
CheckClr_A	634428730	235	0	0
CheckEn_A	634179977	269915704	0	0
CheckPhase0_A	634428730	586	0	0
CheckPhase1_A	634428730	576	0	0
CheckPhase2_A	634428730	560	0	0
CheckPhase3_A	634428730	549	0	0
CheckTimeout0_A	634428730	1724	0	0
CheckTimeoutSt1_A	634428730	158523	0	0
CheckTimeoutSt2_A	634428730	1647	0	0
CheckTimeoutStTrig_A	634428730	62	0	0
ErrorStAllEscAsserted_A	634428730	1078	0	0
ErrorStIsTerminal_A	634428730	868	0	0
EscStateOut_A	634178609	634110406	0	0
u_state_regs_A	634428730	634271311	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	243	0	0
T7	112155	63	0	0
T8	0	70	0	0
T9	0	39	0	0
T32	0	37	0	0
T33	0	34	0	0
T34	10240	0	0	0
T35	192575	0	0	0
T36	8826	0	0	0
T37	110555	0	0	0
T38	87614	0	0	0
T39	351790	0	0	0
T40	250869	0	0	0
T41	60764	0	0	0
T42	75608	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	513	0	0
T2	125712	3	0	0
T3	137908	2	0	0
T4	0	6	0	0
T5	0	5	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	0	0	0
T12	23692	2	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	79083	0	0	0
T19	55709	0	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T25	0	1	0	0
T64	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	15	0	0
T5	639068	1	0	0
T15	593241	0	0	0
T16	524315	0	0	0
T17	399318	0	0	0
T25	28330	0	0	0
T31	0	2	0	0
T45	377447	0	0	0
T55	0	1	0	0
T60	0	2	0	0
T62	0	1	0	0
T63	40214	0	0	0
T64	44741	0	0	0
T65	33533	0	0	0
T66	14389	0	0	0
T81	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	235	0	0
T2	125712	2	0	0
T3	137908	1	0	0
T4	0	2	0	0
T5	0	4	0	0
T6	125667	0	0	0
T10	49640	0	0	0
T11	35476	0	0	0
T12	23692	1	0	0
T17	0	3	0	0
T18	79083	0	0	0
T19	55709	1	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T64	0	1	0	0
T68	0	1	0	0
T69	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634179977	269915704	0	0
T1	7777	7680	0	0
T2	125712	4020	0	0
T3	137908	112040	0	0
T6	125667	94703	0	0
T10	49640	2176	0	0
T11	35476	35388	0	0
T12	23692	3177	0	0
T18	79083	5829	0	0
T19	55709	2220	0	0
T20	28744	28676	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	586	0	0
T2	125712	3	0	0
T3	137908	2	0	0
T4	0	7	0	0
T5	0	8	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	0	0	0
T12	23692	2	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	79083	0	0	0
T19	55709	2	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T25	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	576	0	0
T2	125712	3	0	0
T3	137908	2	0	0
T4	0	7	0	0
T5	0	8	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	0	0	0
T12	23692	2	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	79083	0	0	0
T19	55709	1	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T25	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	560	0	0
T2	125712	3	0	0
T3	137908	2	0	0
T4	0	7	0	0
T5	0	8	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	0	0	0
T12	23692	2	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	79083	0	0	0
T19	55709	1	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T25	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	549	0	0
T2	125712	3	0	0
T3	137908	2	0	0
T4	0	6	0	0
T5	0	8	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	0	0	0
T12	23692	2	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	79083	0	0	0
T19	55709	1	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T25	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	1724	0	0
T3	137908	55	0	0
T4	0	15	0	0
T5	0	7	0	0
T6	125667	0	0	0
T10	49640	0	0	0
T11	35476	0	0	0
T12	23692	0	0	0
T17	0	293	0	0
T18	79083	0	0	0
T19	55709	3	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T24	13453	0	0	0
T31	0	8	0	0
T64	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T73	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	158523	0	0
T3	137908	3224	0	0
T4	0	1736	0	0
T5	0	949	0	0
T6	125667	0	0	0
T10	49640	0	0	0
T11	35476	0	0	0
T12	23692	0	0	0
T17	0	13534	0	0
T18	79083	0	0	0
T19	55709	1480	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T24	13453	0	0	0
T31	0	717	0	0
T64	0	496	0	0
T68	0	14	0	0
T69	0	1	0	0
T73	0	29	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	1647	0	0
T3	137908	55	0	0
T4	0	14	0	0
T5	0	4	0	0
T6	125667	0	0	0
T10	49640	0	0	0
T11	35476	0	0	0
T12	23692	0	0	0
T17	0	293	0	0
T18	79083	0	0	0
T19	55709	1	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T24	13453	0	0	0
T31	0	6	0	0
T48	0	3	0	0
T68	0	1	0	0
T73	0	1	0	0
T77	0	9	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	62	0	0
T4	923657	1	0	0
T5	639068	2	0	0
T13	512755	0	0	0
T14	372589	0	0	0
T19	55709	2	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T24	13453	0	0	0
T43	3351	0	0	0
T44	17313	0	0	0
T48	0	3	0	0
T50	0	1	0	0
T64	0	1	0	0
T69	0	1	0	0
T72	0	1	0	0
T78	0	1	0	0
T91	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	1078	0	0
T7	112155	315	0	0
T8	0	306	0	0
T9	0	164	0	0
T32	0	145	0	0
T33	0	148	0	0
T34	10240	0	0	0
T35	192575	0	0	0
T36	8826	0	0	0
T37	110555	0	0	0
T38	87614	0	0	0
T39	351790	0	0	0
T40	250869	0	0	0
T41	60764	0	0	0
T42	75608	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	868	0	0
T7	112155	255	0	0
T8	0	246	0	0
T9	0	134	0	0
T32	0	115	0	0
T33	0	118	0	0
T34	10240	0	0	0
T35	192575	0	0	0
T36	8826	0	0	0
T37	110555	0	0	0
T38	87614	0	0	0
T39	351790	0	0	0
T40	250869	0	0	0
T41	60764	0	0	0
T42	75608	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634178609	634110406	0	0
T1	7777	7681	0	0
T2	125712	125705	0	0
T3	137908	137836	0	0
T6	125667	125657	0	0
T10	49640	49577	0	0
T11	35476	35389	0	0
T12	23692	23620	0	0
T18	79083	78988	0	0
T19	55709	55647	0	0
T20	28744	28677	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	634271311	0	0
T1	7777	7681	0	0
T2	125712	125705	0	0
T3	137908	137836	0	0
T6	125667	125657	0	0
T10	49640	49577	0	0
T11	35476	35389	0	0
T12	23692	23620	0	0
T18	79083	78988	0	0
T19	55709	55647	0	0
T20	28744	28677	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T11
1	0	1	Covered	T2,T18,T24
1	1	0	Covered	T3,T11,T19
1	1	1	Covered	T1,T3,T11

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T5,T69,T50
1	0	Covered	T10,T25,T17

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T10,T25,T17

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T28
1	1	Covered	T5,T69,T50

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T1,T3,T12

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T18,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19,T24,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T2,T10,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T18,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T12,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T10

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T3,T11

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T3,T11
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T92,T72,T81
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T93,T92,T50
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T94,T86,T95
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T96,T39,T97
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T3,T12
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T3,T11
TimeoutSt->Phase0St	172	Covered	T10,T5,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T11
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T10,T5,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T11
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T11
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T92,T98,T22
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T93,T92,T50
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T94,T86,T95
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T96,T39,T97
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T12,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	634428730	180	0	0
CheckAccumTrig0_A	634428730	447	0	0
CheckAccumTrig1_A	634428730	16	0	0
CheckClr_A	634428730	183	0	0
CheckEn_A	634179977	305319165	0	0
CheckPhase0_A	634428730	514	0	0
CheckPhase1_A	634428730	505	0	0
CheckPhase2_A	634428730	495	0	0
CheckPhase3_A	634428730	489	0	0
CheckTimeout0_A	634428730	1740	0	0
CheckTimeoutSt1_A	634428730	161893	0	0
CheckTimeoutSt2_A	634428730	1665	0	0
CheckTimeoutStTrig_A	634428730	59	0	0
ErrorStAllEscAsserted_A	634428730	1062	0	0
ErrorStIsTerminal_A	634428730	852	0	0
EscStateOut_A	634178609	634110406	0	0
u_state_regs_A	634428730	634271311	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	180	0	0
T7	112155	56	0	0
T8	0	53	0	0
T9	0	21	0	0
T32	0	23	0	0
T33	0	27	0	0
T34	10240	0	0	0
T35	192575	0	0	0
T36	8826	0	0	0
T37	110555	0	0	0
T38	87614	0	0	0
T39	351790	0	0	0
T40	250869	0	0	0
T41	60764	0	0	0
T42	75608	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	447	0	0
T1	7777	2	0	0
T2	125712	1	0	0
T3	137908	2	0	0
T4	0	2	0	0
T6	125667	0	0	0
T10	49640	0	0	0
T11	35476	0	0	0
T12	23692	1	0	0
T14	0	1	0	0
T18	79083	1	0	0
T19	55709	1	0	0
T20	28744	0	0	0
T24	0	1	0	0
T43	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	16	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T12	23692	0	0	0
T13	512755	0	0	0
T17	0	1	0	0
T18	79083	0	0	0
T19	55709	0	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T24	13453	0	0	0
T25	0	1	0	0
T43	3351	0	0	0
T52	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	183	0	0
T1	7777	1	0	0
T2	125712	0	0	0
T3	137908	0	0	0
T5	0	3	0	0
T6	125667	0	0	0
T10	49640	0	0	0
T11	35476	0	0	0
T12	23692	1	0	0
T18	79083	0	0	0
T19	55709	0	0	0
T20	28744	0	0	0
T24	0	1	0	0
T25	0	3	0	0
T47	0	1	0	0
T64	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634179977	305319165	0	0
T1	7777	586	0	0
T2	125712	16513	0	0
T3	137908	115107	0	0
T6	125667	125657	0	0
T10	49640	7496	0	0
T11	35476	29369	0	0
T12	23692	9772	0	0
T18	79083	2797	0	0
T19	55709	14415	0	0
T20	28744	28676	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	514	0	0
T1	7777	2	0	0
T2	125712	1	0	0
T3	137908	2	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	0	0	0
T12	23692	1	0	0
T14	0	1	0	0
T18	79083	1	0	0
T19	55709	1	0	0
T20	28744	0	0	0
T24	0	1	0	0
T43	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	505	0	0
T1	7777	2	0	0
T2	125712	1	0	0
T3	137908	2	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	0	0	0
T12	23692	1	0	0
T14	0	1	0	0
T18	79083	1	0	0
T19	55709	1	0	0
T20	28744	0	0	0
T24	0	1	0	0
T43	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	495	0	0
T1	7777	2	0	0
T2	125712	1	0	0
T3	137908	2	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	0	0	0
T12	23692	1	0	0
T14	0	1	0	0
T18	79083	1	0	0
T19	55709	1	0	0
T20	28744	0	0	0
T24	0	1	0	0
T43	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	489	0	0
T1	7777	2	0	0
T2	125712	1	0	0
T3	137908	2	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	0	0	0
T12	23692	1	0	0
T14	0	1	0	0
T18	79083	1	0	0
T19	55709	1	0	0
T20	28744	0	0	0
T24	0	1	0	0
T43	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	1740	0	0
T1	7777	1	0	0
T2	125712	0	0	0
T3	137908	6	0	0
T4	0	3	0	0
T5	0	21	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	1	0	0
T12	23692	0	0	0
T17	0	58	0	0
T18	79083	0	0	0
T19	55709	0	0	0
T20	28744	0	0	0
T25	0	2	0	0
T47	0	1	0	0
T69	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	161893	0	0
T1	7777	11	0	0
T2	125712	0	0	0
T3	137908	413	0	0
T4	0	159	0	0
T5	0	4021	0	0
T6	125667	0	0	0
T10	49640	9	0	0
T11	35476	33	0	0
T12	23692	0	0	0
T17	0	2819	0	0
T18	79083	0	0	0
T19	55709	0	0	0
T20	28744	0	0	0
T25	0	12	0	0
T47	0	11	0	0
T69	0	903	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	1665	0	0
T1	7777	1	0	0
T2	125712	0	0	0
T3	137908	6	0	0
T4	0	3	0	0
T5	0	19	0	0
T6	125667	0	0	0
T10	49640	0	0	0
T11	35476	1	0	0
T12	23692	0	0	0
T17	0	57	0	0
T18	79083	0	0	0
T19	55709	0	0	0
T20	28744	0	0	0
T25	0	1	0	0
T47	0	1	0	0
T69	0	1	0	0
T73	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	59	0	0
T5	639068	2	0	0
T15	593241	0	0	0
T16	524315	0	0	0
T17	399318	0	0	0
T25	28330	0	0	0
T27	0	1	0	0
T45	377447	0	0	0
T50	0	1	0	0
T51	0	3	0	0
T53	0	1	0	0
T56	0	1	0	0
T57	0	6	0	0
T63	40214	0	0	0
T64	44741	0	0	0
T65	33533	0	0	0
T66	14389	0	0	0
T69	0	1	0	0
T79	0	1	0	0
T80	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	1062	0	0
T7	112155	356	0	0
T8	0	272	0	0
T9	0	139	0	0
T32	0	130	0	0
T33	0	165	0	0
T34	10240	0	0	0
T35	192575	0	0	0
T36	8826	0	0	0
T37	110555	0	0	0
T38	87614	0	0	0
T39	351790	0	0	0
T40	250869	0	0	0
T41	60764	0	0	0
T42	75608	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	852	0	0
T7	112155	296	0	0
T8	0	212	0	0
T9	0	109	0	0
T32	0	100	0	0
T33	0	135	0	0
T34	10240	0	0	0
T35	192575	0	0	0
T36	8826	0	0	0
T37	110555	0	0	0
T38	87614	0	0	0
T39	351790	0	0	0
T40	250869	0	0	0
T41	60764	0	0	0
T42	75608	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634178609	634110406	0	0
T1	7777	7681	0	0
T2	125712	125705	0	0
T3	137908	137836	0	0
T6	125667	125657	0	0
T10	49640	49577	0	0
T11	35476	35389	0	0
T12	23692	23620	0	0
T18	79083	78988	0	0
T19	55709	55647	0	0
T20	28744	28677	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	634271311	0	0
T1	7777	7681	0	0
T2	125712	125705	0	0
T3	137908	137836	0	0
T6	125667	125657	0	0
T10	49640	49577	0	0
T11	35476	35389	0	0
T12	23692	23620	0	0
T18	79083	78988	0	0
T19	55709	55647	0	0
T20	28744	28677	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T10

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T22
1	1	1	Covered	T2,T3,T18

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T10,T12
1	0	1	Covered	T18,T24,T14
1	1	0	Covered	T3,T11,T19
1	1	1	Covered	T3,T10,T12

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T12
0	1	Covered	T3,T10,T12
1	0	Covered	T4,T25,T17

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T10,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T25,T17

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Not Covered
1	1	Covered	T3,T10,T12

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T3,T10,T18

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T12
1	Covered	T2,T19,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T3,T12,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T3,T4,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T10,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T10
Phase1St	198	Covered	T2,T3,T10
Phase2St	215	Covered	T2,T3,T10
Phase3St	233	Covered	T2,T3,T10
TerminalSt	249	Covered	T2,T3,T10
TimeoutSt	159	Covered	T3,T10,T12

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T2,T3,T18
IdleSt->TimeoutSt	159	Covered	T3,T10,T12
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T99,T100,T101
Phase0St->Phase1St	198	Covered	T2,T3,T10
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T51,T102,T103
Phase1St->Phase2St	215	Covered	T2,T3,T10
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T3,T5,T104
Phase2St->Phase3St	233	Covered	T2,T3,T10
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T105,T39,T106
Phase3St->TerminalSt	249	Covered	T2,T3,T10
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T3,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T4,T5
TimeoutSt->Phase0St	172	Covered	T3,T10,T12

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T18
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T12
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T12
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T12
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T99,T100,T107
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T10
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T10
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T51,T102,T103
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T10
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T10
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T5,T104
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T10
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T105,T39,T106
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T10
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	634428730	185	0	0
CheckAccumTrig0_A	634428730	451	0	0
CheckAccumTrig1_A	634428730	16	0	0
CheckClr_A	634428730	183	0	0
CheckEn_A	634179977	283635584	0	0
CheckPhase0_A	634428730	519	0	0
CheckPhase1_A	634428730	514	0	0
CheckPhase2_A	634428730	511	0	0
CheckPhase3_A	634428730	507	0	0
CheckTimeout0_A	634428730	1344	0	0
CheckTimeoutSt1_A	634428730	131120	0	0
CheckTimeoutSt2_A	634428730	1269	0	0
CheckTimeoutStTrig_A	634428730	58	0	0
ErrorStAllEscAsserted_A	634428730	1089	0	0
ErrorStIsTerminal_A	634428730	879	0	0
EscStateOut_A	634178609	634110406	0	0
u_state_regs_A	634428730	634271311	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	185	0	0
T7	112155	58	0	0
T8	0	58	0	0
T9	0	23	0	0
T32	0	13	0	0
T33	0	33	0	0
T34	10240	0	0	0
T35	192575	0	0	0
T36	8826	0	0	0
T37	110555	0	0	0
T38	87614	0	0	0
T39	351790	0	0	0
T40	250869	0	0	0
T41	60764	0	0	0
T42	75608	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	451	0	0
T2	125712	2	0	0
T3	137908	12	0	0
T4	0	4	0	0
T5	0	5	0	0
T6	125667	0	0	0
T10	49640	0	0	0
T11	35476	0	0	0
T12	23692	0	0	0
T17	0	2	0	0
T18	79083	1	0	0
T19	55709	1	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	16	0	0
T4	923657	1	0	0
T5	639068	0	0	0
T15	593241	0	0	0
T16	524315	0	0	0
T17	399318	1	0	0
T25	28330	1	0	0
T31	0	1	0	0
T44	17313	0	0	0
T48	0	1	0	0
T51	0	1	0	0
T63	40214	0	0	0
T64	44741	0	0	0
T65	33533	0	0	0
T99	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	183	0	0
T2	125712	1	0	0
T3	137908	8	0	0
T4	0	2	0	0
T5	0	2	0	0
T6	125667	0	0	0
T10	49640	0	0	0
T11	35476	0	0	0
T12	23692	0	0	0
T17	0	1	0	0
T18	79083	0	0	0
T19	55709	0	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T70	0	1	0	0
T72	0	1	0	0
T104	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634179977	283635584	0	0
T1	7777	7680	0	0
T2	125712	1724	0	0
T3	137908	107086	0	0
T6	125667	125657	0	0
T10	49640	7506	0	0
T11	35476	35388	0	0
T12	23692	3158	0	0
T18	79083	18966	0	0
T19	55709	11630	0	0
T20	28744	28676	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	519	0	0
T2	125712	2	0	0
T3	137908	13	0	0
T4	0	7	0	0
T5	0	5	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	0	0	0
T12	23692	1	0	0
T18	79083	1	0	0
T19	55709	1	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T25	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	514	0	0
T2	125712	2	0	0
T3	137908	13	0	0
T4	0	7	0	0
T5	0	5	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	0	0	0
T12	23692	1	0	0
T18	79083	1	0	0
T19	55709	1	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T25	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	511	0	0
T2	125712	2	0	0
T3	137908	12	0	0
T4	0	7	0	0
T5	0	4	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	0	0	0
T12	23692	1	0	0
T18	79083	1	0	0
T19	55709	1	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T25	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	507	0	0
T2	125712	2	0	0
T3	137908	12	0	0
T4	0	7	0	0
T5	0	4	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	0	0	0
T12	23692	1	0	0
T18	79083	1	0	0
T19	55709	1	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T25	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	1344	0	0
T3	137908	7	0	0
T4	0	15	0	0
T5	0	3	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	0	0	0
T12	23692	1	0	0
T17	0	80	0	0
T18	79083	0	0	0
T19	55709	0	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T24	13453	0	0	0
T25	0	1	0	0
T31	0	1	0	0
T47	0	1	0	0
T66	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	131120	0	0
T3	137908	323	0	0
T4	0	1643	0	0
T5	0	606	0	0
T6	125667	0	0	0
T10	49640	59	0	0
T11	35476	0	0	0
T12	23692	794	0	0
T17	0	4080	0	0
T18	79083	0	0	0
T19	55709	0	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T24	13453	0	0	0
T25	0	2	0	0
T47	0	468	0	0
T66	0	123	0	0
T74	0	118	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	1269	0	0
T3	137908	6	0	0
T4	0	12	0	0
T5	0	3	0	0
T6	125667	0	0	0
T10	49640	0	0	0
T11	35476	0	0	0
T12	23692	0	0	0
T17	0	79	0	0
T18	79083	0	0	0
T19	55709	0	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T24	13453	0	0	0
T48	0	2	0	0
T66	0	1	0	0
T73	0	2	0	0
T75	0	1	0	0
T76	0	8	0	0
T77	0	10	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	58	0	0
T3	137908	1	0	0
T4	0	2	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	0	0	0
T12	23692	1	0	0
T18	79083	0	0	0
T19	55709	0	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T24	13453	0	0	0
T47	0	1	0	0
T72	0	1	0	0
T74	0	1	0	0
T78	0	1	0	0
T93	0	1	0	0
T113	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	1089	0	0
T7	112155	291	0	0
T8	0	298	0	0
T9	0	163	0	0
T32	0	163	0	0
T33	0	174	0	0
T34	10240	0	0	0
T35	192575	0	0	0
T36	8826	0	0	0
T37	110555	0	0	0
T38	87614	0	0	0
T39	351790	0	0	0
T40	250869	0	0	0
T41	60764	0	0	0
T42	75608	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	879	0	0
T7	112155	231	0	0
T8	0	238	0	0
T9	0	133	0	0
T32	0	133	0	0
T33	0	144	0	0
T34	10240	0	0	0
T35	192575	0	0	0
T36	8826	0	0	0
T37	110555	0	0	0
T38	87614	0	0	0
T39	351790	0	0	0
T40	250869	0	0	0
T41	60764	0	0	0
T42	75608	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634178609	634110406	0	0
T1	7777	7681	0	0
T2	125712	125705	0	0
T3	137908	137836	0	0
T6	125667	125657	0	0
T10	49640	49577	0	0
T11	35476	35389	0	0
T12	23692	23620	0	0
T18	79083	78988	0	0
T19	55709	55647	0	0
T20	28744	28677	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	634271311	0	0
T1	7777	7681	0	0
T2	125712	125705	0	0
T3	137908	137836	0	0
T6	125667	125657	0	0
T10	49640	49577	0	0
T11	35476	35389	0	0
T12	23692	23620	0	0
T18	79083	78988	0	0
T19	55709	55647	0	0
T20	28744	28677	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T23
1	1	1	Covered	T2,T3,T11

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T11,T10
1	0	1	Covered	T18,T4,T5
1	1	0	Covered	T3,T20,T4
1	1	1	Covered	T3,T12,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T4
0	1	Covered	T12,T4,T5
1	0	Covered	T4,T47,T31

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T12,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T47,T31

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T4
1	0	Covered	T26,T27
1	1	Covered	T12,T4,T5

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T12,T20,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T11,T10
1	Covered	T2,T3,T12

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T3,T10,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T11,T19,T21

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T11,T10

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T11
Phase1St	198	Covered	T2,T3,T11
Phase2St	215	Covered	T2,T3,T11
Phase3St	233	Covered	T2,T3,T11
TerminalSt	249	Covered	T2,T3,T11
TimeoutSt	159	Covered	T3,T12,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T2,T3,T11
IdleSt->TimeoutSt	159	Covered	T3,T12,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T5,T29,T30
Phase0St->Phase1St	198	Covered	T2,T3,T11
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T20,T4,T17
Phase1St->Phase2St	215	Covered	T2,T3,T11
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T3,T4,T5
Phase2St->Phase3St	233	Covered	T2,T3,T11
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T5,T31,T72
Phase3St->TerminalSt	249	Covered	T2,T3,T11
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T12,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T12,T4
TimeoutSt->Phase0St	172	Covered	T12,T4,T5

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T4,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T29,T30
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T4,T17
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T31,T50
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T12,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	634428730	185	0	0
CheckAccumTrig0_A	634428730	836	0	0
CheckAccumTrig1_A	634428730	38	0	0
CheckClr_A	634428730	441	0	0
CheckEn_A	634179977	241855191	0	0
CheckPhase0_A	634428730	939	0	0
CheckPhase1_A	634428730	909	0	0
CheckPhase2_A	634428730	884	0	0
CheckPhase3_A	634428730	869	0	0
CheckTimeout0_A	634428730	2413	0	0
CheckTimeoutSt1_A	634428730	196865	0	0
CheckTimeoutSt2_A	634428730	2293	0	0
CheckTimeoutStTrig_A	634428730	82	0	0
ErrorStAllEscAsserted_A	634428730	1089	0	0
ErrorStIsTerminal_A	634428730	879	0	0
EscStateOut_A	634178609	634110406	0	0
u_state_regs_A	634428730	634271311	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	185	0	0
T7	112155	48	0	0
T8	0	65	0	0
T9	0	22	0	0
T32	0	24	0	0
T33	0	26	0	0
T34	10240	0	0	0
T35	192575	0	0	0
T36	8826	0	0	0
T37	110555	0	0	0
T38	87614	0	0	0
T39	351790	0	0	0
T40	250869	0	0	0
T41	60764	0	0	0
T42	75608	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	836	0	0
T2	125712	1	0	0
T3	137908	10	0	0
T4	0	6	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	1	0	0
T12	23692	1	0	0
T18	79083	1	0	0
T19	55709	1	0	0
T20	28744	3	0	0
T21	5886	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	38	0	0
T4	923657	1	0	0
T5	639068	0	0	0
T15	593241	0	0	0
T16	524315	0	0	0
T17	399318	0	0	0
T25	28330	0	0	0
T31	0	1	0	0
T44	17313	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T63	40214	0	0	0
T64	44741	0	0	0
T65	33533	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	441	0	0
T3	137908	6	0	0
T4	0	5	0	0
T5	0	18	0	0
T6	125667	0	0	0
T10	49640	0	0	0
T11	35476	0	0	0
T12	23692	1	0	0
T17	0	2	0	0
T18	79083	0	0	0
T19	55709	0	0	0
T20	28744	2	0	0
T21	5886	1	0	0
T24	13453	0	0	0
T63	0	1	0	0
T65	0	1	0	0
T67	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634179977	241855191	0	0
T1	7777	7680	0	0
T2	125712	997	0	0
T3	137908	110282	0	0
T6	125667	125657	0	0
T10	49640	10876	0	0
T11	35476	3065	0	0
T12	23692	3106	0	0
T18	79083	582	0	0
T19	55709	6008	0	0
T20	28744	8813	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	939	0	0
T2	125712	1	0	0
T3	137908	10	0	0
T4	0	10	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	1	0	0
T12	23692	2	0	0
T18	79083	1	0	0
T19	55709	1	0	0
T20	28744	3	0	0
T21	5886	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	909	0	0
T2	125712	1	0	0
T3	137908	10	0	0
T4	0	8	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	1	0	0
T12	23692	2	0	0
T18	79083	1	0	0
T19	55709	1	0	0
T20	28744	2	0	0
T21	5886	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	884	0	0
T2	125712	1	0	0
T3	137908	9	0	0
T4	0	7	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	1	0	0
T12	23692	2	0	0
T18	79083	1	0	0
T19	55709	1	0	0
T20	28744	2	0	0
T21	5886	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	869	0	0
T2	125712	1	0	0
T3	137908	9	0	0
T4	0	7	0	0
T6	125667	0	0	0
T10	49640	1	0	0
T11	35476	1	0	0
T12	23692	2	0	0
T18	79083	1	0	0
T19	55709	1	0	0
T20	28744	2	0	0
T21	5886	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	2413	0	0
T3	137908	5	0	0
T4	0	217	0	0
T5	0	32	0	0
T6	125667	0	0	0
T10	49640	0	0	0
T11	35476	0	0	0
T12	23692	2	0	0
T17	0	5	0	0
T18	79083	0	0	0
T19	55709	0	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T24	13453	0	0	0
T29	0	1	0	0
T31	0	2	0	0
T47	0	2	0	0
T66	0	1	0	0
T69	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	196865	0	0
T3	137908	330	0	0
T4	0	14147	0	0
T5	0	3457	0	0
T6	125667	0	0	0
T10	49640	0	0	0
T11	35476	0	0	0
T12	23692	499	0	0
T17	0	277	0	0
T18	79083	0	0	0
T19	55709	0	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T24	13453	0	0	0
T29	0	45	0	0
T31	0	120	0	0
T47	0	20	0	0
T66	0	131	0	0
T69	0	124	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	2293	0	0
T3	137908	5	0	0
T4	0	213	0	0
T5	0	18	0	0
T6	125667	0	0	0
T10	49640	0	0	0
T11	35476	0	0	0
T12	23692	1	0	0
T17	0	3	0	0
T18	79083	0	0	0
T19	55709	0	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T24	13453	0	0	0
T29	0	1	0	0
T31	0	1	0	0
T47	0	1	0	0
T66	0	1	0	0
T73	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	82	0	0
T4	0	3	0	0
T5	0	14	0	0
T6	125667	0	0	0
T12	23692	1	0	0
T13	512755	0	0	0
T14	372589	0	0	0
T17	0	2	0	0
T18	79083	0	0	0
T19	55709	0	0	0
T20	28744	0	0	0
T21	5886	0	0	0
T24	13453	0	0	0
T30	0	1	0	0
T43	3351	0	0	0
T48	0	1	0	0
T69	0	2	0	0
T73	0	1	0	0
T75	0	1	0	0
T78	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	1089	0	0
T7	112155	327	0	0
T8	0	285	0	0
T9	0	161	0	0
T32	0	141	0	0
T33	0	175	0	0
T34	10240	0	0	0
T35	192575	0	0	0
T36	8826	0	0	0
T37	110555	0	0	0
T38	87614	0	0	0
T39	351790	0	0	0
T40	250869	0	0	0
T41	60764	0	0	0
T42	75608	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	879	0	0
T7	112155	267	0	0
T8	0	225	0	0
T9	0	131	0	0
T32	0	111	0	0
T33	0	145	0	0
T34	10240	0	0	0
T35	192575	0	0	0
T36	8826	0	0	0
T37	110555	0	0	0
T38	87614	0	0	0
T39	351790	0	0	0
T40	250869	0	0	0
T41	60764	0	0	0
T42	75608	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634178609	634110406	0	0
T1	7777	7681	0	0
T2	125712	125705	0	0
T3	137908	137836	0	0
T6	125667	125657	0	0
T10	49640	49577	0	0
T11	35476	35389	0	0
T12	23692	23620	0	0
T18	79083	78988	0	0
T19	55709	55647	0	0
T20	28744	28677	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634428730	634271311	0	0
T1	7777	7681	0	0
T2	125712	125705	0	0
T3	137908	137836	0	0
T6	125667	125657	0	0
T10	49640	49577	0	0
T11	35476	35389	0	0
T12	23692	23620	0	0
T18	79083	78988	0	0
T19	55709	55647	0	0
T20	28744	28677	0	0