Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T86,T217,T218
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T7

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12868	0	0
DisabledNoTrigBkwd_A	2147483647	886366	0	0
DisabledNoTrigFwd_A	2147483647	1377358512	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12868	0	0
T9	17841	0	0	0
T39	580954	0	0	0
T40	232496	0	0	0
T41	288949	0	0	0
T42	55194	0	0	0
T43	323431	0	0	0
T44	87132	0	0	0
T45	114862	0	0	0
T46	37186	0	0	0
T86	0	310	0	0
T120	13884	0	0	0
T217	2795	351	0	0
T218	0	484	0	0
T219	0	587	0	0
T220	2993	647	0	0
T221	8018	678	0	0
T222	0	197	0	0
T223	0	710	0	0
T224	0	817	0	0
T225	0	908	0	0
T226	0	661	0	0
T227	0	810	0	0
T228	0	361	0	0
T229	0	801	0	0
T230	0	1118	0	0
T231	0	202	0	0
T232	0	632	0	0
T233	0	1039	0	0
T234	0	880	0	0
T235	0	675	0	0
T236	20079	0	0	0
T237	13573	0	0	0
T238	3176	0	0	0
T239	955615	0	0	0
T240	384106	0	0	0
T241	116512	0	0	0
T242	8936	0	0	0
T243	17739	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	886366	0	0
T1	113955	260	0	0
T2	86649	0	0	0
T3	62788	7	0	0
T4	28008	0	0	0
T5	0	110	0	0
T6	0	6154	0	0
T7	502872	10	0	0
T8	3365848	6699	0	0
T12	146468	1	0	0
T13	7780	1	0	0
T14	100364	0	0	0
T15	0	1	0	0
T16	0	368	0	0
T17	0	9	0	0
T18	0	3	0	0
T19	0	2273	0	0
T20	0	25	0	0
T21	463096	0	0	0
T22	144782	279	0	0
T23	41506	474	0	0
T24	0	13	0	0
T35	0	11	0	0
T48	0	29	0	0
T49	0	4	0	0
T86	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1377358512	0	0
T1	151940	94621	0	0
T2	115532	85822	0	0
T3	62788	47487	0	0
T4	28008	3144	0	0
T7	502872	457257	0	0
T8	3365848	1689132	0	0
T12	146468	111837	0	0
T13	7780	5024	0	0
T14	100364	43877	0	0
T21	463096	127672	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T3,T8

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T217,T219,T223
1	1	Covered	T1,T3,T8

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	662233319	3302	0	0
DisabledNoTrigBkwd_A	662233319	217419	0	0
DisabledNoTrigFwd_A	662233319	335170915	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	3302	0	0
T9	17841	0	0	0
T39	580954	0	0	0
T40	232496	0	0	0
T41	288949	0	0	0
T42	55194	0	0	0
T43	323431	0	0	0
T44	87132	0	0	0
T45	114862	0	0	0
T46	37186	0	0	0
T217	2795	351	0	0
T219	0	587	0	0
T223	0	710	0	0
T226	0	661	0	0
T228	0	361	0	0
T232	0	632	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	217419	0	0
T1	37985	76	0	0
T2	28883	0	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T5	0	40	0	0
T7	125718	0	0	0
T8	841462	1602	0	0
T12	36617	1	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T15	0	1	0	0
T19	0	976	0	0
T21	115774	0	0	0
T22	0	109	0	0
T23	0	8	0	0
T24	0	1	0	0
T48	0	29	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	335170915	0	0
T1	37985	3041	0	0
T2	28883	28794	0	0
T3	15697	14261	0	0
T4	7002	780	0	0
T7	125718	114359	0	0
T8	841462	8970	0	0
T12	36617	19033	0	0
T13	1945	1894	0	0
T14	25091	9827	0	0
T21	115774	3066	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T220,T225,T231
1	1	Covered	T1,T3,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	662233319	3312	0	0
DisabledNoTrigBkwd_A	662233319	245346	0	0
DisabledNoTrigFwd_A	662233319	336019442	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	3312	0	0
T120	13884	0	0	0
T220	2993	647	0	0
T221	4009	0	0	0
T225	0	908	0	0
T231	0	202	0	0
T234	0	880	0	0
T235	0	675	0	0
T236	20079	0	0	0
T237	13573	0	0	0
T238	3176	0	0	0
T239	955615	0	0	0
T240	384106	0	0	0
T241	58256	0	0	0
T242	4468	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	245346	0	0
T1	37985	2	0	0
T2	28883	0	0	0
T3	15697	5	0	0
T4	7002	0	0	0
T7	125718	0	0	0
T8	841462	3	0	0
T12	36617	0	0	0
T13	1945	1	0	0
T14	25091	0	0	0
T17	0	9	0	0
T18	0	3	0	0
T19	0	19	0	0
T21	115774	0	0	0
T22	0	144	0	0
T23	0	17	0	0
T24	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	336019442	0	0
T1	37985	21652	0	0
T2	28883	28794	0	0
T3	15697	4599	0	0
T4	7002	784	0	0
T7	125718	10018	0	0
T8	841462	840367	0	0
T12	36617	28137	0	0
T13	1945	616	0	0
T14	25091	10069	0	0
T21	115774	85338	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T13

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T221,T222,T224
1	1	Covered	T1,T2,T13

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T22

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	662233319	3541	0	0
DisabledNoTrigBkwd_A	662233319	187846	0	0
DisabledNoTrigFwd_A	662233319	381997006	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	3541	0	0
T26	38940	0	0	0
T221	4009	678	0	0
T222	0	197	0	0
T224	0	817	0	0
T227	0	810	0	0
T233	0	1039	0	0
T241	58256	0	0	0
T242	4468	0	0	0
T243	17739	0	0	0
T244	61694	0	0	0
T245	21464	0	0	0
T246	38850	0	0	0
T247	8084	0	0	0
T248	529511	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	187846	0	0
T1	37985	182	0	0
T2	28883	0	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T5	0	67	0	0
T6	0	474	0	0
T7	125718	0	0	0
T8	841462	5087	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T16	0	368	0	0
T19	0	1278	0	0
T20	0	15	0	0
T21	115774	0	0	0
T22	0	26	0	0
T35	0	8	0	0
T49	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	381997006	0	0
T1	37985	32030	0	0
T2	28883	597	0	0
T3	15697	15646	0	0
T4	7002	788	0	0
T7	125718	125713	0	0
T8	841462	2647	0	0
T12	36617	32746	0	0
T13	1945	620	0	0
T14	25091	10206	0	0
T21	115774	24557	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T86,T218,T229
1	1	Covered	T2,T3,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T8

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	662233319	2713	0	0
DisabledNoTrigBkwd_A	662233319	235755	0	0
DisabledNoTrigFwd_A	662233319	324171149	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	2713	0	0
T16	461866	0	0	0
T25	86737	0	0	0
T34	375275	0	0	0
T35	42559	0	0	0
T49	73184	0	0	0
T65	306986	0	0	0
T66	411882	0	0	0
T67	79233	0	0	0
T86	1132	310	0	0
T124	21791	0	0	0
T218	0	484	0	0
T229	0	801	0	0
T230	0	1118	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	235755	0	0
T3	15697	2	0	0
T4	7002	0	0	0
T5	0	3	0	0
T6	0	5680	0	0
T7	125718	10	0	0
T8	841462	7	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T20	0	10	0	0
T21	115774	0	0	0
T22	144782	0	0	0
T23	41506	449	0	0
T24	0	7	0	0
T35	0	3	0	0
T86	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	324171149	0	0
T1	37985	37898	0	0
T2	28883	27637	0	0
T3	15697	12981	0	0
T4	7002	792	0	0
T7	125718	207167	0	0
T8	841462	837148	0	0
T12	36617	31921	0	0
T13	1945	1894	0	0
T14	25091	13775	0	0
T21	115774	14711	0	0