Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T22,T15
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T12,T14
1	0	Covered	T1,T6,T25

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T6,T25

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T3,T12,T14

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T13
1	Covered	T8,T21,T22

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T14,T23

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T13,T8
1	Covered	T1,T3,T8

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T13,T8,T12

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T13,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T13,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T13,T8

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T7
Phase1St	198	Covered	T1,T3,T7
Phase2St	215	Covered	T1,T3,T7
Phase3St	233	Covered	T1,T3,T7
TerminalSt	249	Covered	T1,T3,T7
TimeoutSt	159	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T3,T7
IdleSt->TimeoutSt	159	Covered	T1,T2,T3
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T6,T29,T30
Phase0St->Phase1St	198	Covered	T1,T3,T7
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T25,T31,T30
Phase1St->Phase2St	215	Covered	T1,T3,T7
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T14,T5,T32
Phase2St->Phase3St	233	Covered	T1,T3,T7
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T33,T34,T25
Phase3St->TerminalSt	249	Covered	T1,T3,T7
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T8,T21
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T14,T21
TimeoutSt->Phase0St	172	Covered	T1,T3,T12

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T12
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T14,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T35,T30,T36
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T25,T31,T30
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T14,T5,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T34,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T8,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	782	0	0
CheckAccumTrig0_A	2147483647	2274	0	0
CheckAccumTrig1_A	2147483647	116	0	0
CheckClr_A	2147483647	1002	0	0
CheckEn_A	2147483647	1057251626	0	0
CheckPhase0_A	2147483647	2588	0	0
CheckPhase1_A	2147483647	2540	0	0
CheckPhase2_A	2147483647	2486	0	0
CheckPhase3_A	2147483647	2437	0	0
CheckTimeout0_A	2147483647	5255	0	0
CheckTimeoutSt1_A	2147483647	519362	0	0
CheckTimeoutSt2_A	2147483647	4895	0	0
CheckTimeoutStTrig_A	2147483647	242	0	0
ErrorStAllEscAsserted_A	2147483647	4560	0	0
ErrorStIsTerminal_A	2147483647	3720	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	782	0	0
T9	71364	95	0	0
T10	0	230	0	0
T11	0	101	0	0
T37	0	227	0	0
T38	0	129	0	0
T39	2323816	0	0	0
T40	929984	0	0	0
T41	1155796	0	0	0
T42	220776	0	0	0
T43	1293724	0	0	0
T44	348528	0	0	0
T45	459448	0	0	0
T46	148744	0	0	0
T47	1564204	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2274	0	0
T1	75970	5	0	0
T2	57766	0	0	0
T3	47091	1	0	0
T4	21006	0	0	0
T5	0	12	0	0
T6	0	8	0	0
T7	377154	1	0	0
T8	3365848	5	0	0
T12	146468	0	0	0
T13	5835	1	0	0
T14	100364	0	0	0
T15	124038	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	448626	3	0	0
T20	0	2	0	0
T21	463096	0	0	0
T22	289564	3	0	0
T23	83012	4	0	0
T24	11291	3	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	2	0	0
T48	21113	1	0	0
T49	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	116	0	0
T1	37985	1	0	0
T6	0	1	0	0
T25	86737	1	0	0
T30	0	2	0	0
T39	0	2	0	0
T43	0	1	0	0
T50	539850	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	4	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	306986	0	0	0
T66	411882	0	0	0
T67	79233	0	0	0
T68	83743	0	0	0
T69	904317	0	0	0
T70	24033	0	0	0
T71	23714	0	0	0
T72	39398	0	0	0
T73	365388	0	0	0
T74	68038	0	0	0
T75	31145	0	0	0
T76	24623	0	0	0
T77	349079	0	0	0
T78	64344	0	0	0
T79	207908	0	0	0
T80	261201	0	0	0
T81	37597	0	0	0
T82	65285	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1002	0	0
T1	75970	4	0	0
T2	57766	0	0	0
T3	31394	0	0	0
T4	14004	0	0	0
T5	509076	3	0	0
T6	0	5	0	0
T7	251436	0	0	0
T8	2524386	1	0	0
T12	109851	0	0	0
T13	3890	0	0	0
T14	75273	1	0	0
T15	248076	0	0	0
T17	107703	0	0	0
T18	843394	0	0	0
T19	897252	0	0	0
T20	117554	0	0	0
T21	347322	1	0	0
T22	144782	0	0	0
T23	83012	3	0	0
T24	22582	0	0	0
T25	0	2	0	0
T32	0	10	0	0
T33	27138	1	0	0
T34	0	2	0	0
T48	42226	0	0	0
T49	0	6	0	0
T50	0	1	0	0
T67	0	4	0	0
T70	0	1	0	0
T74	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T83	0	3	0	0
T84	0	2	0	0
T85	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1057251626	0	0
T1	151940	63284	0	0
T2	115532	85819	0	0
T3	62788	41024	0	0
T4	28008	3140	0	0
T7	502872	328185	0	0
T8	3365848	1681961	0	0
T12	146468	98686	0	0
T13	7780	5022	0	0
T14	100364	43876	0	0
T21	463096	127671	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2588	0	0
T1	113955	6	0	0
T2	86649	0	0	0
T3	62788	2	0	0
T4	28008	0	0	0
T5	0	4	0	0
T6	0	9	0	0
T7	502872	1	0	0
T8	3365848	5	0	0
T12	146468	1	0	0
T13	7780	1	0	0
T14	100364	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	0	3	0	0
T20	0	2	0	0
T21	463096	1	0	0
T22	144782	3	0	0
T23	41506	8	0	0
T24	0	3	0	0
T35	0	2	0	0
T48	0	1	0	0
T86	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2540	0	0
T1	113955	6	0	0
T2	86649	0	0	0
T3	62788	2	0	0
T4	28008	0	0	0
T5	0	4	0	0
T6	0	9	0	0
T7	502872	1	0	0
T8	3365848	5	0	0
T12	146468	1	0	0
T13	7780	1	0	0
T14	100364	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	0	3	0	0
T20	0	2	0	0
T21	463096	1	0	0
T22	144782	3	0	0
T23	41506	8	0	0
T24	0	3	0	0
T35	0	2	0	0
T48	0	1	0	0
T86	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2486	0	0
T1	113955	6	0	0
T2	86649	0	0	0
T3	62788	2	0	0
T4	28008	0	0	0
T5	0	9	0	0
T6	0	9	0	0
T7	502872	1	0	0
T8	3365848	5	0	0
T12	146468	1	0	0
T13	7780	1	0	0
T14	100364	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	0	3	0	0
T20	0	2	0	0
T21	463096	1	0	0
T22	144782	3	0	0
T23	41506	8	0	0
T24	0	3	0	0
T35	0	2	0	0
T48	0	1	0	0
T86	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2437	0	0
T1	113955	6	0	0
T2	86649	0	0	0
T3	62788	2	0	0
T4	28008	0	0	0
T5	0	9	0	0
T6	0	9	0	0
T7	502872	1	0	0
T8	3365848	5	0	0
T12	146468	1	0	0
T13	7780	1	0	0
T14	100364	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	0	3	0	0
T20	0	2	0	0
T21	463096	1	0	0
T22	144782	3	0	0
T23	41506	8	0	0
T24	0	3	0	0
T35	0	2	0	0
T48	0	1	0	0
T86	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5255	0	0
T1	37985	1	0	0
T2	57766	9	0	0
T3	47091	1	0	0
T4	21006	0	0	0
T5	0	1	0	0
T6	0	4	0	0
T7	377154	0	0	0
T8	2524386	0	0	0
T12	146468	1	0	0
T13	5835	0	0	0
T14	100364	7	0	0
T15	124038	0	0	0
T17	107703	0	0	0
T19	448626	0	0	0
T21	463096	19	0	0
T22	434346	0	0	0
T23	83012	7	0	0
T24	11291	1	0	0
T25	0	1	0	0
T33	0	1	0	0
T35	0	2	0	0
T48	21113	0	0	0
T49	0	1	0	0
T50	0	28	0	0
T67	0	4	0	0
T69	0	251	0	0
T70	0	1	0	0
T83	0	3	0	0
T84	0	1	0	0
T87	0	23	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	519362	0	0
T1	37985	260	0	0
T2	57766	1395	0	0
T3	47091	220	0	0
T4	21006	0	0	0
T5	0	45	0	0
T6	0	755	0	0
T7	377154	0	0	0
T8	2524386	0	0	0
T12	146468	192	0	0
T13	5835	0	0	0
T14	100364	896	0	0
T15	124038	0	0	0
T17	107703	0	0	0
T19	448626	0	0	0
T21	463096	3267	0	0
T22	434346	0	0	0
T23	83012	712	0	0
T24	11291	39	0	0
T25	0	9	0	0
T33	0	86	0	0
T48	21113	0	0	0
T49	0	157	0	0
T50	0	4166	0	0
T67	0	323	0	0
T69	0	9283	0	0
T70	0	22	0	0
T74	0	25	0	0
T83	0	1035	0	0
T84	0	103	0	0
T87	0	1582	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4895	0	0
T2	57766	9	0	0
T3	31394	0	0	0
T4	14004	0	0	0
T5	509076	1	0	0
T6	0	3	0	0
T7	251436	0	0	0
T8	1682924	0	0	0
T12	73234	0	0	0
T13	3890	0	0	0
T14	75273	6	0	0
T15	248076	0	0	0
T17	215406	0	0	0
T18	1686788	0	0	0
T19	897252	0	0	0
T21	463096	18	0	0
T22	579128	0	0	0
T23	83012	3	0	0
T24	22582	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T48	42226	0	0	0
T49	0	1	0	0
T50	0	29	0	0
T51	0	2	0	0
T67	0	2	0	0
T69	0	251	0	0
T70	0	1	0	0
T74	0	2	0	0
T81	0	2	0	0
T82	0	4	0	0
T83	0	1	0	0
T84	0	2	0	0
T87	0	22	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	242	0	0
T3	15697	1	0	0
T4	7002	0	0	0
T5	1018152	0	0	0
T7	125718	0	0	0
T8	841462	0	0	0
T12	73234	1	0	0
T13	1945	0	0	0
T14	50182	1	0	0
T15	372114	0	0	0
T17	323109	0	0	0
T18	1686788	0	0	0
T19	1345878	0	0	0
T20	235108	0	0	0
T21	231548	1	0	0
T22	289564	0	0	0
T23	166024	2	0	0
T24	33873	0	0	0
T29	0	3	0	0
T30	0	2	0	0
T33	54276	0	0	0
T36	0	1	0	0
T48	63339	0	0	0
T50	0	3	0	0
T53	0	2	0	0
T56	0	2	0	0
T58	0	1	0	0
T67	0	2	0	0
T82	0	2	0	0
T83	0	2	0	0
T84	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	2	0	0
T91	0	1	0	0
T92	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4560	0	0
T9	71364	620	0	0
T10	0	1339	0	0
T11	0	641	0	0
T37	0	1327	0	0
T38	0	633	0	0
T39	2323816	0	0	0
T40	929984	0	0	0
T41	1155796	0	0	0
T42	220776	0	0	0
T43	1293724	0	0	0
T44	348528	0	0	0
T45	459448	0	0	0
T46	148744	0	0	0
T47	1564204	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3720	0	0
T9	71364	500	0	0
T10	0	1099	0	0
T11	0	521	0	0
T37	0	1087	0	0
T38	0	513	0	0
T39	2323816	0	0	0
T40	929984	0	0	0
T41	1155796	0	0	0
T42	220776	0	0	0
T43	1293724	0	0	0
T44	348528	0	0	0
T45	459448	0	0	0
T46	148744	0	0	0
T47	1564204	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	151940	151592	0	0
T2	115532	115176	0	0
T3	62788	62584	0	0
T4	28008	27456	0	0
T7	502872	502852	0	0
T8	3365848	3365572	0	0
T12	146468	146140	0	0
T13	7780	7576	0	0
T14	100364	100020	0	0
T21	463096	462732	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	151940	151592	0	0
T2	115532	115176	0	0
T3	62788	62584	0	0
T4	28008	27456	0	0
T7	502872	502852	0	0
T8	3365848	3365572	0	0
T12	146468	146140	0	0
T13	7780	7576	0	0
T14	100364	100020	0	0
T21	463096	462732	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T8,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T8,T22

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T8
1	0	1	Covered	T22,T5,T20
1	1	0	Covered	T2,T3,T19
1	1	1	Covered	T12,T14,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T21
0	1	Covered	T12,T14,T23
1	0	Covered	T25,T51,T52

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T14,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T25,T51,T52

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T21
1	0	Not Covered
1	1	Covered	T12,T14,T23

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T12,T14
1	Covered	T8,T24,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T8,T12
1	Covered	T14,T19,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T8,T12,T14
1	Covered	T1,T22,T23

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T8,T22
1	Covered	T12,T15,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T8,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T22,T23,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T8,T12,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T12,T14,T23

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T8,T12
Phase1St	198	Covered	T1,T8,T12
Phase2St	215	Covered	T1,T8,T12
Phase3St	233	Covered	T1,T8,T12
TerminalSt	249	Covered	T1,T8,T12
TimeoutSt	159	Covered	T12,T14,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T8,T22
IdleSt->TimeoutSt	159	Covered	T12,T14,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T29,T93
Phase0St->Phase1St	198	Covered	T1,T8,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T25,T31,T94
Phase1St->Phase2St	215	Covered	T1,T8,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T14,T5,T95
Phase2St->Phase3St	233	Covered	T1,T8,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T33,T34,T25
Phase3St->TerminalSt	249	Covered	T1,T8,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T23,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T21,T24,T33
TimeoutSt->Phase0St	172	Covered	T12,T14,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T22
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T21,T24,T33
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T93,T96,T39
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T8,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T8,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T25,T31,T94
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T8,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T12,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T14,T5,T95
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T8,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T8,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T34,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T8,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T8,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T23,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T8,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	662233319	173	0	0
CheckAccumTrig0_A	662233319	796	0	0
CheckAccumTrig1_A	662233319	56	0	0
CheckClr_A	662233319	384	0	0
CheckEn_A	662102540	253489053	0	0
CheckPhase0_A	662233319	904	0	0
CheckPhase1_A	662233319	888	0	0
CheckPhase2_A	662233319	867	0	0
CheckPhase3_A	662233319	848	0	0
CheckTimeout0_A	662233319	1269	0	0
CheckTimeoutSt1_A	662233319	139206	0	0
CheckTimeoutSt2_A	662233319	1137	0	0
CheckTimeoutStTrig_A	662233319	75	0	0
ErrorStAllEscAsserted_A	662233319	1072	0	0
ErrorStIsTerminal_A	662233319	862	0	0
EscStateOut_A	662101016	662030898	0	0
u_state_regs_A	662233319	662073766	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	173	0	0
T9	17841	29	0	0
T10	0	60	0	0
T11	0	15	0	0
T37	0	46	0	0
T38	0	23	0	0
T39	580954	0	0	0
T40	232496	0	0	0
T41	288949	0	0	0
T42	55194	0	0	0
T43	323431	0	0	0
T44	87132	0	0	0
T45	114862	0	0	0
T46	37186	0	0	0
T47	391051	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	796	0	0
T1	37985	3	0	0
T2	28883	0	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T5	0	6	0	0
T7	125718	0	0	0
T8	841462	1	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T15	0	1	0	0
T19	0	1	0	0
T21	115774	0	0	0
T22	0	1	0	0
T23	0	2	0	0
T24	0	1	0	0
T33	0	2	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	56	0	0
T25	86737	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	4	0	0
T59	0	1	0	0
T65	306986	0	0	0
T66	411882	0	0	0
T67	79233	0	0	0
T68	83743	0	0	0
T69	904317	0	0	0
T70	24033	0	0	0
T71	23714	0	0	0
T72	39398	0	0	0
T73	365388	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	384	0	0
T1	37985	3	0	0
T2	28883	0	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T5	0	3	0	0
T6	0	2	0	0
T7	125718	0	0	0
T8	841462	0	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	1	0	0
T21	115774	0	0	0
T23	0	2	0	0
T25	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T49	0	4	0	0
T83	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662102540	253489053	0	0
T1	37985	3041	0	0
T2	28883	28793	0	0
T3	15697	14260	0	0
T4	7002	779	0	0
T7	125718	114359	0	0
T8	841462	3794	0	0
T12	36617	5885	0	0
T13	1945	1893	0	0
T14	25091	9826	0	0
T21	115774	3066	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	904	0	0
T1	37985	3	0	0
T2	28883	0	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T7	125718	0	0	0
T8	841462	1	0	0
T12	36617	1	0	0
T13	1945	0	0	0
T14	25091	1	0	0
T15	0	1	0	0
T19	0	1	0	0
T21	115774	0	0	0
T22	0	1	0	0
T23	0	3	0	0
T24	0	1	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	888	0	0
T1	37985	3	0	0
T2	28883	0	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T7	125718	0	0	0
T8	841462	1	0	0
T12	36617	1	0	0
T13	1945	0	0	0
T14	25091	1	0	0
T15	0	1	0	0
T19	0	1	0	0
T21	115774	0	0	0
T22	0	1	0	0
T23	0	3	0	0
T24	0	1	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	867	0	0
T1	37985	3	0	0
T2	28883	0	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T5	0	5	0	0
T7	125718	0	0	0
T8	841462	1	0	0
T12	36617	1	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T15	0	1	0	0
T19	0	1	0	0
T21	115774	0	0	0
T22	0	1	0	0
T23	0	3	0	0
T24	0	1	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	848	0	0
T1	37985	3	0	0
T2	28883	0	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T5	0	5	0	0
T7	125718	0	0	0
T8	841462	1	0	0
T12	36617	1	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T15	0	1	0	0
T19	0	1	0	0
T21	115774	0	0	0
T22	0	1	0	0
T23	0	3	0	0
T24	0	1	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	1269	0	0
T12	36617	1	0	0
T14	25091	1	0	0
T15	124038	0	0	0
T17	107703	0	0	0
T19	448626	0	0	0
T21	115774	6	0	0
T22	144782	0	0	0
T23	41506	1	0	0
T24	11291	1	0	0
T25	0	1	0	0
T33	0	1	0	0
T48	21113	0	0	0
T49	0	1	0	0
T69	0	3	0	0
T87	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	139206	0	0
T12	36617	192	0	0
T14	25091	13	0	0
T15	124038	0	0	0
T17	107703	0	0	0
T19	448626	0	0	0
T21	115774	1093	0	0
T22	144782	0	0	0
T23	41506	38	0	0
T24	11291	39	0	0
T25	0	9	0	0
T33	0	86	0	0
T48	21113	0	0	0
T49	0	157	0	0
T69	0	147	0	0
T87	0	133	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	1137	0	0
T5	509076	0	0	0
T15	124038	0	0	0
T17	107703	0	0	0
T18	843394	0	0	0
T19	448626	0	0	0
T21	115774	6	0	0
T22	144782	0	0	0
T23	41506	0	0	0
T24	11291	1	0	0
T33	0	1	0	0
T48	21113	0	0	0
T49	0	1	0	0
T50	0	3	0	0
T69	0	3	0	0
T81	0	2	0	0
T82	0	3	0	0
T84	0	1	0	0
T87	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	75	0	0
T12	36617	1	0	0
T14	25091	1	0	0
T15	124038	0	0	0
T17	107703	0	0	0
T19	448626	0	0	0
T21	115774	0	0	0
T22	144782	0	0	0
T23	41506	1	0	0
T24	11291	0	0	0
T29	0	3	0	0
T30	0	1	0	0
T48	21113	0	0	0
T50	0	2	0	0
T53	0	2	0	0
T84	0	1	0	0
T88	0	1	0	0
T90	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	1072	0	0
T9	17841	154	0	0
T10	0	315	0	0
T11	0	153	0	0
T37	0	319	0	0
T38	0	131	0	0
T39	580954	0	0	0
T40	232496	0	0	0
T41	288949	0	0	0
T42	55194	0	0	0
T43	323431	0	0	0
T44	87132	0	0	0
T45	114862	0	0	0
T46	37186	0	0	0
T47	391051	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	862	0	0
T9	17841	124	0	0
T10	0	255	0	0
T11	0	123	0	0
T37	0	259	0	0
T38	0	101	0	0
T39	580954	0	0	0
T40	232496	0	0	0
T41	288949	0	0	0
T42	55194	0	0	0
T43	323431	0	0	0
T44	87132	0	0	0
T45	114862	0	0	0
T46	37186	0	0	0
T47	391051	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662101016	662030898	0	0
T1	37985	37898	0	0
T2	28883	28794	0	0
T3	15697	15646	0	0
T4	7002	6864	0	0
T7	125718	125713	0	0
T8	841462	841393	0	0
T12	36617	36535	0	0
T13	1945	1894	0	0
T14	25091	25005	0	0
T21	115774	115683	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	662073766	0	0
T1	37985	37898	0	0
T2	28883	28794	0	0
T3	15697	15646	0	0
T4	7002	6864	0	0
T7	125718	125713	0	0
T8	841462	841393	0	0
T12	36617	36535	0	0
T13	1945	1894	0	0
T14	25091	25005	0	0
T21	115774	115683	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T8
1	0	1	Covered	T7,T22,T15
1	1	0	Covered	T1,T2,T8
1	1	1	Covered	T3,T14,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T14,T21
0	1	Covered	T3,T21,T67
1	0	Covered	T50,T29,T53

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T14,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T50,T29,T53

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T14,T21
1	0	Not Covered
1	1	Covered	T3,T21,T67

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T13
1	Covered	T21,T23,T18

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T13
1	Covered	T1,T17,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T13,T21
1	Covered	T1,T3,T8

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T13,T22,T24

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T13,T8,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T13,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T13,T8

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T13
Phase1St	198	Covered	T1,T3,T13
Phase2St	215	Covered	T1,T3,T13
Phase3St	233	Covered	T1,T3,T13
TerminalSt	249	Covered	T1,T3,T13
TimeoutSt	159	Covered	T3,T14,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T13,T8
IdleSt->TimeoutSt	159	Covered	T3,T14,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T36,T39,T97
Phase0St->Phase1St	198	Covered	T1,T3,T13
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T58,T97,T98
Phase1St->Phase2St	215	Covered	T1,T3,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T50,T99,T100
Phase2St->Phase3St	233	Covered	T1,T3,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T101,T64,T102
Phase3St->TerminalSt	249	Covered	T1,T3,T13
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T8,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T14,T21,T5
TimeoutSt->Phase0St	172	Covered	T3,T21,T67

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T14,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T67
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T14,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T14,T21,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T36,T39,T97
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T13
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T58,T97,T98
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T13
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T50,T99,T100
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T101,T64,T102
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T8,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	662233319	209	0	0
CheckAccumTrig0_A	662233319	474	0	0
CheckAccumTrig1_A	662233319	16	0	0
CheckClr_A	662233319	195	0	0
CheckEn_A	662102540	255914480	0	0
CheckPhase0_A	662233319	554	0	0
CheckPhase1_A	662233319	541	0	0
CheckPhase2_A	662233319	531	0	0
CheckPhase3_A	662233319	524	0	0
CheckTimeout0_A	662233319	1682	0	0
CheckTimeoutSt1_A	662233319	133640	0	0
CheckTimeoutSt2_A	662233319	1594	0	0
CheckTimeoutStTrig_A	662233319	72	0	0
ErrorStAllEscAsserted_A	662233319	1148	0	0
ErrorStIsTerminal_A	662233319	938	0	0
EscStateOut_A	662101016	662030898	0	0
u_state_regs_A	662233319	662073766	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	209	0	0
T9	17841	26	0	0
T10	0	47	0	0
T11	0	44	0	0
T37	0	53	0	0
T38	0	39	0	0
T39	580954	0	0	0
T40	232496	0	0	0
T41	288949	0	0	0
T42	55194	0	0	0
T43	323431	0	0	0
T44	87132	0	0	0
T45	114862	0	0	0
T46	37186	0	0	0
T47	391051	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	474	0	0
T1	37985	2	0	0
T2	28883	0	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T5	0	2	0	0
T7	125718	0	0	0
T8	841462	1	0	0
T12	36617	0	0	0
T13	1945	1	0	0
T14	25091	0	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T21	115774	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	16	0	0
T30	0	1	0	0
T39	0	1	0	0
T50	539850	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T74	68038	0	0	0
T75	31145	0	0	0
T76	24623	0	0	0
T77	349079	0	0	0
T78	64344	0	0	0
T79	207908	0	0	0
T80	261201	0	0	0
T81	37597	0	0	0
T82	65285	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	195	0	0
T1	37985	1	0	0
T2	28883	0	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T6	0	2	0	0
T7	125718	0	0	0
T8	841462	1	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T21	115774	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T67	0	4	0	0
T77	0	1	0	0
T83	0	2	0	0
T84	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662102540	255914480	0	0
T1	37985	13773	0	0
T2	28883	28793	0	0
T3	15697	1934	0	0
T4	7002	783	0	0
T7	125718	10018	0	0
T8	841462	839904	0	0
T12	36617	28136	0	0
T13	1945	616	0	0
T14	25091	10069	0	0
T21	115774	85337	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	554	0	0
T1	37985	2	0	0
T2	28883	0	0	0
T3	15697	1	0	0
T4	7002	0	0	0
T7	125718	0	0	0
T8	841462	1	0	0
T12	36617	0	0	0
T13	1945	1	0	0
T14	25091	0	0	0
T17	0	1	0	0
T19	0	1	0	0
T21	115774	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	541	0	0
T1	37985	2	0	0
T2	28883	0	0	0
T3	15697	1	0	0
T4	7002	0	0	0
T7	125718	0	0	0
T8	841462	1	0	0
T12	36617	0	0	0
T13	1945	1	0	0
T14	25091	0	0	0
T17	0	1	0	0
T19	0	1	0	0
T21	115774	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	531	0	0
T1	37985	2	0	0
T2	28883	0	0	0
T3	15697	1	0	0
T4	7002	0	0	0
T7	125718	0	0	0
T8	841462	1	0	0
T12	36617	0	0	0
T13	1945	1	0	0
T14	25091	0	0	0
T17	0	1	0	0
T19	0	1	0	0
T21	115774	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	524	0	0
T1	37985	2	0	0
T2	28883	0	0	0
T3	15697	1	0	0
T4	7002	0	0	0
T7	125718	0	0	0
T8	841462	1	0	0
T12	36617	0	0	0
T13	1945	1	0	0
T14	25091	0	0	0
T17	0	1	0	0
T19	0	1	0	0
T21	115774	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	1682	0	0
T3	15697	1	0	0
T4	7002	0	0	0
T5	0	1	0	0
T7	125718	0	0	0
T8	841462	0	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	3	0	0
T21	115774	2	0	0
T22	144782	0	0	0
T23	41506	0	0	0
T50	0	18	0	0
T67	0	4	0	0
T69	0	244	0	0
T83	0	3	0	0
T84	0	1	0	0
T87	0	11	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	133640	0	0
T3	15697	220	0	0
T4	7002	0	0	0
T5	0	45	0	0
T7	125718	0	0	0
T8	841462	0	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	519	0	0
T21	115774	251	0	0
T22	144782	0	0	0
T23	41506	0	0	0
T50	0	2804	0	0
T67	0	323	0	0
T69	0	8924	0	0
T83	0	1035	0	0
T84	0	103	0	0
T87	0	726	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	1594	0	0
T5	0	1	0	0
T14	25091	3	0	0
T15	124038	0	0	0
T17	107703	0	0	0
T18	843394	0	0	0
T19	448626	0	0	0
T21	115774	1	0	0
T22	144782	0	0	0
T23	41506	0	0	0
T24	11291	0	0	0
T48	21113	0	0	0
T50	0	17	0	0
T67	0	2	0	0
T69	0	244	0	0
T74	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T87	0	11	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	72	0	0
T3	15697	1	0	0
T4	7002	0	0	0
T7	125718	0	0	0
T8	841462	0	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T21	115774	1	0	0
T22	144782	0	0	0
T23	41506	0	0	0
T36	0	1	0	0
T56	0	2	0	0
T58	0	1	0	0
T67	0	2	0	0
T82	0	1	0	0
T83	0	2	0	0
T91	0	1	0	0
T92	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	1148	0	0
T9	17841	162	0	0
T10	0	335	0	0
T11	0	164	0	0
T37	0	320	0	0
T38	0	167	0	0
T39	580954	0	0	0
T40	232496	0	0	0
T41	288949	0	0	0
T42	55194	0	0	0
T43	323431	0	0	0
T44	87132	0	0	0
T45	114862	0	0	0
T46	37186	0	0	0
T47	391051	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	938	0	0
T9	17841	132	0	0
T10	0	275	0	0
T11	0	134	0	0
T37	0	260	0	0
T38	0	137	0	0
T39	580954	0	0	0
T40	232496	0	0	0
T41	288949	0	0	0
T42	55194	0	0	0
T43	323431	0	0	0
T44	87132	0	0	0
T45	114862	0	0	0
T46	37186	0	0	0
T47	391051	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662101016	662030898	0	0
T1	37985	37898	0	0
T2	28883	28794	0	0
T3	15697	15646	0	0
T4	7002	6864	0	0
T7	125718	125713	0	0
T8	841462	841393	0	0
T12	36617	36535	0	0
T13	1945	1894	0	0
T14	25091	25005	0	0
T21	115774	115683	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	662073766	0	0
T1	37985	37898	0	0
T2	28883	28794	0	0
T3	15697	15646	0	0
T4	7002	6864	0	0
T7	125718	125713	0	0
T8	841462	841393	0	0
T12	36617	36535	0	0
T13	1945	1894	0	0
T14	25091	25005	0	0
T21	115774	115683	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T8

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T8,T22,T19

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T8
1	0	1	Covered	T22,T5,T6
1	1	0	Covered	T1,T3,T8
1	1	1	Covered	T1,T2,T14

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T14
0	1	Covered	T23,T50,T82
1	0	Covered	T1,T6,T103

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T6,T103

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T27
1	1	Covered	T23,T50,T82

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T8,T23
1	Covered	T22,T19,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T8,T22
1	Covered	T23,T16,T65

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T8,T22,T23
1	Covered	T1,T5,T6

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T22,T23
1	Covered	T8,T5,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T22,T19,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T23,T20,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T8,T23,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T8,T22

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T8,T22
Phase1St	198	Covered	T1,T8,T22
Phase2St	215	Covered	T1,T8,T22
Phase3St	233	Covered	T1,T8,T22
TerminalSt	249	Covered	T1,T8,T22
TimeoutSt	159	Covered	T1,T2,T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T8,T22,T19
IdleSt->TimeoutSt	159	Covered	T1,T2,T14
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T30,T104,T105
Phase0St->Phase1St	198	Covered	T1,T8,T22
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T30,T93,T58
Phase1St->Phase2St	215	Covered	T1,T8,T22
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T32,T106,T96
Phase2St->Phase3St	233	Covered	T1,T8,T22
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T32,T30,T107
Phase3St->TerminalSt	249	Covered	T1,T8,T22
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T23,T5,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T14,T21
TimeoutSt->Phase0St	172	Covered	T1,T23,T6

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T22,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T14
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T23,T6
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T14,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T104,T108
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T8,T22
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T8,T22
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T30,T93,T109
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T8,T22
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T8,T22
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T106,T63
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T8,T22
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T8,T22,T23
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T32,T30,T107
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T8,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T8,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T23,T6,T49
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T8,T22
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	662233319	176	0	0
CheckAccumTrig0_A	662233319	482	0	0
CheckAccumTrig1_A	662233319	24	0	0
CheckClr_A	662233319	199	0	0
CheckEn_A	662102540	282791788	0	0
CheckPhase0_A	662233319	551	0	0
CheckPhase1_A	662233319	543	0	0
CheckPhase2_A	662233319	532	0	0
CheckPhase3_A	662233319	524	0	0
CheckTimeout0_A	662233319	1237	0	0
CheckTimeoutSt1_A	662233319	131959	0	0
CheckTimeoutSt2_A	662233319	1162	0	0
CheckTimeoutStTrig_A	662233319	50	0	0
ErrorStAllEscAsserted_A	662233319	1153	0	0
ErrorStIsTerminal_A	662233319	943	0	0
EscStateOut_A	662101016	662030898	0	0
u_state_regs_A	662233319	662073766	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	176	0	0
T9	17841	22	0	0
T10	0	61	0	0
T11	0	16	0	0
T37	0	46	0	0
T38	0	31	0	0
T39	580954	0	0	0
T40	232496	0	0	0
T41	288949	0	0	0
T42	55194	0	0	0
T43	323431	0	0	0
T44	87132	0	0	0
T45	114862	0	0	0
T46	37186	0	0	0
T47	391051	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	482	0	0
T5	0	2	0	0
T6	0	4	0	0
T8	841462	1	0	0
T12	36617	0	0	0
T14	25091	0	0	0
T15	124038	0	0	0
T16	0	1	0	0
T19	448626	1	0	0
T20	0	1	0	0
T21	115774	0	0	0
T22	144782	1	0	0
T23	41506	0	0	0
T24	11291	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T48	21113	0	0	0
T49	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	24	0	0
T1	37985	1	0	0
T2	28883	0	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T6	0	1	0	0
T7	125718	0	0	0
T8	841462	0	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T21	115774	0	0	0
T30	0	1	0	0
T64	0	1	0	0
T103	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	2	0	0
T114	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	199	0	0
T5	509076	0	0	0
T6	0	1	0	0
T15	124038	0	0	0
T17	107703	0	0	0
T18	843394	0	0	0
T19	448626	0	0	0
T20	117554	0	0	0
T23	41506	1	0	0
T24	11291	0	0	0
T32	0	10	0	0
T33	27138	0	0	0
T48	21113	0	0	0
T49	0	1	0	0
T51	0	2	0	0
T70	0	1	0	0
T74	0	1	0	0
T78	0	1	0	0
T85	0	1	0	0
T115	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662102540	282791788	0	0
T1	37985	8573	0	0
T2	28883	597	0	0
T3	15697	15645	0	0
T4	7002	787	0	0
T7	125718	125713	0	0
T8	841462	2647	0	0
T12	36617	32745	0	0
T13	1945	620	0	0
T14	25091	10206	0	0
T21	115774	24557	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	551	0	0
T1	37985	1	0	0
T2	28883	0	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T5	0	2	0	0
T6	0	5	0	0
T7	125718	0	0	0
T8	841462	1	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T16	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	115774	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T35	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	543	0	0
T1	37985	1	0	0
T2	28883	0	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T5	0	2	0	0
T6	0	5	0	0
T7	125718	0	0	0
T8	841462	1	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T16	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	115774	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T35	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	532	0	0
T1	37985	1	0	0
T2	28883	0	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T5	0	2	0	0
T6	0	5	0	0
T7	125718	0	0	0
T8	841462	1	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T16	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	115774	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T35	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	524	0	0
T1	37985	1	0	0
T2	28883	0	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T5	0	2	0	0
T6	0	5	0	0
T7	125718	0	0	0
T8	841462	1	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T16	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	115774	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T35	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	1237	0	0
T1	37985	1	0	0
T2	28883	8	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T6	0	1	0	0
T7	125718	0	0	0
T8	841462	0	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	2	0	0
T21	115774	4	0	0
T23	0	2	0	0
T50	0	7	0	0
T69	0	4	0	0
T70	0	1	0	0
T87	0	9	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	131959	0	0
T1	37985	260	0	0
T2	28883	1249	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T7	125718	0	0	0
T8	841462	0	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	244	0	0
T21	115774	736	0	0
T23	0	112	0	0
T50	0	979	0	0
T69	0	212	0	0
T70	0	22	0	0
T74	0	25	0	0
T87	0	658	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	1162	0	0
T2	28883	8	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T7	125718	0	0	0
T8	841462	0	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	2	0	0
T21	115774	4	0	0
T22	144782	0	0	0
T23	0	1	0	0
T50	0	6	0	0
T51	0	2	0	0
T69	0	4	0	0
T70	0	1	0	0
T74	0	1	0	0
T87	0	9	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	50	0	0
T5	509076	0	0	0
T15	124038	0	0	0
T17	107703	0	0	0
T18	843394	0	0	0
T19	448626	0	0	0
T20	117554	0	0	0
T23	41506	1	0	0
T24	11291	0	0	0
T30	0	1	0	0
T33	27138	0	0	0
T48	21113	0	0	0
T50	0	1	0	0
T55	0	1	0	0
T82	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T92	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	1153	0	0
T9	17841	143	0	0
T10	0	331	0	0
T11	0	162	0	0
T37	0	354	0	0
T38	0	163	0	0
T39	580954	0	0	0
T40	232496	0	0	0
T41	288949	0	0	0
T42	55194	0	0	0
T43	323431	0	0	0
T44	87132	0	0	0
T45	114862	0	0	0
T46	37186	0	0	0
T47	391051	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	943	0	0
T9	17841	113	0	0
T10	0	271	0	0
T11	0	132	0	0
T37	0	294	0	0
T38	0	133	0	0
T39	580954	0	0	0
T40	232496	0	0	0
T41	288949	0	0	0
T42	55194	0	0	0
T43	323431	0	0	0
T44	87132	0	0	0
T45	114862	0	0	0
T46	37186	0	0	0
T47	391051	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662101016	662030898	0	0
T1	37985	37898	0	0
T2	28883	28794	0	0
T3	15697	15646	0	0
T4	7002	6864	0	0
T7	125718	125713	0	0
T8	841462	841393	0	0
T12	36617	36535	0	0
T13	1945	1894	0	0
T14	25091	25005	0	0
T21	115774	115683	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	662073766	0	0
T1	37985	37898	0	0
T2	28883	28794	0	0
T3	15697	15646	0	0
T4	7002	6864	0	0
T7	125718	125713	0	0
T8	841462	841393	0	0
T12	36617	36535	0	0
T13	1945	1894	0	0
T14	25091	25005	0	0
T21	115774	115683	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T8
1	0	1	Covered	T22,T15,T86
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T2,T14,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T14,T21
0	1	Covered	T23,T35,T87
1	0	Covered	T23,T106,T54

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T14,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T106,T54

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T21
1	0	Covered	T26,T28
1	1	Covered	T23,T35,T87

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T8,T23
1	Covered	T7,T5,T86

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T8,T23,T24

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T8,T23,T6

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T7,T8,T23
1	Covered	T3,T5,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T7,T8,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T7,T8,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T7,T8,T23

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T7,T8
Phase1St	198	Covered	T3,T7,T8
Phase2St	215	Covered	T3,T7,T8
Phase3St	233	Covered	T3,T7,T8
TerminalSt	249	Covered	T3,T7,T8
TimeoutSt	159	Covered	T2,T14,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T3,T7,T8
IdleSt->TimeoutSt	159	Covered	T2,T14,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T35,T118,T54
Phase0St->Phase1St	198	Covered	T3,T7,T8
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T118,T29,T39
Phase1St->Phase2St	215	Covered	T3,T7,T8
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T118,T50,T106
Phase2St->Phase3St	233	Covered	T3,T7,T8
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T51,T29,T106
Phase3St->TerminalSt	249	Covered	T3,T7,T8
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T8,T23,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T14,T21
TimeoutSt->Phase0St	172	Covered	T23,T35,T87

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T14,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T35,T87
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T14,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T14,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T35,T54,T112
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T7,T8
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T7,T8
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T118,T29,T39
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T7,T8
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T7,T8
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T118,T50,T106
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T7,T8
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T7,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T51,T29,T106
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T7,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T7,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T8,T23,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T7,T8
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	662233319	224	0	0
CheckAccumTrig0_A	662233319	522	0	0
CheckAccumTrig1_A	662233319	20	0	0
CheckClr_A	662233319	224	0	0
CheckEn_A	662102540	265056305	0	0
CheckPhase0_A	662233319	579	0	0
CheckPhase1_A	662233319	568	0	0
CheckPhase2_A	662233319	556	0	0
CheckPhase3_A	662233319	541	0	0
CheckTimeout0_A	662233319	1067	0	0
CheckTimeoutSt1_A	662233319	114557	0	0
CheckTimeoutSt2_A	662233319	1002	0	0
CheckTimeoutStTrig_A	662233319	45	0	0
ErrorStAllEscAsserted_A	662233319	1187	0	0
ErrorStIsTerminal_A	662233319	977	0	0
EscStateOut_A	662101016	662030898	0	0
u_state_regs_A	662233319	662073766	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	224	0	0
T9	17841	18	0	0
T10	0	62	0	0
T11	0	26	0	0
T37	0	82	0	0
T38	0	36	0	0
T39	580954	0	0	0
T40	232496	0	0	0
T41	288949	0	0	0
T42	55194	0	0	0
T43	323431	0	0	0
T44	87132	0	0	0
T45	114862	0	0	0
T46	37186	0	0	0
T47	391051	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	522	0	0
T3	15697	1	0	0
T4	7002	0	0	0
T5	0	2	0	0
T6	0	4	0	0
T7	125718	1	0	0
T8	841462	2	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T20	0	1	0	0
T21	115774	0	0	0
T22	144782	0	0	0
T23	41506	1	0	0
T24	0	1	0	0
T35	0	1	0	0
T86	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	20	0	0
T5	509076	0	0	0
T15	124038	0	0	0
T17	107703	0	0	0
T18	843394	0	0	0
T19	448626	0	0	0
T20	117554	0	0	0
T23	41506	1	0	0
T24	11291	0	0	0
T30	0	1	0	0
T33	27138	0	0	0
T39	0	1	0	0
T48	21113	0	0	0
T54	0	1	0	0
T100	0	2	0	0
T106	0	2	0	0
T111	0	1	0	0
T113	0	1	0	0
T119	0	1	0	0
T120	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	224	0	0
T6	0	1	0	0
T8	841462	2	0	0
T12	36617	0	0	0
T14	25091	0	0	0
T15	124038	0	0	0
T19	448626	0	0	0
T21	115774	0	0	0
T22	144782	0	0	0
T23	41506	2	0	0
T24	11291	0	0	0
T35	0	1	0	0
T48	21113	0	0	0
T50	0	1	0	0
T51	0	2	0	0
T77	0	1	0	0
T83	0	1	0	0
T118	0	3	0	0
T121	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662102540	265056305	0	0
T1	37985	37897	0	0
T2	28883	27636	0	0
T3	15697	9185	0	0
T4	7002	791	0	0
T7	125718	78095	0	0
T8	841462	835616	0	0
T12	36617	31920	0	0
T13	1945	1893	0	0
T14	25091	13775	0	0
T21	115774	14711	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	579	0	0
T3	15697	1	0	0
T4	7002	0	0	0
T5	0	2	0	0
T6	0	4	0	0
T7	125718	1	0	0
T8	841462	2	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T20	0	1	0	0
T21	115774	0	0	0
T22	144782	0	0	0
T23	41506	3	0	0
T24	0	1	0	0
T35	0	1	0	0
T86	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	568	0	0
T3	15697	1	0	0
T4	7002	0	0	0
T5	0	2	0	0
T6	0	4	0	0
T7	125718	1	0	0
T8	841462	2	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T20	0	1	0	0
T21	115774	0	0	0
T22	144782	0	0	0
T23	41506	3	0	0
T24	0	1	0	0
T35	0	1	0	0
T86	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	556	0	0
T3	15697	1	0	0
T4	7002	0	0	0
T5	0	2	0	0
T6	0	4	0	0
T7	125718	1	0	0
T8	841462	2	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T20	0	1	0	0
T21	115774	0	0	0
T22	144782	0	0	0
T23	41506	3	0	0
T24	0	1	0	0
T35	0	1	0	0
T86	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	541	0	0
T3	15697	1	0	0
T4	7002	0	0	0
T5	0	2	0	0
T6	0	4	0	0
T7	125718	1	0	0
T8	841462	2	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	0	0	0
T20	0	1	0	0
T21	115774	0	0	0
T22	144782	0	0	0
T23	41506	3	0	0
T24	0	1	0	0
T35	0	1	0	0
T86	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	1067	0	0
T2	28883	1	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T6	0	3	0	0
T7	125718	0	0	0
T8	841462	0	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	1	0	0
T21	115774	7	0	0
T22	144782	0	0	0
T23	0	4	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	2	0	0
T50	0	3	0	0
T87	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	114557	0	0
T2	28883	146	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T6	0	755	0	0
T7	125718	0	0	0
T8	841462	0	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	120	0	0
T21	115774	1187	0	0
T22	144782	0	0	0
T23	0	562	0	0
T32	0	75	0	0
T34	0	107	0	0
T35	0	846	0	0
T50	0	383	0	0
T87	0	65	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	1002	0	0
T2	28883	1	0	0
T3	15697	0	0	0
T4	7002	0	0	0
T6	0	3	0	0
T7	125718	0	0	0
T8	841462	0	0	0
T12	36617	0	0	0
T13	1945	0	0	0
T14	25091	1	0	0
T21	115774	7	0	0
T22	144782	0	0	0
T23	0	2	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T50	0	3	0	0
T82	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	45	0	0
T5	509076	0	0	0
T15	124038	0	0	0
T17	107703	0	0	0
T18	843394	0	0	0
T19	448626	0	0	0
T20	117554	0	0	0
T23	41506	1	0	0
T24	11291	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T33	27138	0	0	0
T35	0	1	0	0
T48	21113	0	0	0
T87	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T116	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	1187	0	0
T9	17841	161	0	0
T10	0	358	0	0
T11	0	162	0	0
T37	0	334	0	0
T38	0	172	0	0
T39	580954	0	0	0
T40	232496	0	0	0
T41	288949	0	0	0
T42	55194	0	0	0
T43	323431	0	0	0
T44	87132	0	0	0
T45	114862	0	0	0
T46	37186	0	0	0
T47	391051	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	977	0	0
T9	17841	131	0	0
T10	0	298	0	0
T11	0	132	0	0
T37	0	274	0	0
T38	0	142	0	0
T39	580954	0	0	0
T40	232496	0	0	0
T41	288949	0	0	0
T42	55194	0	0	0
T43	323431	0	0	0
T44	87132	0	0	0
T45	114862	0	0	0
T46	37186	0	0	0
T47	391051	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662101016	662030898	0	0
T1	37985	37898	0	0
T2	28883	28794	0	0
T3	15697	15646	0	0
T4	7002	6864	0	0
T7	125718	125713	0	0
T8	841462	841393	0	0
T12	36617	36535	0	0
T13	1945	1894	0	0
T14	25091	25005	0	0
T21	115774	115683	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662233319	662073766	0	0
T1	37985	37898	0	0
T2	28883	28794	0	0
T3	15697	15646	0	0
T4	7002	6864	0	0
T7	125718	125713	0	0
T8	841462	841393	0	0
T12	36617	36535	0	0
T13	1945	1894	0	0
T14	25091	25005	0	0
T21	115774	115683	0	0