Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T184,T185
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14402	0	0
DisabledNoTrigBkwd_A	2147483647	830081	0	0
DisabledNoTrigFwd_A	2147483647	1614227603	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14402	0	0
T33	21194	0	0	0
T51	114104	0	0	0
T69	1512	645	0	0
T70	915016	0	0	0
T71	59417	0	0	0
T76	167467	0	0	0
T87	241995	0	0	0
T97	233713	0	0	0
T184	2889	557	0	0
T185	0	206	0	0
T186	0	277	0	0
T187	0	671	0	0
T188	1085	363	0	0
T189	0	880	0	0
T190	0	341	0	0
T191	0	990	0	0
T192	0	595	0	0
T193	0	742	0	0
T194	0	297	0	0
T195	0	178	0	0
T196	0	1138	0	0
T197	0	436	0	0
T198	0	1405	0	0
T199	0	848	0	0
T200	0	1913	0	0
T201	0	1459	0	0
T202	0	461	0	0
T203	17561	0	0	0
T204	12316	0	0	0
T205	59584	0	0	0
T206	83102	0	0	0
T207	134755	0	0	0
T208	355238	0	0	0
T209	832488	0	0	0
T210	267692	0	0	0
T211	4082	0	0	0
T212	21961	0	0	0
T213	361375	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	830081	0	0
T1	200156	112	0	0
T2	958476	876	0	0
T3	444436	5726	0	0
T4	0	9	0	0
T6	2120784	6694	0	0
T7	0	5	0	0
T11	128040	15	0	0
T12	147564	9	0	0
T13	0	1650	0	0
T14	0	631	0	0
T15	0	25	0	0
T18	134840	0	0	0
T19	71392	25	0	0
T20	43208	1	0	0
T21	175732	22	0	0
T22	0	232	0	0
T48	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1614227603	0	0
T1	200156	53392	0	0
T2	958476	1990653	0	0
T3	444436	122987	0	0
T6	2120784	555161	0	0
T11	128040	74021	0	0
T12	147564	77954	0	0
T18	134840	102394	0	0
T19	71392	32149	0	0
T20	43208	36694	0	0
T21	175732	122712	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T189,T193
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	727712217	3405	0	0
DisabledNoTrigBkwd_A	727712217	216524	0	0
DisabledNoTrigFwd_A	727712217	390514016	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	3405	0	0
T33	21194	0	0	0
T69	1512	645	0	0
T70	915016	0	0	0
T71	59417	0	0	0
T76	167467	0	0	0
T87	241995	0	0	0
T97	233713	0	0	0
T189	0	880	0	0
T193	0	742	0	0
T196	0	1138	0	0
T203	17561	0	0	0
T204	12316	0	0	0
T205	59584	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	216524	0	0
T1	50039	58	0	0
T2	239619	6	0	0
T3	111109	2022	0	0
T6	530196	2183	0	0
T11	32010	0	0	0
T12	36891	9	0	0
T18	33710	0	0	0
T19	17848	3	0	0
T20	10802	1	0	0
T21	43933	1	0	0
T22	0	101	0	0
T48	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	390514016	0	0
T1	50039	17501	0	0
T2	239619	229748	0	0
T3	111109	4314	0	0
T6	530196	3112	0	0
T11	32010	26975	0	0
T12	36891	2122	0	0
T18	33710	31528	0	0
T19	17848	10116	0	0
T20	10802	4501	0	0
T21	43933	32022	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T184,T185,T187
1	1	Covered	T1,T2,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T11

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	727712217	3942	0	0
DisabledNoTrigBkwd_A	727712217	258130	0	0
DisabledNoTrigFwd_A	727712217	385978691	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	3942	0	0
T51	114104	0	0	0
T184	2889	557	0	0
T185	0	206	0	0
T187	0	671	0	0
T192	0	595	0	0
T200	0	1913	0	0
T206	83102	0	0	0
T207	134755	0	0	0
T208	355238	0	0	0
T209	832488	0	0	0
T210	267692	0	0	0
T211	4082	0	0	0
T212	21961	0	0	0
T213	361375	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	258130	0	0
T1	50039	5	0	0
T2	239619	166	0	0
T3	111109	0	0	0
T4	0	9	0	0
T6	530196	2372	0	0
T7	0	2	0	0
T11	32010	12	0	0
T12	36891	0	0	0
T13	0	325	0	0
T14	0	630	0	0
T18	33710	0	0	0
T19	17848	13	0	0
T20	10802	0	0	0
T21	43933	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	385978691	0	0
T1	50039	2400	0	0
T2	239619	648673	0	0
T3	111109	111104	0	0
T6	530196	13762	0	0
T11	32010	3824	0	0
T12	36891	36839	0	0
T18	33710	5718	0	0
T19	17848	4336	0	0
T20	10802	10731	0	0
T21	43933	19937	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T188,T190,T195
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	727712217	1318	0	0
DisabledNoTrigBkwd_A	727712217	171053	0	0
DisabledNoTrigFwd_A	727712217	407139591	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	1318	0	0
T104	12612	0	0	0
T188	1085	363	0	0
T190	0	341	0	0
T195	0	178	0	0
T197	0	436	0	0
T214	269583	0	0	0
T215	96681	0	0	0
T216	413299	0	0	0
T217	14352	0	0	0
T218	375784	0	0	0
T219	19464	0	0	0
T220	25729	0	0	0
T221	677495	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	171053	0	0
T1	50039	21	0	0
T2	239619	473	0	0
T3	111109	1576	0	0
T6	530196	2138	0	0
T11	32010	3	0	0
T12	36891	0	0	0
T13	0	313	0	0
T15	0	25	0	0
T18	33710	0	0	0
T19	17848	4	0	0
T20	10802	0	0	0
T21	43933	4	0	0
T22	0	129	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	407139591	0	0
T1	50039	31074	0	0
T2	239619	955260	0	0
T3	111109	3243	0	0
T6	530196	8645	0	0
T11	32010	11297	0	0
T12	36891	36839	0	0
T18	33710	31528	0	0
T19	17848	11367	0	0
T20	10802	10731	0	0
T21	43933	38754	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T11
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T186,T191,T194
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	727712217	5737	0	0
DisabledNoTrigBkwd_A	727712217	184374	0	0
DisabledNoTrigFwd_A	727712217	430595305	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	5737	0	0
T52	43112	0	0	0
T53	182273	0	0	0
T79	49249	0	0	0
T80	23432	0	0	0
T81	481348	0	0	0
T96	18790	0	0	0
T103	518599	0	0	0
T186	2573	277	0	0
T191	0	990	0	0
T194	0	297	0	0
T198	0	1405	0	0
T199	0	848	0	0
T201	0	1459	0	0
T202	0	461	0	0
T222	13915	0	0	0
T223	38468	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	184374	0	0
T1	50039	28	0	0
T2	239619	231	0	0
T3	111109	2128	0	0
T6	530196	1	0	0
T7	0	3	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T13	0	1012	0	0
T14	0	1	0	0
T18	33710	0	0	0
T19	17848	5	0	0
T20	10802	0	0	0
T21	43933	8	0	0
T22	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	430595305	0	0
T1	50039	2417	0	0
T2	239619	156972	0	0
T3	111109	4326	0	0
T6	530196	529642	0	0
T11	32010	31925	0	0
T12	36891	2154	0	0
T18	33710	33620	0	0
T19	17848	6330	0	0
T20	10802	10731	0	0
T21	43933	31999	0	0