Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.39	100.00	97.78	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T23,T24
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T11
1	1	0	Covered	T2,T3,T11
1	1	1	Covered	T1,T2,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T18
0	1	Covered	T1,T2,T25
1	0	Covered	T2,T4,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T18
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T27,T28
1	1	Covered	T1,T2,T25

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T11,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T2,T18

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T2,T18
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T26,T29,T30
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T6,T31,T32
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T33,T34,T35
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T13,T31,T32
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T3
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T2,T18
TimeoutSt->Phase0St	172	Covered	T1,T2,T25

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T26,T31
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T31,T32
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T33,T34,T36
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T13,T31,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	731	0	0
CheckAccumTrig0_A	2147483647	2404	0	0
CheckAccumTrig1_A	2147483647	115	0	0
CheckClr_A	2147483647	1123	0	0
CheckEn_A	2147483647	1229065995	0	0
CheckPhase0_A	2147483647	2723	0	0
CheckPhase1_A	2147483647	2667	0	0
CheckPhase2_A	2147483647	2612	0	0
CheckPhase3_A	2147483647	2546	0	0
CheckTimeout0_A	2147483647	3197	0	0
CheckTimeoutSt1_A	2147483647	376514	0	0
CheckTimeoutSt2_A	2147483647	2833	0	0
CheckTimeoutStTrig_A	2147483647	243	0	0
ErrorStAllEscAsserted_A	2147483647	3922	0	0
ErrorStIsTerminal_A	2147483647	3202	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	731	0	0
T8	68328	124	0	0
T9	0	112	0	0
T10	0	129	0	0
T37	0	143	0	0
T38	0	223	0	0
T39	840032	0	0	0
T40	2599724	0	0	0
T41	981460	0	0	0
T42	1099136	0	0	0
T43	518252	0	0	0
T44	1535932	0	0	0
T45	3600308	0	0	0
T46	3476864	0	0	0
T47	8116	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2404	0	0
T1	150117	4	0	0
T2	718857	4	0	0
T3	333327	6	0	0
T4	0	1	0	0
T6	2120784	5	0	0
T7	958355	2	0	0
T11	128040	2	0	0
T12	147564	3	0	0
T13	0	5	0	0
T14	0	2	0	0
T15	0	1	0	0
T18	134840	0	0	0
T19	71392	4	0	0
T20	43208	1	0	0
T21	175732	4	0	0
T22	451213	3	0	0
T31	0	5	0	0
T48	3637	1	0	0
T49	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	115	0	0
T2	239619	1	0	0
T3	111109	0	0	0
T4	0	1	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	0	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T22	451213	0	0	0
T26	26562	1	0	0
T29	0	3	0	0
T31	1469268	1	0	0
T32	206544	1	0	0
T40	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	3	0	0
T63	0	2	0	0
T64	35146	0	0	0
T65	631092	0	0	0
T66	832760	0	0	0
T67	42348	0	0	0
T68	31950	0	0	0
T69	3024	0	0	0
T70	1830032	0	0	0
T71	59417	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1123	0	0
T1	200156	3	0	0
T2	958476	4	0	0
T3	444436	3	0	0
T4	0	1	0	0
T6	2120784	1	0	0
T11	128040	0	0	0
T12	147564	2	0	0
T13	0	1	0	0
T18	134840	0	0	0
T19	71392	0	0	0
T20	43208	0	0	0
T21	175732	1	0	0
T25	0	1	0	0
T26	0	2	0	0
T29	0	4	0	0
T31	0	5	0	0
T32	0	11	0	0
T33	0	1	0	0
T34	0	2	0	0
T48	0	1	0	0
T50	0	3	0	0
T64	0	1	0	0
T72	0	4	0	0
T73	0	3	0	0
T74	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1229065995	0	0
T1	200156	9610	0	0
T2	958476	2498799	0	0
T3	444436	121626	0	0
T6	2120784	555161	0	0
T11	128040	66719	0	0
T12	147564	77952	0	0
T18	134840	102391	0	0
T19	71392	11552	0	0
T20	43208	34855	0	0
T21	175732	69796	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2723	0	0
T1	200156	8	0	0
T2	958476	9	0	0
T3	444436	6	0	0
T4	0	1	0	0
T6	2120784	4	0	0
T7	0	2	0	0
T11	128040	2	0	0
T12	147564	3	0	0
T13	0	5	0	0
T14	0	2	0	0
T15	0	1	0	0
T18	134840	0	0	0
T19	71392	4	0	0
T20	43208	1	0	0
T21	175732	4	0	0
T22	0	3	0	0
T25	0	1	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2667	0	0
T1	200156	8	0	0
T2	958476	9	0	0
T3	444436	6	0	0
T4	0	1	0	0
T6	2120784	3	0	0
T7	0	2	0	0
T11	128040	2	0	0
T12	147564	3	0	0
T13	0	5	0	0
T14	0	2	0	0
T15	0	1	0	0
T18	134840	0	0	0
T19	71392	4	0	0
T20	43208	1	0	0
T21	175732	4	0	0
T22	0	3	0	0
T25	0	1	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2612	0	0
T1	200156	8	0	0
T2	958476	9	0	0
T3	444436	6	0	0
T4	0	1	0	0
T6	2120784	3	0	0
T7	0	2	0	0
T11	128040	2	0	0
T12	147564	3	0	0
T13	0	5	0	0
T14	0	2	0	0
T15	0	1	0	0
T18	134840	0	0	0
T19	71392	4	0	0
T20	43208	1	0	0
T21	175732	4	0	0
T22	0	3	0	0
T25	0	1	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2546	0	0
T1	200156	8	0	0
T2	958476	9	0	0
T3	444436	6	0	0
T4	0	1	0	0
T6	2120784	3	0	0
T7	0	2	0	0
T11	128040	2	0	0
T12	147564	3	0	0
T13	0	4	0	0
T14	0	2	0	0
T15	0	1	0	0
T18	134840	0	0	0
T19	71392	4	0	0
T20	43208	1	0	0
T21	175732	4	0	0
T22	0	3	0	0
T25	0	1	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3197	0	0
T1	150117	7	0	0
T2	958476	10	0	0
T3	444436	0	0	0
T4	0	5	0	0
T6	2120784	0	0	0
T11	128040	0	0	0
T12	147564	0	0	0
T18	134840	10	0	0
T19	71392	0	0	0
T20	43208	0	0	0
T21	175732	1	0	0
T22	451213	0	0	0
T25	0	10	0	0
T26	0	1	0	0
T29	0	2	0	0
T30	0	3	0	0
T31	0	20	0	0
T32	0	12	0	0
T34	0	1	0	0
T35	0	2	0	0
T50	0	7	0	0
T66	0	11	0	0
T67	0	2	0	0
T75	0	6	0	0
T76	0	1	0	0
T77	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	376514	0	0
T1	150117	1294	0	0
T2	958476	2616	0	0
T3	444436	0	0	0
T4	0	345	0	0
T6	2120784	0	0	0
T11	128040	0	0	0
T12	147564	0	0	0
T18	134840	978	0	0
T19	71392	0	0	0
T20	43208	0	0	0
T21	175732	165	0	0
T22	451213	0	0	0
T25	0	614	0	0
T26	0	57	0	0
T29	0	720	0	0
T30	0	316	0	0
T31	0	1543	0	0
T32	0	898	0	0
T34	0	1	0	0
T35	0	270	0	0
T50	0	1195	0	0
T66	0	2126	0	0
T67	0	166	0	0
T75	0	1053	0	0
T76	0	57	0	0
T77	0	215	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2833	0	0
T1	150117	3	0	0
T2	958476	5	0	0
T3	444436	0	0	0
T4	0	4	0	0
T6	2120784	0	0	0
T11	128040	0	0	0
T12	147564	0	0	0
T18	134840	10	0	0
T19	71392	0	0	0
T20	43208	0	0	0
T21	175732	1	0	0
T22	451213	0	0	0
T25	0	8	0	0
T29	0	2	0	0
T30	0	2	0	0
T31	0	15	0	0
T32	0	11	0	0
T35	0	5	0	0
T50	0	5	0	0
T66	0	9	0	0
T67	0	2	0	0
T73	0	1	0	0
T75	0	5	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	243	0	0
T1	150117	4	0	0
T2	718857	3	0	0
T3	333327	0	0	0
T4	303092	0	0	0
T5	73203	0	0	0
T6	1590588	0	0	0
T11	96030	0	0	0
T12	110673	0	0	0
T17	224344	0	0	0
T18	101130	0	0	0
T19	53544	0	0	0
T20	32406	0	0	0
T21	131799	0	0	0
T25	26975	1	0	0
T26	26562	0	0	0
T29	0	1	0	0
T30	0	2	0	0
T31	734634	0	0	0
T32	103272	0	0	0
T36	0	2	0	0
T49	143657	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T66	0	5	0	0
T73	0	3	0	0
T75	24656	1	0	0
T76	0	1	0	0
T78	0	2	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	611190	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3922	0	0
T8	68328	665	0	0
T9	0	641	0	0
T10	0	700	0	0
T37	0	640	0	0
T38	0	1276	0	0
T39	840032	0	0	0
T40	2599724	0	0	0
T41	981460	0	0	0
T42	1099136	0	0	0
T43	518252	0	0	0
T44	1535932	0	0	0
T45	3600308	0	0	0
T46	3476864	0	0	0
T47	8116	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3202	0	0
T8	68328	545	0	0
T9	0	521	0	0
T10	0	580	0	0
T37	0	520	0	0
T38	0	1036	0	0
T39	840032	0	0	0
T40	2599724	0	0	0
T41	981460	0	0	0
T42	1099136	0	0	0
T43	518252	0	0	0
T44	1535932	0	0	0
T45	3600308	0	0	0
T46	3476864	0	0	0
T47	8116	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	200156	199928	0	0
T2	958476	958432	0	0
T3	444436	444416	0	0
T6	2120784	2120760	0	0
T11	128040	127700	0	0
T12	147564	147356	0	0
T18	134840	134480	0	0
T19	71392	70992	0	0
T20	43208	42924	0	0
T21	175732	175472	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	200156	199928	0	0
T2	958476	958432	0	0
T3	444436	444416	0	0
T6	2120784	2120760	0	0
T11	128040	127700	0	0
T12	147564	147356	0	0
T18	134840	134480	0	0
T19	71392	70992	0	0
T20	43208	42924	0	0
T21	175732	175472	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T19
1	1	0	Covered	T2,T11,T18
1	1	1	Covered	T1,T2,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T18
0	1	Covered	T1,T2,T75
1	0	Covered	T26,T32,T51

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T32,T51

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Not Covered
1	1	Covered	T1,T2,T75

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T48

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T3,T6,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T21

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T2,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T2,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T26,T29,T86
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T6,T32,T87
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T33,T34,T35
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T72,T30,T88
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T3
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T2,T18
TimeoutSt->Phase0St	172	Covered	T1,T2,T75

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T75
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T29,T59
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T32,T87
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T33,T34,T53
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T72,T30,T88
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	727712217	208	0	0
CheckAccumTrig0_A	727712217	875	0	0
CheckAccumTrig1_A	727712217	42	0	0
CheckClr_A	727712217	423	0	0
CheckEn_A	727596159	284307814	0	0
CheckPhase0_A	727712217	966	0	0
CheckPhase1_A	727712217	943	0	0
CheckPhase2_A	727712217	923	0	0
CheckPhase3_A	727712217	902	0	0
CheckTimeout0_A	727712217	581	0	0
CheckTimeoutSt1_A	727712217	76944	0	0
CheckTimeoutSt2_A	727712217	474	0	0
CheckTimeoutStTrig_A	727712217	63	0	0
ErrorStAllEscAsserted_A	727712217	989	0	0
ErrorStIsTerminal_A	727712217	809	0	0
EscStateOut_A	727595321	727526509	0	0
u_state_regs_A	727712217	727567330	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	208	0	0
T8	17082	46	0	0
T9	0	33	0	0
T10	0	29	0	0
T37	0	39	0	0
T38	0	61	0	0
T39	210008	0	0	0
T40	649931	0	0	0
T41	245365	0	0	0
T42	274784	0	0	0
T43	129563	0	0	0
T44	383983	0	0	0
T45	900077	0	0	0
T46	869216	0	0	0
T47	2029	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	875	0	0
T1	50039	1	0	0
T2	239619	2	0	0
T3	111109	4	0	0
T6	530196	2	0	0
T11	32010	0	0	0
T12	36891	3	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	1	0	0
T21	43933	1	0	0
T22	0	1	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	42	0	0
T26	26562	1	0	0
T31	734634	0	0	0
T32	103272	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T63	0	1	0	0
T64	17573	0	0	0
T65	315546	0	0	0
T66	416380	0	0	0
T67	21174	0	0	0
T68	15975	0	0	0
T69	1512	0	0	0
T70	915016	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	423	0	0
T1	50039	1	0	0
T2	239619	3	0	0
T3	111109	3	0	0
T6	530196	1	0	0
T11	32010	0	0	0
T12	36891	2	0	0
T18	33710	0	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	1	0	0
T26	0	2	0	0
T32	0	7	0	0
T48	0	1	0	0
T64	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727596159	284307814	0	0
T1	50039	2387	0	0
T2	239619	229748	0	0
T3	111109	4314	0	0
T6	530196	3112	0	0
T11	32010	26974	0	0
T12	36891	2122	0	0
T18	33710	31527	0	0
T19	17848	2706	0	0
T20	10802	2665	0	0
T21	43933	32021	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	966	0	0
T1	50039	2	0	0
T2	239619	3	0	0
T3	111109	4	0	0
T6	530196	2	0	0
T11	32010	0	0	0
T12	36891	3	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	1	0	0
T21	43933	1	0	0
T22	0	1	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	943	0	0
T1	50039	2	0	0
T2	239619	3	0	0
T3	111109	4	0	0
T6	530196	1	0	0
T11	32010	0	0	0
T12	36891	3	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	1	0	0
T21	43933	1	0	0
T22	0	1	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	923	0	0
T1	50039	2	0	0
T2	239619	3	0	0
T3	111109	4	0	0
T6	530196	1	0	0
T11	32010	0	0	0
T12	36891	3	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	1	0	0
T21	43933	1	0	0
T22	0	1	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	902	0	0
T1	50039	2	0	0
T2	239619	3	0	0
T3	111109	4	0	0
T6	530196	1	0	0
T11	32010	0	0	0
T12	36891	3	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	1	0	0
T21	43933	1	0	0
T22	0	1	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	581	0	0
T1	50039	2	0	0
T2	239619	2	0	0
T3	111109	0	0	0
T4	0	4	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	1	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T31	0	6	0	0
T32	0	4	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	76944	0	0
T1	50039	163	0	0
T2	239619	430	0	0
T3	111109	0	0	0
T4	0	343	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	124	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	165	0	0
T25	0	83	0	0
T26	0	57	0	0
T31	0	580	0	0
T32	0	185	0	0
T75	0	170	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	474	0	0
T1	50039	1	0	0
T2	239619	1	0	0
T3	111109	0	0	0
T4	0	4	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	1	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	1	0	0
T25	0	1	0	0
T31	0	5	0	0
T32	0	3	0	0
T66	0	2	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	63	0	0
T1	50039	1	0	0
T2	239619	1	0	0
T3	111109	0	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	0	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T30	0	1	0	0
T51	0	1	0	0
T66	0	2	0	0
T73	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	989	0	0
T8	17082	162	0	0
T9	0	144	0	0
T10	0	165	0	0
T37	0	169	0	0
T38	0	349	0	0
T39	210008	0	0	0
T40	649931	0	0	0
T41	245365	0	0	0
T42	274784	0	0	0
T43	129563	0	0	0
T44	383983	0	0	0
T45	900077	0	0	0
T46	869216	0	0	0
T47	2029	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	809	0	0
T8	17082	132	0	0
T9	0	114	0	0
T10	0	135	0	0
T37	0	139	0	0
T38	0	289	0	0
T39	210008	0	0	0
T40	649931	0	0	0
T41	245365	0	0	0
T42	274784	0	0	0
T43	129563	0	0	0
T44	383983	0	0	0
T45	900077	0	0	0
T46	869216	0	0	0
T47	2029	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727595321	727526509	0	0
T1	50039	49982	0	0
T2	239619	239608	0	0
T3	111109	111104	0	0
T6	530196	530190	0	0
T11	32010	31925	0	0
T12	36891	36839	0	0
T18	33710	33620	0	0
T19	17848	17748	0	0
T20	10802	10731	0	0
T21	43933	43868	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	727567330	0	0
T1	50039	49982	0	0
T2	239619	239608	0	0
T3	111109	111104	0	0
T6	530196	530190	0	0
T11	32010	31925	0	0
T12	36891	36839	0	0
T18	33710	33620	0	0
T19	17848	17748	0	0
T20	10802	10731	0	0
T21	43933	43868	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T22,T7,T16
1	1	0	Covered	T2,T18,T25
1	1	1	Covered	T2,T25,T31

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T25,T31
0	1	Covered	T25,T66,T29
1	0	Covered	T2,T31,T34

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T25,T31
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T31,T34

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T25,T31
1	0	Not Covered
1	1	Covered	T25,T66,T29

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T49,T31

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T21,T22
1	Covered	T1,T3,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T19
1	Covered	T2,T25,T31

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T19,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T13,T25,T31

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T2,T25,T31

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T2,T25,T31
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T31,T76
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T31,T30,T89
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T67,T90
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T33,T34,T72
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T13
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T25,T31
TimeoutSt->Phase0St	172	Covered	T2,T25,T31

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T31
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T31
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T31
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T31
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T31,T35
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T30,T89
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T67,T90
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T34,T72
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	727712217	192	0	0
CheckAccumTrig0_A	727712217	525	0	0
CheckAccumTrig1_A	727712217	25	0	0
CheckClr_A	727712217	254	0	0
CheckEn_A	727596159	324646369	0	0
CheckPhase0_A	727712217	598	0	0
CheckPhase1_A	727712217	590	0	0
CheckPhase2_A	727712217	577	0	0
CheckPhase3_A	727712217	558	0	0
CheckTimeout0_A	727712217	690	0	0
CheckTimeoutSt1_A	727712217	81801	0	0
CheckTimeoutSt2_A	727712217	606	0	0
CheckTimeoutStTrig_A	727712217	58	0	0
ErrorStAllEscAsserted_A	727712217	1012	0	0
ErrorStIsTerminal_A	727712217	832	0	0
EscStateOut_A	727595321	727526509	0	0
u_state_regs_A	727712217	727567330	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	192	0	0
T8	17082	30	0	0
T9	0	22	0	0
T10	0	29	0	0
T37	0	45	0	0
T38	0	66	0	0
T39	210008	0	0	0
T40	649931	0	0	0
T41	245365	0	0	0
T42	274784	0	0	0
T43	129563	0	0	0
T44	383983	0	0	0
T45	900077	0	0	0
T46	869216	0	0	0
T47	2029	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	525	0	0
T1	50039	2	0	0
T2	239619	1	0	0
T3	111109	1	0	0
T6	530196	1	0	0
T7	0	1	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	0	0	0
T21	43933	1	0	0
T22	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	25	0	0
T2	239619	1	0	0
T3	111109	0	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	0	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T22	451213	0	0	0
T31	0	3	0	0
T34	0	1	0	0
T40	0	1	0	0
T55	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	254	0	0
T1	50039	1	0	0
T2	239619	1	0	0
T3	111109	0	0	0
T6	530196	1	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T13	0	1	0	0
T18	33710	0	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T31	0	8	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	3	0	0
T67	0	2	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727596159	324646369	0	0
T1	50039	2417	0	0
T2	239619	665126	0	0
T3	111109	4326	0	0
T6	530196	529642	0	0
T11	32010	31924	0	0
T12	36891	2154	0	0
T18	33710	33619	0	0
T19	17848	1738	0	0
T20	10802	10730	0	0
T21	43933	2995	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	598	0	0
T1	50039	2	0	0
T2	239619	2	0	0
T3	111109	1	0	0
T6	530196	0	0	0
T7	0	1	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	0	0	0
T21	43933	1	0	0
T22	0	1	0	0
T25	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	590	0	0
T1	50039	2	0	0
T2	239619	2	0	0
T3	111109	1	0	0
T6	530196	0	0	0
T7	0	1	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	0	0	0
T21	43933	1	0	0
T22	0	1	0	0
T25	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	577	0	0
T1	50039	2	0	0
T2	239619	2	0	0
T3	111109	1	0	0
T6	530196	0	0	0
T7	0	1	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	0	0	0
T21	43933	1	0	0
T22	0	1	0	0
T25	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	558	0	0
T1	50039	2	0	0
T2	239619	2	0	0
T3	111109	1	0	0
T6	530196	0	0	0
T7	0	1	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	0	0	0
T21	43933	1	0	0
T22	0	1	0	0
T25	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	690	0	0
T2	239619	4	0	0
T3	111109	0	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	0	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T22	451213	0	0	0
T25	0	4	0	0
T29	0	2	0	0
T30	0	3	0	0
T31	0	11	0	0
T32	0	4	0	0
T34	0	1	0	0
T35	0	2	0	0
T66	0	4	0	0
T67	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	81801	0	0
T2	239619	721	0	0
T3	111109	0	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	0	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T22	451213	0	0	0
T25	0	270	0	0
T29	0	720	0	0
T30	0	316	0	0
T31	0	772	0	0
T32	0	565	0	0
T34	0	1	0	0
T35	0	270	0	0
T66	0	710	0	0
T67	0	166	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	606	0	0
T2	239619	3	0	0
T3	111109	0	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	0	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T22	451213	0	0	0
T25	0	3	0	0
T29	0	1	0	0
T30	0	2	0	0
T31	0	8	0	0
T32	0	4	0	0
T35	0	2	0	0
T66	0	3	0	0
T67	0	2	0	0
T78	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	58	0	0
T4	303092	0	0	0
T5	73203	0	0	0
T17	224344	0	0	0
T25	26975	1	0	0
T26	26562	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	734634	0	0	0
T32	103272	0	0	0
T49	143657	0	0	0
T53	0	1	0	0
T66	0	1	0	0
T75	24656	0	0	0
T79	0	1	0	0
T83	0	2	0	0
T85	611190	0	0	0
T86	0	2	0	0
T91	0	2	0	0
T96	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	1012	0	0
T8	17082	158	0	0
T9	0	164	0	0
T10	0	166	0	0
T37	0	187	0	0
T38	0	337	0	0
T39	210008	0	0	0
T40	649931	0	0	0
T41	245365	0	0	0
T42	274784	0	0	0
T43	129563	0	0	0
T44	383983	0	0	0
T45	900077	0	0	0
T46	869216	0	0	0
T47	2029	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	832	0	0
T8	17082	128	0	0
T9	0	134	0	0
T10	0	136	0	0
T37	0	157	0	0
T38	0	277	0	0
T39	210008	0	0	0
T40	649931	0	0	0
T41	245365	0	0	0
T42	274784	0	0	0
T43	129563	0	0	0
T44	383983	0	0	0
T45	900077	0	0	0
T46	869216	0	0	0
T47	2029	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727595321	727526509	0	0
T1	50039	49982	0	0
T2	239619	239608	0	0
T3	111109	111104	0	0
T6	530196	530190	0	0
T11	32010	31925	0	0
T12	36891	36839	0	0
T18	33710	33620	0	0
T19	17848	17748	0	0
T20	10802	10731	0	0
T21	43933	43868	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	727567330	0	0
T1	50039	49982	0	0
T2	239619	239608	0	0
T3	111109	111104	0	0
T6	530196	530190	0	0
T11	32010	31925	0	0
T12	36891	36839	0	0
T18	33710	33620	0	0
T19	17848	17748	0	0
T20	10802	10731	0	0
T21	43933	43868	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T24
1	1	1	Covered	T11,T6,T19

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T18
1	0	1	Covered	T19,T22,T15
1	1	0	Covered	T2,T3,T18
1	1	1	Covered	T1,T2,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T18
0	1	Covered	T1,T2,T66
1	0	Covered	T31,T50,T29

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T31,T50,T29

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Not Covered
1	1	Covered	T1,T2,T66

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T31,T97,T50

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T14,T32,T66

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T11,T6,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T6,T19
1	Covered	T1,T2,T7

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T6,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T6,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T11
Phase1St	198	Covered	T1,T2,T11
Phase2St	215	Covered	T1,T2,T11
Phase3St	233	Covered	T1,T2,T11
TerminalSt	249	Covered	T1,T2,T11
TimeoutSt	159	Covered	T1,T2,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T11,T6,T19
IdleSt->TimeoutSt	159	Covered	T1,T2,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T29,T30,T98
Phase0St->Phase1St	198	Covered	T1,T2,T11
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T31,T33,T55
Phase1St->Phase2St	215	Covered	T1,T2,T11
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T41,T99,T100
Phase2St->Phase3St	233	Covered	T1,T2,T11
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T31,T32,T36
Phase3St->TerminalSt	249	Covered	T1,T2,T11
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T2,T18
TimeoutSt->Phase0St	172	Covered	T1,T2,T31

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T6,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T31
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T30,T98
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T33,T55
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T41,T99,T100
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T31,T32,T36
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T31,T32
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	727712217	155	0	0
CheckAccumTrig0_A	727712217	530	0	0
CheckAccumTrig1_A	727712217	26	0	0
CheckClr_A	727712217	235	0	0
CheckEn_A	727596159	307490740	0	0
CheckPhase0_A	727712217	592	0	0
CheckPhase1_A	727712217	575	0	0
CheckPhase2_A	727712217	566	0	0
CheckPhase3_A	727712217	552	0	0
CheckTimeout0_A	727712217	891	0	0
CheckTimeoutSt1_A	727712217	112601	0	0
CheckTimeoutSt2_A	727712217	817	0	0
CheckTimeoutStTrig_A	727712217	46	0	0
ErrorStAllEscAsserted_A	727712217	980	0	0
ErrorStIsTerminal_A	727712217	800	0	0
EscStateOut_A	727595321	727526509	0	0
u_state_regs_A	727712217	727567330	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	155	0	0
T8	17082	18	0	0
T9	0	18	0	0
T10	0	38	0	0
T37	0	28	0	0
T38	0	53	0	0
T39	210008	0	0	0
T40	649931	0	0	0
T41	245365	0	0	0
T42	274784	0	0	0
T43	129563	0	0	0
T44	383983	0	0	0
T45	900077	0	0	0
T46	869216	0	0	0
T47	2029	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	530	0	0
T4	0	1	0	0
T6	530196	1	0	0
T7	958355	1	0	0
T11	32010	1	0	0
T12	36891	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	0	0	0
T21	43933	1	0	0
T22	451213	0	0	0
T31	0	5	0	0
T48	3637	0	0	0
T49	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	26	0	0
T29	0	1	0	0
T31	734634	1	0	0
T32	103272	0	0	0
T40	0	1	0	0
T50	0	1	0	0
T54	0	1	0	0
T58	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	17573	0	0	0
T65	315546	0	0	0
T66	416380	0	0	0
T67	21174	0	0	0
T68	15975	0	0	0
T69	1512	0	0	0
T70	915016	0	0	0
T71	59417	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	235	0	0
T1	50039	1	0	0
T2	239619	0	0	0
T3	111109	0	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	0	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T29	0	2	0	0
T31	0	5	0	0
T32	0	4	0	0
T33	0	1	0	0
T34	0	2	0	0
T50	0	1	0	0
T72	0	1	0	0
T73	0	3	0	0
T74	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727596159	307490740	0	0
T1	50039	2400	0	0
T2	239619	648669	0	0
T3	111109	111103	0	0
T6	530196	13762	0	0
T11	32010	2074	0	0
T12	36891	36838	0	0
T18	33710	5718	0	0
T19	17848	1730	0	0
T20	10802	10730	0	0
T21	43933	19937	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	592	0	0
T1	50039	2	0	0
T2	239619	1	0	0
T3	111109	0	0	0
T4	0	1	0	0
T6	530196	1	0	0
T7	0	1	0	0
T11	32010	1	0	0
T12	36891	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	0	0	0
T21	43933	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	575	0	0
T1	50039	2	0	0
T2	239619	1	0	0
T3	111109	0	0	0
T4	0	1	0	0
T6	530196	1	0	0
T7	0	1	0	0
T11	32010	1	0	0
T12	36891	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	0	0	0
T21	43933	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	566	0	0
T1	50039	2	0	0
T2	239619	1	0	0
T3	111109	0	0	0
T4	0	1	0	0
T6	530196	1	0	0
T7	0	1	0	0
T11	32010	1	0	0
T12	36891	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	0	0	0
T21	43933	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	552	0	0
T1	50039	2	0	0
T2	239619	1	0	0
T3	111109	0	0	0
T4	0	1	0	0
T6	530196	1	0	0
T7	0	1	0	0
T11	32010	1	0	0
T12	36891	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	0	0	0
T21	43933	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	891	0	0
T1	50039	3	0	0
T2	239619	2	0	0
T3	111109	0	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	7	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T25	0	2	0	0
T31	0	3	0	0
T32	0	2	0	0
T50	0	6	0	0
T66	0	4	0	0
T75	0	4	0	0
T76	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	112601	0	0
T1	50039	742	0	0
T2	239619	1112	0	0
T3	111109	0	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	662	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T25	0	142	0	0
T31	0	191	0	0
T32	0	47	0	0
T50	0	1101	0	0
T66	0	970	0	0
T75	0	727	0	0
T76	0	57	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	817	0	0
T1	50039	1	0	0
T2	239619	1	0	0
T3	111109	0	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	7	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T25	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T50	0	5	0	0
T66	0	2	0	0
T75	0	4	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	46	0	0
T1	50039	2	0	0
T2	239619	1	0	0
T3	111109	0	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	0	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T29	0	1	0	0
T36	0	2	0	0
T54	0	1	0	0
T66	0	2	0	0
T73	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	980	0	0
T8	17082	181	0	0
T9	0	178	0	0
T10	0	185	0	0
T37	0	130	0	0
T38	0	306	0	0
T39	210008	0	0	0
T40	649931	0	0	0
T41	245365	0	0	0
T42	274784	0	0	0
T43	129563	0	0	0
T44	383983	0	0	0
T45	900077	0	0	0
T46	869216	0	0	0
T47	2029	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	800	0	0
T8	17082	151	0	0
T9	0	148	0	0
T10	0	155	0	0
T37	0	100	0	0
T38	0	246	0	0
T39	210008	0	0	0
T40	649931	0	0	0
T41	245365	0	0	0
T42	274784	0	0	0
T43	129563	0	0	0
T44	383983	0	0	0
T45	900077	0	0	0
T46	869216	0	0	0
T47	2029	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727595321	727526509	0	0
T1	50039	49982	0	0
T2	239619	239608	0	0
T3	111109	111104	0	0
T6	530196	530190	0	0
T11	32010	31925	0	0
T12	36891	36839	0	0
T18	33710	33620	0	0
T19	17848	17748	0	0
T20	10802	10731	0	0
T21	43933	43868	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	727567330	0	0
T1	50039	49982	0	0
T2	239619	239608	0	0
T3	111109	111104	0	0
T6	530196	530190	0	0
T11	32010	31925	0	0
T12	36891	36839	0	0
T18	33710	33620	0	0
T19	17848	17748	0	0
T20	10802	10731	0	0
T21	43933	43868	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T23
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T11
1	0	1	Covered	T3,T11,T22
1	1	0	Covered	T2,T18,T21
1	1	1	Covered	T1,T2,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T18
0	1	Covered	T1,T2,T25
1	0	Covered	T2,T4,T29

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T29

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T27,T28
1	1	Covered	T1,T2,T25

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T22,T85

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19,T21,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T11,T6
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T15

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T6,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T2,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T2,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T88,T62,T41
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T29,T55,T95
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T36,T101,T102
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T13,T72,T103
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T25
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T18,T25
TimeoutSt->Phase0St	172	Covered	T1,T2,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T25
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T88,T62,T41
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T55,T95
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T36,T101,T102
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T13,T72,T103
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T25
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	727712217	176	0	0
CheckAccumTrig0_A	727712217	474	0	0
CheckAccumTrig1_A	727712217	22	0	0
CheckClr_A	727712217	211	0	0
CheckEn_A	727596159	312621072	0	0
CheckPhase0_A	727712217	567	0	0
CheckPhase1_A	727712217	559	0	0
CheckPhase2_A	727712217	546	0	0
CheckPhase3_A	727712217	534	0	0
CheckTimeout0_A	727712217	1035	0	0
CheckTimeoutSt1_A	727712217	105168	0	0
CheckTimeoutSt2_A	727712217	936	0	0
CheckTimeoutStTrig_A	727712217	76	0	0
ErrorStAllEscAsserted_A	727712217	941	0	0
ErrorStIsTerminal_A	727712217	761	0	0
EscStateOut_A	727595321	727526509	0	0
u_state_regs_A	727712217	727567330	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	176	0	0
T8	17082	30	0	0
T9	0	39	0	0
T10	0	33	0	0
T37	0	31	0	0
T38	0	43	0	0
T39	210008	0	0	0
T40	649931	0	0	0
T41	245365	0	0	0
T42	274784	0	0	0
T43	129563	0	0	0
T44	383983	0	0	0
T45	900077	0	0	0
T46	869216	0	0	0
T47	2029	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	474	0	0
T1	50039	1	0	0
T2	239619	1	0	0
T3	111109	1	0	0
T6	530196	1	0	0
T11	32010	1	0	0
T12	36891	0	0	0
T13	0	2	0	0
T15	0	1	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	0	0	0
T21	43933	1	0	0
T22	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	22	0	0
T2	239619	1	0	0
T3	111109	0	0	0
T4	0	1	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	0	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T22	451213	0	0	0
T29	0	2	0	0
T41	0	2	0	0
T55	0	1	0	0
T62	0	1	0	0
T89	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	211	0	0
T1	50039	1	0	0
T2	239619	1	0	0
T3	111109	0	0	0
T4	0	1	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T13	0	1	0	0
T18	33710	0	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T25	0	1	0	0
T29	0	2	0	0
T35	0	5	0	0
T50	0	2	0	0
T66	0	1	0	0
T72	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727596159	312621072	0	0
T1	50039	2406	0	0
T2	239619	955256	0	0
T3	111109	1883	0	0
T6	530196	8645	0	0
T11	32010	5747	0	0
T12	36891	36838	0	0
T18	33710	31527	0	0
T19	17848	5378	0	0
T20	10802	10730	0	0
T21	43933	14843	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	567	0	0
T1	50039	2	0	0
T2	239619	3	0	0
T3	111109	1	0	0
T6	530196	1	0	0
T11	32010	1	0	0
T12	36891	0	0	0
T13	0	2	0	0
T15	0	1	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	0	0	0
T21	43933	1	0	0
T22	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	559	0	0
T1	50039	2	0	0
T2	239619	3	0	0
T3	111109	1	0	0
T6	530196	1	0	0
T11	32010	1	0	0
T12	36891	0	0	0
T13	0	2	0	0
T15	0	1	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	0	0	0
T21	43933	1	0	0
T22	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	546	0	0
T1	50039	2	0	0
T2	239619	3	0	0
T3	111109	1	0	0
T6	530196	1	0	0
T11	32010	1	0	0
T12	36891	0	0	0
T13	0	2	0	0
T15	0	1	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	0	0	0
T21	43933	1	0	0
T22	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	534	0	0
T1	50039	2	0	0
T2	239619	3	0	0
T3	111109	1	0	0
T6	530196	1	0	0
T11	32010	1	0	0
T12	36891	0	0	0
T13	0	1	0	0
T15	0	1	0	0
T18	33710	0	0	0
T19	17848	1	0	0
T20	10802	0	0	0
T21	43933	1	0	0
T22	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	1035	0	0
T1	50039	2	0	0
T2	239619	2	0	0
T3	111109	0	0	0
T4	0	1	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	2	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T25	0	3	0	0
T32	0	2	0	0
T50	0	1	0	0
T66	0	3	0	0
T75	0	1	0	0
T77	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	105168	0	0
T1	50039	389	0	0
T2	239619	353	0	0
T3	111109	0	0	0
T4	0	2	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	192	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T25	0	119	0	0
T32	0	101	0	0
T50	0	94	0	0
T66	0	446	0	0
T75	0	156	0	0
T77	0	215	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	936	0	0
T1	50039	1	0	0
T2	239619	0	0	0
T3	111109	0	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	2	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T25	0	2	0	0
T29	0	1	0	0
T32	0	2	0	0
T35	0	3	0	0
T66	0	2	0	0
T73	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	76	0	0
T1	50039	1	0	0
T2	239619	1	0	0
T3	111109	0	0	0
T6	530196	0	0	0
T11	32010	0	0	0
T12	36891	0	0	0
T18	33710	0	0	0
T19	17848	0	0	0
T20	10802	0	0	0
T21	43933	0	0	0
T25	0	1	0	0
T30	0	1	0	0
T50	0	1	0	0
T53	0	2	0	0
T66	0	1	0	0
T73	0	1	0	0
T78	0	2	0	0
T81	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	941	0	0
T8	17082	164	0	0
T9	0	155	0	0
T10	0	184	0	0
T37	0	154	0	0
T38	0	284	0	0
T39	210008	0	0	0
T40	649931	0	0	0
T41	245365	0	0	0
T42	274784	0	0	0
T43	129563	0	0	0
T44	383983	0	0	0
T45	900077	0	0	0
T46	869216	0	0	0
T47	2029	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	761	0	0
T8	17082	134	0	0
T9	0	125	0	0
T10	0	154	0	0
T37	0	124	0	0
T38	0	224	0	0
T39	210008	0	0	0
T40	649931	0	0	0
T41	245365	0	0	0
T42	274784	0	0	0
T43	129563	0	0	0
T44	383983	0	0	0
T45	900077	0	0	0
T46	869216	0	0	0
T47	2029	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727595321	727526509	0	0
T1	50039	49982	0	0
T2	239619	239608	0	0
T3	111109	111104	0	0
T6	530196	530190	0	0
T11	32010	31925	0	0
T12	36891	36839	0	0
T18	33710	33620	0	0
T19	17848	17748	0	0
T20	10802	10731	0	0
T21	43933	43868	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727712217	727567330	0	0
T1	50039	49982	0	0
T2	239619	239608	0	0
T3	111109	111104	0	0
T6	530196	530190	0	0
T11	32010	31925	0	0
T12	36891	36839	0	0
T18	33710	33620	0	0
T19	17848	17748	0	0
T20	10802	10731	0	0
T21	43933	43868	0	0