Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62521922	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30310368

1

T1

118

T2

1881

T3

325

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14228600	1			T1	73		T2	667		T3	113
values[0x0]	38331487	1			T1	181		T2	2423		T3	449
values[0x1]	40272203	1			T1	199		T2	2379		T3	445

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53373082	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39459208

1

T1

173

T2

2320

T3

418

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	303358	1			T1	6		T2	36		T3	12
valid_sources[0x01]	298486	1			T1	4		T2	8		T3	6
valid_sources[0x02]	295969	1			T1	3		T2	18		T3	10
valid_sources[0x03]	307946	1			T1	1		T2	19		T6	896
valid_sources[0x04]	306134	1			T1	5		T2	16		T6	904
valid_sources[0x05]	304957	1			T1	3		T2	27		T3	7
valid_sources[0x06]	310979	1			T1	1		T2	23		T3	1
valid_sources[0x07]	303811	1			T1	2		T2	22		T6	879
valid_sources[0x08]	1239954	1			T1	3		T2	14		T6	861
valid_sources[0x09]	300596	1			T1	2		T2	14		T3	2
valid_sources[0x0a]	732295	1			T1	3		T2	19		T3	7
valid_sources[0x0b]	311655	1			T1	2		T2	18		T6	891
valid_sources[0x0c]	687275	1			T1	1		T2	38		T6	879
valid_sources[0x0d]	542248	1			T1	2		T2	17		T3	2
valid_sources[0x0e]	746590	1			T1	3		T2	20		T6	862
valid_sources[0x0f]	545063	1			T1	4		T2	30		T3	1
valid_sources[0x10]	304011	1			T1	1		T2	25		T3	10
valid_sources[0x11]	310886	1			T1	1		T2	18		T3	15
valid_sources[0x12]	294818	1			T2	13		T6	900		T11	37
valid_sources[0x13]	624138	1			T1	2		T2	18		T6	851
valid_sources[0x14]	538003	1			T1	2		T2	60		T3	2
valid_sources[0x15]	742823	1			T1	4		T2	8		T3	1
valid_sources[0x16]	304285	1			T1	3		T2	7		T3	4
valid_sources[0x17]	304394	1			T1	1		T2	9		T6	890
valid_sources[0x18]	306055	1			T1	2		T2	26		T3	2
valid_sources[0x19]	300009	1			T1	3		T2	12		T3	5
valid_sources[0x1a]	303061	1			T1	2		T2	4		T6	955
valid_sources[0x1b]	305927	1			T2	19		T3	5		T6	826
valid_sources[0x1c]	299063	1			T1	1		T2	7		T6	888
valid_sources[0x1d]	298640	1			T1	3		T2	10		T6	837
valid_sources[0x1e]	299857	1			T1	2		T2	28		T3	11
valid_sources[0x1f]	314347	1			T1	2		T2	17		T6	856
valid_sources[0x20]	309422	1			T1	2		T2	17		T3	7
valid_sources[0x21]	307542	1			T2	20		T3	2		T6	840
valid_sources[0x22]	302694	1			T1	2		T2	41		T6	871
valid_sources[0x23]	315712	1			T2	22		T6	879		T11	19
valid_sources[0x24]	308332	1			T1	2		T2	14		T6	876
valid_sources[0x25]	564975	1			T1	2		T2	11		T6	850
valid_sources[0x26]	854548	1			T2	29		T3	17		T6	876
valid_sources[0x27]	867633	1			T1	3		T2	20		T3	6
valid_sources[0x28]	299458	1			T1	2		T2	29		T3	7
valid_sources[0x29]	305732	1			T1	2		T2	28		T6	843
valid_sources[0x2a]	295029	1			T1	4		T2	15		T3	2
valid_sources[0x2b]	307574	1			T1	2		T2	14		T6	839
valid_sources[0x2c]	309047	1			T2	26		T6	866		T11	24
valid_sources[0x2d]	296546	1			T1	1		T2	31		T3	7
valid_sources[0x2e]	732455	1			T2	51		T3	5		T6	815
valid_sources[0x2f]	295458	1			T1	2		T2	16		T3	1
valid_sources[0x30]	314492	1			T1	5		T2	9		T6	841
valid_sources[0x31]	301863	1			T1	5		T2	40		T3	3
valid_sources[0x32]	536670	1			T1	4		T2	40		T6	916
valid_sources[0x33]	302305	1			T1	2		T2	27		T6	847
valid_sources[0x34]	301342	1			T1	1		T2	35		T6	861
valid_sources[0x35]	303652	1			T1	1		T2	16		T3	4
valid_sources[0x36]	593435	1			T1	3		T2	17		T6	936
valid_sources[0x37]	304204	1			T1	4		T2	17		T6	853
valid_sources[0x38]	312319	1			T1	3		T2	38		T3	3
valid_sources[0x39]	319973	1			T1	2		T2	23		T3	4
valid_sources[0x3a]	299812	1			T2	18		T3	2		T6	860
valid_sources[0x3b]	642591	1			T1	1		T2	69		T3	3
valid_sources[0x3c]	307567	1			T1	3		T2	14		T6	840
valid_sources[0x3d]	309225	1			T1	2		T2	10		T3	8
valid_sources[0x3e]	721558	1			T1	3		T2	24		T6	917
valid_sources[0x3f]	295214	1			T1	2		T2	37		T3	7
valid_sources[0x40]	308801	1			T1	1		T2	20		T3	4
valid_sources[0x41]	312523	1			T1	3		T2	19		T3	8
valid_sources[0x42]	338667	1			T1	2		T2	21		T3	16
valid_sources[0x43]	301766	1			T1	3		T2	20		T3	2
valid_sources[0x44]	292653	1			T1	1		T2	25		T6	860
valid_sources[0x45]	323655	1			T1	2		T2	18		T3	3
valid_sources[0x46]	297323	1			T1	1		T2	19		T3	1
valid_sources[0x47]	303217	1			T1	2		T2	24		T6	815
valid_sources[0x48]	343240	1			T1	1		T2	18		T6	889
valid_sources[0x49]	301088	1			T1	1		T2	15		T3	6
valid_sources[0x4a]	294084	1			T2	13		T3	5		T6	898
valid_sources[0x4b]	298475	1			T1	2		T2	28		T3	8
valid_sources[0x4c]	296411	1			T1	2		T2	37		T3	1
valid_sources[0x4d]	314854	1			T1	3		T2	15		T3	9
valid_sources[0x4e]	303901	1			T1	4		T2	30		T3	8
valid_sources[0x4f]	303702	1			T1	3		T2	27		T3	1
valid_sources[0x50]	310145	1			T1	1		T2	24		T3	2
valid_sources[0x51]	296402	1			T1	1		T2	22		T6	891
valid_sources[0x52]	303799	1			T2	18		T6	899		T11	18
valid_sources[0x53]	336900	1			T1	1		T2	26		T3	1
valid_sources[0x54]	307408	1			T2	30		T3	3		T6	857
valid_sources[0x55]	396542	1			T1	5		T2	37		T3	12
valid_sources[0x56]	304722	1			T1	2		T2	12		T3	1
valid_sources[0x57]	296448	1			T1	2		T2	13		T3	8
valid_sources[0x58]	306583	1			T1	1		T2	17		T3	3
valid_sources[0x59]	315808	1			T1	1		T2	16		T3	1
valid_sources[0x5a]	299746	1			T1	1		T2	31		T3	6
valid_sources[0x5b]	296673	1			T2	20		T3	7		T6	794
valid_sources[0x5c]	301424	1			T1	1		T2	11		T6	865
valid_sources[0x5d]	298611	1			T1	4		T2	25		T6	786
valid_sources[0x5e]	310444	1			T1	2		T2	19		T6	860
valid_sources[0x5f]	300532	1			T1	3		T2	11		T6	866
valid_sources[0x60]	304404	1			T2	6		T3	14		T6	839
valid_sources[0x61]	303050	1			T2	27		T6	869		T11	20
valid_sources[0x62]	345243	1			T1	3		T2	14		T6	855
valid_sources[0x63]	297032	1			T1	1		T2	20		T3	10
valid_sources[0x64]	303035	1			T1	4		T2	16		T6	860
valid_sources[0x65]	298697	1			T1	1		T2	27		T3	10
valid_sources[0x66]	534247	1			T2	20		T3	3		T6	832
valid_sources[0x67]	301444	1			T1	1		T2	13		T3	13
valid_sources[0x68]	310273	1			T2	25		T6	846		T11	31
valid_sources[0x69]	303043	1			T1	2		T2	19		T3	6
valid_sources[0x6a]	305152	1			T1	1		T2	19		T3	4
valid_sources[0x6b]	322534	1			T1	4		T2	2		T3	13
valid_sources[0x6c]	302070	1			T1	1		T2	21		T3	8
valid_sources[0x6d]	302104	1			T2	19		T3	3		T6	782
valid_sources[0x6e]	301580	1			T1	4		T2	23		T6	838
valid_sources[0x6f]	309826	1			T1	1		T2	39		T3	1
valid_sources[0x70]	507480	1			T1	2		T2	7		T3	26
valid_sources[0x71]	300181	1			T1	1		T2	27		T3	4
valid_sources[0x72]	294965	1			T1	1		T2	11		T3	2
valid_sources[0x73]	298878	1			T2	21		T6	879		T11	22
valid_sources[0x74]	298849	1			T1	2		T2	25		T3	2
valid_sources[0x75]	315801	1			T1	2		T2	37		T3	3
valid_sources[0x76]	314961	1			T1	2		T2	11		T6	876
valid_sources[0x77]	301592	1			T2	16		T3	1		T6	865
valid_sources[0x78]	297168	1			T1	2		T2	16		T3	3
valid_sources[0x79]	345618	1			T1	2		T2	14		T3	1
valid_sources[0x7a]	295015	1			T1	3		T2	24		T3	1
valid_sources[0x7b]	298842	1			T1	1		T2	48		T3	6
valid_sources[0x7c]	297600	1			T1	1		T2	30		T3	12
valid_sources[0x7d]	307256	1			T2	14		T3	1		T6	893
valid_sources[0x7e]	299700	1			T1	1		T2	17		T3	13
valid_sources[0x7f]	316677	1			T1	3		T2	24		T3	2
valid_sources[0x80]	547212	1			T2	12		T3	3		T6	871

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7043790

1

T1

34

T2

346

T3

56

values[0x0]

all_enables

biggest_size

14681655

1

T1

51

T2

949

T3

159

values[0x1]

all_enables

biggest_size

8584923

1

T1

33

T2

586

T3

110