Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T11
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T55,T200,T201
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15712	0	0
DisabledNoTrigBkwd_A	2147483647	800362	0	0
DisabledNoTrigFwd_A	2147483647	1400402739	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15712	0	0
T52	481414	0	0	0
T55	0	835	0	0
T77	71481	0	0	0
T98	157048	0	0	0
T113	42511	0	0	0
T171	278993	0	0	0
T174	0	1113	0	0
T200	3974	1045	0	0
T201	7164	456	0	0
T202	0	1260	0	0
T203	0	1105	0	0
T204	0	675	0	0
T205	2928	605	0	0
T206	0	1031	0	0
T207	0	1213	0	0
T208	0	592	0	0
T209	0	591	0	0
T210	0	862	0	0
T211	0	343	0	0
T212	0	620	0	0
T213	0	456	0	0
T214	0	1549	0	0
T215	0	223	0	0
T216	0	610	0	0
T217	0	528	0	0
T218	124398	0	0	0
T219	35688	0	0	0
T220	1633616	0	0	0
T221	406552	0	0	0
T222	9666	0	0	0
T223	118224	0	0	0
T224	11508	0	0	0
T225	886827	0	0	0
T226	251797	0	0	0
T227	281768	0	0	0
T228	72455	0	0	0
T229	67036	0	0	0
T230	103405	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	800362	0	0
T2	24199	3	0	0
T3	10164	0	0	0
T4	919068	202	0	0
T5	46650	0	0	0
T6	1833843	3	0	0
T7	723687	2	0	0
T8	92130	0	0	0
T11	191937	54	0	0
T12	99090	21	0	0
T13	233079	36	0	0
T14	139596	4524	0	0
T15	448331	2137	0	0
T16	137082	2	0	0
T17	2180637	6	0	0
T18	926415	278	0	0
T21	165733	4241	0	0
T22	15952	22	0	0
T31	892429	3902	0	0
T35	33794	2	0	0
T36	18706	0	0	0
T37	0	53	0	0
T38	0	873	0	0
T39	0	2140	0	0
T40	0	1	0	0
T54	0	1196	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1400402739	0	0
T1	62208	14591	0	0
T2	96796	71739	0	0
T3	40656	32301	0	0
T4	1225424	615862	0	0
T5	62200	21907	0	0
T6	2445124	1827147	0	0
T7	964916	637509	0	0
T11	255916	148024	0	0
T12	132120	101993	0	0
T17	2907516	2896495	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T11
1	1	Covered	T2,T3,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T200,T210,T211
1	1	Covered	T2,T3,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T11,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	657025895	5160	0	0
DisabledNoTrigBkwd_A	657025895	244091	0	0
DisabledNoTrigFwd_A	657025895	288349021	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	5160	0	0
T98	78524	0	0	0
T200	3974	1045	0	0
T201	3582	0	0	0
T210	0	862	0	0
T211	0	343	0	0
T214	0	1549	0	0
T215	0	223	0	0
T216	0	610	0	0
T217	0	528	0	0
T218	124398	0	0	0
T219	17844	0	0	0
T220	816808	0	0	0
T221	203276	0	0	0
T222	4833	0	0	0
T223	59112	0	0	0
T224	5754	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	244091	0	0
T2	24199	3	0	0
T3	10164	0	0	0
T4	306356	106	0	0
T5	15550	0	0	0
T6	611281	0	0	0
T7	241229	0	0	0
T11	63979	9	0	0
T12	33030	21	0	0
T15	0	86	0	0
T16	0	2	0	0
T17	726879	0	0	0
T18	308805	277	0	0
T21	0	2300	0	0
T31	0	870	0	0
T35	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	288349021	0	0
T1	15552	3617	0	0
T2	24199	1725	0	0
T3	10164	2094	0	0
T4	306356	8732	0	0
T5	15550	2154	0	0
T6	611281	608211	0	0
T7	241229	241148	0	0
T11	63979	24052	0	0
T12	33030	3095	0	0
T17	726879	726783	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T11
1	0	Covered	T6,T11,T7
1	1	Covered	T1,T6,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T203,T204
1	1	Covered	T1,T6,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T7,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T11

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	657025895	2827	0	0
DisabledNoTrigBkwd_A	657025895	202273	0	0
DisabledNoTrigFwd_A	657025895	372643440	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	2827	0	0
T77	71481	0	0	0
T98	78524	0	0	0
T201	3582	456	0	0
T203	0	1105	0	0
T204	0	675	0	0
T209	0	591	0	0
T219	17844	0	0	0
T220	816808	0	0	0
T221	203276	0	0	0
T222	4833	0	0	0
T223	59112	0	0	0
T224	5754	0	0	0
T225	886827	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	202273	0	0
T4	306356	96	0	0
T5	15550	0	0	0
T6	611281	2	0	0
T7	241229	2	0	0
T8	30710	0	0	0
T11	63979	39	0	0
T12	33030	0	0	0
T13	77693	0	0	0
T14	0	3073	0	0
T15	0	383	0	0
T17	726879	6	0	0
T18	308805	1	0	0
T22	0	7	0	0
T37	0	17	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	372643440	0	0
T1	15552	3633	0	0
T2	24199	24100	0	0
T3	10164	10069	0	0
T4	306356	8881	0	0
T5	15550	15373	0	0
T6	611281	606861	0	0
T7	241229	95757	0	0
T11	63979	41901	0	0
T12	33030	32966	0	0
T17	726879	716146	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T6,T11,T7
1	1	Covered	T4,T13,T16

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T205,T206,T208
1	1	Covered	T4,T13,T16

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T14,T15

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	657025895	2228	0	0
DisabledNoTrigBkwd_A	657025895	187874	0	0
DisabledNoTrigFwd_A	657025895	356254905	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	2228	0	0
T52	481414	0	0	0
T113	42511	0	0	0
T171	278993	0	0	0
T205	2928	605	0	0
T206	0	1031	0	0
T208	0	592	0	0
T226	251797	0	0	0
T227	281768	0	0	0
T228	72455	0	0	0
T229	67036	0	0	0
T230	103405	0	0	0
T231	115861	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	187874	0	0
T8	30710	0	0	0
T13	77693	36	0	0
T14	139596	8	0	0
T15	448331	104	0	0
T16	137082	0	0	0
T21	165733	1941	0	0
T22	15952	15	0	0
T31	892429	3032	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	0	36	0	0
T38	0	443	0	0
T39	0	2140	0	0
T40	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	356254905	0	0
T1	15552	3658	0	0
T2	24199	22957	0	0
T3	10164	10069	0	0
T4	306356	302871	0	0
T5	15550	2180	0	0
T6	611281	611195	0	0
T7	241229	186107	0	0
T11	63979	63896	0	0
T12	33030	32966	0	0
T17	726879	726783	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T11,T17,T4
1	1	Covered	T6,T11,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T55,T202,T174
1	1	Covered	T6,T11,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T11,T14

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	657025895	5497	0	0
DisabledNoTrigBkwd_A	657025895	166124	0	0
DisabledNoTrigFwd_A	657025895	383155373	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	5497	0	0
T20	160213	0	0	0
T23	120976	0	0	0
T38	391927	0	0	0
T39	433675	0	0	0
T40	6573	0	0	0
T55	4156	835	0	0
T56	124055	0	0	0
T84	34297	0	0	0
T174	0	1113	0	0
T202	0	1260	0	0
T207	0	1213	0	0
T212	0	620	0	0
T213	0	456	0	0
T232	28766	0	0	0
T233	592414	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	166124	0	0
T4	306356	0	0	0
T5	15550	0	0	0
T6	611281	1	0	0
T7	241229	0	0	0
T8	30710	0	0	0
T11	63979	6	0	0
T12	33030	0	0	0
T13	77693	0	0	0
T14	0	1443	0	0
T15	0	1564	0	0
T17	726879	0	0	0
T18	308805	0	0	0
T38	0	430	0	0
T54	0	1196	0	0
T55	0	7	0	0
T64	0	285	0	0
T84	0	38	0	0
T96	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	383155373	0	0
T1	15552	3683	0	0
T2	24199	22957	0	0
T3	10164	10069	0	0
T4	306356	295378	0	0
T5	15550	2200	0	0
T6	611281	880	0	0
T7	241229	114497	0	0
T11	63979	18175	0	0
T12	33030	32966	0	0
T17	726879	726783	0	0