Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	100.00	89.36		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T11
1	0	1	Covered	T6,T7,T12
1	1	0	Covered	T2,T11,T13
1	1	1	Covered	T11,T13,T15

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T15
0	1	Covered	T13,T15,T22
1	0	Covered	T15,T22,T23

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T13,T15
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T15,T22,T23

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T15
1	0	Not Covered
1	1	Covered	T13,T15,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T11
1	Covered	T7,T17,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T11
1	Covered	T11,T4,T18

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T7
1	Covered	T6,T11,T12

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T11,T7
1	Covered	T2,T11,T12

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T12,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T6,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T6,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T7,T17

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T6,T11
Phase1St	198	Covered	T2,T6,T11
Phase2St	215	Covered	T2,T6,T11
Phase3St	233	Covered	T2,T6,T11
TerminalSt	249	Covered	T2,T6,T11
TimeoutSt	159	Covered	T11,T13,T15

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T2,T6,T11
IdleSt->TimeoutSt	159	Covered	T11,T13,T15
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T15,T24,T25
Phase0St->Phase1St	198	Covered	T2,T6,T11
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T13,T21,T26
Phase1St->Phase2St	215	Covered	T2,T6,T11
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T27,T28,T29
Phase2St->Phase3St	233	Covered	T2,T6,T11
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T15,T27,T30
Phase3St->TerminalSt	249	Covered	T2,T6,T11
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T2,T11,T12
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T13,T15,T31
TimeoutSt->Phase0St	172	Covered	T13,T15,T22

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T13,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T15,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T11,T13,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T15,T31
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T32,T30
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T6,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T6,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T13,T21,T26
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T6,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T6,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T28,T29
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T6,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T6,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T15,T27,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T6,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T6,T11,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T11,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T6,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1015	0	0
CheckAccumTrig0_A	2147483647	2255	0	0
CheckAccumTrig1_A	2147483647	107	0	0
CheckClr_A	2147483647	1016	0	0
CheckEn_A	2147483647	1117130832	0	0
CheckPhase0_A	2147483647	2520	0	0
CheckPhase1_A	2147483647	2482	0	0
CheckPhase2_A	2147483647	2433	0	0
CheckPhase3_A	2147483647	2374	0	0
CheckTimeout0_A	2147483647	4877	0	0
CheckTimeoutSt1_A	2147483647	498301	0	0
CheckTimeoutSt2_A	2147483647	4558	0	0
CheckTimeoutStTrig_A	2147483647	205	0	0
ErrorStAllEscAsserted_A	2147483647	5256	0	0
ErrorStIsTerminal_A	2147483647	4296	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1015	0	0
T8	122840	295	0	0
T9	0	122	0	0
T10	0	261	0	0
T14	558384	0	0	0
T15	1793324	0	0	0
T16	548328	0	0	0
T21	662932	0	0	0
T22	63808	0	0	0
T31	3569716	0	0	0
T33	0	107	0	0
T34	0	230	0	0
T35	135176	0	0	0
T36	74824	0	0	0
T37	322344	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2255	0	0
T2	24199	2	0	0
T3	10164	0	0	0
T4	919068	2	0	0
T5	46650	0	0	0
T6	1833843	1	0	0
T7	723687	1	0	0
T8	92130	0	0	0
T11	191937	3	0	0
T12	99090	4	0	0
T13	233079	1	0	0
T14	139596	2	0	0
T15	448331	14	0	0
T16	137082	1	0	0
T17	2180637	1	0	0
T18	926415	3	0	0
T21	165733	11	0	0
T22	15952	1	0	0
T23	0	1	0	0
T31	892429	3	0	0
T35	33794	1	0	0
T36	18706	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	107	0	0
T15	448331	2	0	0
T19	225128	0	0	0
T21	165733	0	0	0
T22	31904	1	0	0
T23	0	1	0	0
T25	0	1	0	0
T27	0	1	0	0
T28	0	2	0	0
T29	0	2	0	0
T30	0	2	0	0
T31	892429	0	0	0
T35	33794	0	0	0
T36	37412	0	0	0
T37	161172	0	0	0
T41	0	1	0	0
T42	106214	2	0	0
T43	714953	1	0	0
T44	132280	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	559522	0	0	0
T55	8312	0	0	0
T56	124055	0	0	0
T57	2389	0	0	0
T58	59047	0	0	0
T59	309356	0	0	0
T60	41429	0	0	0
T61	277760	0	0	0
T62	68222	0	0	0
T63	32565	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1016	0	0
T2	24199	1	0	0
T3	10164	0	0	0
T4	612712	0	0	0
T5	31100	0	0	0
T6	611281	0	0	0
T7	482458	0	0	0
T8	30710	0	0	0
T11	127958	1	0	0
T12	66060	4	0	0
T13	77693	1	0	0
T15	448331	6	0	0
T16	137082	0	0	0
T17	1453758	0	0	0
T18	617610	1	0	0
T21	165733	9	0	0
T22	15952	2	0	0
T25	0	4	0	0
T27	0	10	0	0
T30	0	8	0	0
T31	892429	1	0	0
T32	0	3	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T42	0	6	0	0
T46	0	1	0	0
T54	279761	1	0	0
T57	0	1	0	0
T59	0	2	0	0
T63	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1117130832	0	0
T1	62208	14587	0	0
T2	96796	71736	0	0
T3	40656	32298	0	0
T4	1225424	615860	0	0
T5	62200	21902	0	0
T6	2445124	1225403	0	0
T7	964916	544778	0	0
T11	255916	95045	0	0
T12	132120	101990	0	0
T17	2907516	2186043	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2520	0	0
T2	24199	2	0	0
T3	10164	0	0	0
T4	919068	2	0	0
T5	46650	0	0	0
T6	1833843	2	0	0
T7	723687	1	0	0
T8	92130	0	0	0
T11	191937	4	0	0
T12	99090	4	0	0
T13	233079	3	0	0
T14	139596	3	0	0
T15	448331	26	0	0
T16	137082	1	0	0
T17	2180637	1	0	0
T18	926415	3	0	0
T21	165733	11	0	0
T22	15952	4	0	0
T31	892429	3	0	0
T35	33794	1	0	0
T36	18706	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T54	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2482	0	0
T2	24199	2	0	0
T3	10164	0	0	0
T4	919068	2	0	0
T5	46650	0	0	0
T6	1833843	2	0	0
T7	723687	1	0	0
T8	92130	0	0	0
T11	191937	4	0	0
T12	99090	4	0	0
T13	233079	2	0	0
T14	139596	3	0	0
T15	448331	26	0	0
T16	137082	1	0	0
T17	2180637	1	0	0
T18	926415	3	0	0
T21	165733	10	0	0
T22	15952	4	0	0
T31	892429	3	0	0
T35	33794	1	0	0
T36	18706	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T54	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2433	0	0
T2	24199	2	0	0
T3	10164	0	0	0
T4	919068	2	0	0
T5	46650	0	0	0
T6	1833843	2	0	0
T7	723687	1	0	0
T8	92130	0	0	0
T11	191937	4	0	0
T12	99090	4	0	0
T13	233079	2	0	0
T14	139596	3	0	0
T15	448331	26	0	0
T16	137082	1	0	0
T17	2180637	1	0	0
T18	926415	3	0	0
T21	165733	10	0	0
T22	15952	4	0	0
T31	892429	3	0	0
T35	33794	1	0	0
T36	18706	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T54	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2374	0	0
T2	24199	2	0	0
T3	10164	0	0	0
T4	919068	2	0	0
T5	46650	0	0	0
T6	1833843	2	0	0
T7	723687	1	0	0
T8	92130	0	0	0
T11	191937	4	0	0
T12	99090	4	0	0
T13	233079	2	0	0
T14	139596	3	0	0
T15	448331	25	0	0
T16	137082	1	0	0
T17	2180637	1	0	0
T18	926415	3	0	0
T21	165733	10	0	0
T22	15952	4	0	0
T31	892429	3	0	0
T35	33794	1	0	0
T36	18706	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T54	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4877	0	0
T4	306356	0	0	0
T5	15550	0	0	0
T7	241229	0	0	0
T8	92130	0	0	0
T11	63979	2	0	0
T12	33030	0	0	0
T13	233079	6	0	0
T14	279192	0	0	0
T15	1344993	87	0	0
T16	411246	0	0	0
T17	726879	0	0	0
T18	308805	0	0	0
T19	112564	0	0	0
T21	497199	0	0	0
T22	47856	5	0	0
T23	0	3	0	0
T25	0	26	0	0
T31	2677287	1	0	0
T35	101382	0	0	0
T36	56118	0	0	0
T37	80586	11	0	0
T39	0	74	0	0
T41	0	22	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	20	0	0
T54	279761	0	0	0
T55	4156	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	19	0	0
T62	0	1	0	0
T64	0	5	0	0
T65	0	3	0	0
T66	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	498301	0	0
T4	306356	0	0	0
T5	15550	0	0	0
T7	241229	0	0	0
T8	92130	0	0	0
T11	63979	78	0	0
T12	33030	0	0	0
T13	233079	970	0	0
T14	279192	0	0	0
T15	1344993	20335	0	0
T16	411246	0	0	0
T17	726879	0	0	0
T18	308805	0	0	0
T19	112564	0	0	0
T21	497199	0	0	0
T22	47856	382	0	0
T23	0	88	0	0
T24	0	214	0	0
T25	0	3517	0	0
T31	2677287	101	0	0
T35	101382	0	0	0
T36	56118	0	0	0
T37	80586	1459	0	0
T39	0	2929	0	0
T41	0	2678	0	0
T42	0	11	0	0
T43	0	6	0	0
T45	0	3058	0	0
T54	279761	0	0	0
T55	4156	0	0	0
T57	0	52	0	0
T58	0	109	0	0
T59	0	3321	0	0
T62	0	72	0	0
T64	0	1746	0	0
T65	0	585	0	0
T66	0	985	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4558	0	0
T7	241229	0	0	0
T8	61420	0	0	0
T11	63979	0	0	0
T12	33030	0	0	0
T13	155386	4	0	0
T14	139596	0	0	0
T15	896662	40	0	0
T16	274164	0	0	0
T17	726879	0	0	0
T19	225128	0	0	0
T20	160213	0	0	0
T21	331466	0	0	0
T22	47856	2	0	0
T23	0	2	0	0
T25	0	22	0	0
T27	0	50	0	0
T30	0	6	0	0
T31	2677287	1	0	0
T35	67588	0	0	0
T36	56118	0	0	0
T37	161172	7	0	0
T38	391927	0	0	0
T39	0	74	0	0
T41	0	20	0	0
T45	0	10	0	0
T46	0	2	0	0
T54	559522	0	0	0
T55	8312	0	0	0
T56	124055	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	10	0	0
T63	0	2	0	0
T64	0	2	0	0
T65	0	7	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	205	0	0
T8	30710	0	0	0
T13	77693	2	0	0
T14	139596	0	0	0
T15	1344993	3	0	0
T16	137082	0	0	0
T19	225128	0	0	0
T21	497199	0	0	0
T22	47856	2	0	0
T25	0	2	0	0
T27	0	6	0	0
T29	0	2	0	0
T30	0	3	0	0
T31	2677287	0	0	0
T35	101382	0	0	0
T36	56118	0	0	0
T37	161172	0	0	0
T41	305037	0	0	0
T42	106214	0	0	0
T43	714953	0	0	0
T45	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T52	0	3	0	0
T54	559522	0	0	0
T55	8312	0	0	0
T57	2389	0	0	0
T58	59047	0	0	0
T59	309356	0	0	0
T62	0	1	0	0
T64	192695	1	0	0
T66	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5256	0	0
T8	122840	1285	0	0
T9	0	649	0	0
T10	0	1371	0	0
T14	558384	0	0	0
T15	1793324	0	0	0
T16	548328	0	0	0
T21	662932	0	0	0
T22	63808	0	0	0
T31	3569716	0	0	0
T33	0	688	0	0
T34	0	1263	0	0
T35	135176	0	0	0
T36	74824	0	0	0
T37	322344	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4296	0	0
T8	122840	1045	0	0
T9	0	529	0	0
T10	0	1131	0	0
T14	558384	0	0	0
T15	1793324	0	0	0
T16	548328	0	0	0
T21	662932	0	0	0
T22	63808	0	0	0
T31	3569716	0	0	0
T33	0	568	0	0
T34	0	1023	0	0
T35	135176	0	0	0
T36	74824	0	0	0
T37	322344	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	62208	61440	0	0
T2	96796	96400	0	0
T3	40656	40276	0	0
T4	1225424	1224748	0	0
T5	62200	61492	0	0
T6	2445124	2444780	0	0
T7	964916	964592	0	0
T11	255916	255584	0	0
T12	132120	131864	0	0
T17	2907516	2907132	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	62208	61440	0	0
T2	96796	96400	0	0
T3	40656	40276	0	0
T4	1225424	1224748	0	0
T5	62200	61492	0	0
T6	2445124	2444780	0	0
T7	964916	964592	0	0
T11	255916	255584	0	0
T12	132120	131864	0	0
T17	2907516	2907132	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T11,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T11,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T11,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T11
1	0	1	Covered	T12,T4,T18
1	1	0	Covered	T2,T13,T15
1	1	1	Covered	T15,T31,T37

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T15,T31,T37
0	1	Covered	T15,T64,T45
1	0	Covered	T42,T25,T45

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T15,T31,T37
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T42,T25,T45

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T31,T37
1	0	Not Covered
1	1	Covered	T15,T64,T45

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T15,T35,T31

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T12,T16
1	Covered	T11,T4,T18

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T12,T31,T38

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T12,T4
1	Covered	T2,T12,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T12,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T12,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T16,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T4,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T11,T12
Phase1St	198	Covered	T2,T11,T12
Phase2St	215	Covered	T2,T11,T12
Phase3St	233	Covered	T2,T11,T12
TerminalSt	249	Covered	T2,T11,T12
TimeoutSt	159	Covered	T15,T31,T37

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T2,T11,T12
IdleSt->TimeoutSt	159	Covered	T15,T31,T37
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T24,T48,T76
Phase0St->Phase1St	198	Covered	T2,T11,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T21,T26,T77
Phase1St->Phase2St	215	Covered	T2,T11,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T29,T51,T78
Phase2St->Phase3St	233	Covered	T2,T11,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T27,T30,T29
Phase3St->TerminalSt	249	Covered	T2,T11,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T12,T18
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T15,T31,T37
TimeoutSt->Phase0St	172	Covered	T15,T64,T42

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T31,T37
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T64,T42
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T15,T31,T37
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T31,T37,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T76,T79,T80
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T11,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T11,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T21,T26,T77
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T11,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T11,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T51,T78
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T11,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T11,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T30,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T11,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T11,T12,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T12,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T11,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	657025895	237	0	0
CheckAccumTrig0_A	657025895	829	0	0
CheckAccumTrig1_A	657025895	46	0	0
CheckClr_A	657025895	402	0	0
CheckEn_A	656891199	226675189	0	0
CheckPhase0_A	657025895	898	0	0
CheckPhase1_A	657025895	881	0	0
CheckPhase2_A	657025895	864	0	0
CheckPhase3_A	657025895	839	0	0
CheckTimeout0_A	657025895	1234	0	0
CheckTimeoutSt1_A	657025895	132352	0	0
CheckTimeoutSt2_A	657025895	1135	0	0
CheckTimeoutStTrig_A	657025895	50	0	0
ErrorStAllEscAsserted_A	657025895	1326	0	0
ErrorStIsTerminal_A	657025895	1086	0	0
EscStateOut_A	656890505	656823380	0	0
u_state_regs_A	657025895	656856599	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	237	0	0
T8	30710	66	0	0
T9	0	26	0	0
T10	0	57	0	0
T14	139596	0	0	0
T15	448331	0	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T31	892429	0	0	0
T33	0	19	0	0
T34	0	69	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	829	0	0
T2	24199	2	0	0
T3	10164	0	0	0
T4	306356	1	0	0
T5	15550	0	0	0
T6	611281	0	0	0
T7	241229	0	0	0
T11	63979	1	0	0
T12	33030	4	0	0
T15	0	3	0	0
T16	0	1	0	0
T17	726879	0	0	0
T18	308805	2	0	0
T21	0	9	0	0
T31	0	2	0	0
T35	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	46	0	0
T25	0	1	0	0
T29	0	1	0	0
T30	0	1	0	0
T42	106214	1	0	0
T43	714953	0	0	0
T44	132280	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	2389	0	0	0
T58	59047	0	0	0
T59	309356	0	0	0
T60	41429	0	0	0
T61	277760	0	0	0
T62	68222	0	0	0
T63	32565	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	402	0	0
T2	24199	1	0	0
T3	10164	0	0	0
T4	306356	0	0	0
T5	15550	0	0	0
T6	611281	0	0	0
T7	241229	0	0	0
T11	63979	0	0	0
T12	33030	4	0	0
T17	726879	0	0	0
T18	308805	1	0	0
T21	0	8	0	0
T31	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T42	0	1	0	0
T59	0	2	0	0
T63	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	656891199	226675189	0	0
T1	15552	3616	0	0
T2	24199	1725	0	0
T3	10164	2094	0	0
T4	306356	8732	0	0
T5	15550	2153	0	0
T6	611281	608210	0	0
T7	241229	241147	0	0
T11	63979	10973	0	0
T12	33030	3095	0	0
T17	726879	726782	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	898	0	0
T2	24199	2	0	0
T3	10164	0	0	0
T4	306356	1	0	0
T5	15550	0	0	0
T6	611281	0	0	0
T7	241229	0	0	0
T11	63979	1	0	0
T12	33030	4	0	0
T15	0	4	0	0
T16	0	1	0	0
T17	726879	0	0	0
T18	308805	2	0	0
T21	0	9	0	0
T31	0	2	0	0
T35	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	881	0	0
T2	24199	2	0	0
T3	10164	0	0	0
T4	306356	1	0	0
T5	15550	0	0	0
T6	611281	0	0	0
T7	241229	0	0	0
T11	63979	1	0	0
T12	33030	4	0	0
T15	0	4	0	0
T16	0	1	0	0
T17	726879	0	0	0
T18	308805	2	0	0
T21	0	8	0	0
T31	0	2	0	0
T35	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	864	0	0
T2	24199	2	0	0
T3	10164	0	0	0
T4	306356	1	0	0
T5	15550	0	0	0
T6	611281	0	0	0
T7	241229	0	0	0
T11	63979	1	0	0
T12	33030	4	0	0
T15	0	4	0	0
T16	0	1	0	0
T17	726879	0	0	0
T18	308805	2	0	0
T21	0	8	0	0
T31	0	2	0	0
T35	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	839	0	0
T2	24199	2	0	0
T3	10164	0	0	0
T4	306356	1	0	0
T5	15550	0	0	0
T6	611281	0	0	0
T7	241229	0	0	0
T11	63979	1	0	0
T12	33030	4	0	0
T15	0	4	0	0
T16	0	1	0	0
T17	726879	0	0	0
T18	308805	2	0	0
T21	0	8	0	0
T31	0	2	0	0
T35	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	1234	0	0
T15	448331	2	0	0
T19	112564	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T23	0	1	0	0
T31	892429	1	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	2	0	0
T41	0	6	0	0
T42	0	1	0	0
T54	279761	0	0	0
T55	4156	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	6	0	0
T64	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	132352	0	0
T15	448331	242	0	0
T19	112564	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T23	0	40	0	0
T31	892429	101	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	245	0	0
T41	0	835	0	0
T42	0	1	0	0
T54	279761	0	0	0
T55	4156	0	0	0
T57	0	52	0	0
T58	0	109	0	0
T59	0	878	0	0
T64	0	1447	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	1135	0	0
T19	112564	0	0	0
T20	160213	0	0	0
T22	15952	0	0	0
T23	0	1	0	0
T31	892429	1	0	0
T36	18706	0	0	0
T37	80586	2	0	0
T38	391927	0	0	0
T41	0	6	0	0
T54	279761	0	0	0
T55	4156	0	0	0
T56	124055	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	6	0	0
T63	0	2	0	0
T64	0	2	0	0
T65	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	50	0	0
T15	448331	1	0	0
T19	112564	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T27	0	3	0	0
T29	0	1	0	0
T30	0	2	0	0
T31	892429	0	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0
T45	0	2	0	0
T48	0	1	0	0
T54	279761	0	0	0
T55	4156	0	0	0
T64	0	1	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	1326	0	0
T8	30710	293	0	0
T9	0	176	0	0
T10	0	367	0	0
T14	139596	0	0	0
T15	448331	0	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T31	892429	0	0	0
T33	0	161	0	0
T34	0	329	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	1086	0	0
T8	30710	233	0	0
T9	0	146	0	0
T10	0	307	0	0
T14	139596	0	0	0
T15	448331	0	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T31	892429	0	0	0
T33	0	131	0	0
T34	0	269	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	656890505	656823380	0	0
T1	15552	15360	0	0
T2	24199	24100	0	0
T3	10164	10069	0	0
T4	306356	306187	0	0
T5	15550	15373	0	0
T6	611281	611195	0	0
T7	241229	241148	0	0
T11	63979	63896	0	0
T12	33030	32966	0	0
T17	726879	726783	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	656856599	0	0
T1	15552	15360	0	0
T2	24199	24100	0	0
T3	10164	10069	0	0
T4	306356	306187	0	0
T5	15550	15373	0	0
T6	611281	611195	0	0
T7	241229	241148	0	0
T11	63979	63896	0	0
T12	33030	32966	0	0
T17	726879	726783	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T6,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T6,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T6,T11

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T13,T15
1	0	1	Covered	T7,T17,T4
1	1	0	Covered	T15,T31,T22
1	1	1	Covered	T13,T15,T37

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T37
0	1	Covered	T13,T62,T25
1	0	Covered	T15,T23,T42

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T13,T15,T37
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T23,T42

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T37
1	0	Not Covered
1	1	Covered	T13,T62,T25

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T11,T18
1	Covered	T7,T17,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T11,T7
1	Covered	T18,T15,T22

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T7,T17
1	Covered	T6,T11,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T11,T7
1	Covered	T11,T54,T38

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T18,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T6,T11,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T6,T11,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T7,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T6,T11,T7
Phase1St	198	Covered	T6,T11,T7
Phase2St	215	Covered	T6,T11,T7
Phase3St	233	Covered	T6,T11,T7
TerminalSt	249	Covered	T6,T11,T7
TimeoutSt	159	Covered	T13,T15,T37

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T6,T11,T7
IdleSt->TimeoutSt	159	Covered	T13,T15,T37
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T29,T52,T81
Phase0St->Phase1St	198	Covered	T6,T11,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T13,T32,T30
Phase1St->Phase2St	215	Covered	T6,T11,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T27,T48,T82
Phase2St->Phase3St	233	Covered	T6,T11,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T27,T30,T82
Phase3St->TerminalSt	249	Covered	T6,T11,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T11,T15,T54
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T15,T37,T39
TimeoutSt->Phase0St	172	Covered	T13,T15,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T11
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T15,T37
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T15,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T13,T15,T37
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T15,T37,T39
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T52,T81,T83
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T6,T11,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T6,T11,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T13,T32,T30
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T6,T11,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T6,T11,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T48,T82
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T6,T11,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T6,T11,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T30,T82
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T6,T11,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T6,T11,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T11,T15,T54
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T11,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	657025895	239	0	0
CheckAccumTrig0_A	657025895	446	0	0
CheckAccumTrig1_A	657025895	31	0	0
CheckClr_A	657025895	194	0	0
CheckEn_A	656891199	301396051	0	0
CheckPhase0_A	657025895	528	0	0
CheckPhase1_A	657025895	517	0	0
CheckPhase2_A	657025895	511	0	0
CheckPhase3_A	657025895	499	0	0
CheckTimeout0_A	657025895	1119	0	0
CheckTimeoutSt1_A	657025895	109813	0	0
CheckTimeoutSt2_A	657025895	1032	0	0
CheckTimeoutStTrig_A	657025895	55	0	0
ErrorStAllEscAsserted_A	657025895	1251	0	0
ErrorStIsTerminal_A	657025895	1011	0	0
EscStateOut_A	656890505	656823380	0	0
u_state_regs_A	657025895	656856599	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	239	0	0
T8	30710	72	0	0
T9	0	30	0	0
T10	0	72	0	0
T14	139596	0	0	0
T15	448331	0	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T31	892429	0	0	0
T33	0	22	0	0
T34	0	43	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	446	0	0
T4	306356	1	0	0
T5	15550	0	0	0
T6	611281	1	0	0
T7	241229	1	0	0
T8	30710	0	0	0
T11	63979	2	0	0
T12	33030	0	0	0
T13	77693	0	0	0
T14	0	1	0	0
T15	0	8	0	0
T17	726879	1	0	0
T18	308805	1	0	0
T22	0	1	0	0
T37	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	31	0	0
T15	448331	2	0	0
T19	112564	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T23	0	1	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	892429	0	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	279761	0	0	0
T55	4156	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	194	0	0
T4	306356	0	0	0
T5	15550	0	0	0
T7	241229	0	0	0
T8	30710	0	0	0
T11	63979	1	0	0
T12	33030	0	0	0
T13	77693	1	0	0
T15	0	4	0	0
T16	137082	0	0	0
T17	726879	0	0	0
T18	308805	0	0	0
T25	0	3	0	0
T27	0	6	0	0
T30	0	5	0	0
T32	0	3	0	0
T42	0	5	0	0
T46	0	1	0	0
T54	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	656891199	301396051	0	0
T1	15552	3632	0	0
T2	24199	24099	0	0
T3	10164	10068	0	0
T4	306356	8881	0	0
T5	15550	15371	0	0
T6	611281	5119	0	0
T7	241229	3028	0	0
T11	63979	2002	0	0
T12	33030	32965	0	0
T17	726879	5697	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	528	0	0
T4	306356	1	0	0
T5	15550	0	0	0
T6	611281	1	0	0
T7	241229	1	0	0
T8	30710	0	0	0
T11	63979	2	0	0
T12	33030	0	0	0
T13	77693	2	0	0
T14	0	1	0	0
T15	0	10	0	0
T17	726879	1	0	0
T18	308805	1	0	0
T22	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	517	0	0
T4	306356	1	0	0
T5	15550	0	0	0
T6	611281	1	0	0
T7	241229	1	0	0
T8	30710	0	0	0
T11	63979	2	0	0
T12	33030	0	0	0
T13	77693	1	0	0
T14	0	1	0	0
T15	0	10	0	0
T17	726879	1	0	0
T18	308805	1	0	0
T22	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	511	0	0
T4	306356	1	0	0
T5	15550	0	0	0
T6	611281	1	0	0
T7	241229	1	0	0
T8	30710	0	0	0
T11	63979	2	0	0
T12	33030	0	0	0
T13	77693	1	0	0
T14	0	1	0	0
T15	0	10	0	0
T17	726879	1	0	0
T18	308805	1	0	0
T22	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	499	0	0
T4	306356	1	0	0
T5	15550	0	0	0
T6	611281	1	0	0
T7	241229	1	0	0
T8	30710	0	0	0
T11	63979	2	0	0
T12	33030	0	0	0
T13	77693	1	0	0
T14	0	1	0	0
T15	0	10	0	0
T17	726879	1	0	0
T18	308805	1	0	0
T22	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	1119	0	0
T8	30710	0	0	0
T13	77693	2	0	0
T14	139596	0	0	0
T15	448331	42	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T23	0	1	0	0
T31	892429	0	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	0	3	0	0
T39	0	74	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T62	0	1	0	0
T65	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	109813	0	0
T8	30710	0	0	0
T13	77693	112	0	0
T14	139596	0	0	0
T15	448331	9325	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T23	0	3	0	0
T25	0	1158	0	0
T31	892429	0	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	0	395	0	0
T39	0	2929	0	0
T42	0	10	0	0
T43	0	6	0	0
T62	0	72	0	0
T65	0	585	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	1032	0	0
T15	448331	40	0	0
T19	112564	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T25	0	12	0	0
T27	0	3	0	0
T31	892429	0	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	3	0	0
T39	0	74	0	0
T45	0	4	0	0
T46	0	2	0	0
T54	279761	0	0	0
T55	4156	0	0	0
T65	0	3	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	55	0	0
T8	30710	0	0	0
T13	77693	2	0	0
T14	139596	0	0	0
T15	448331	0	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T25	0	1	0	0
T27	0	2	0	0
T29	0	1	0	0
T31	892429	0	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T52	0	3	0	0
T62	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	1251	0	0
T8	30710	311	0	0
T9	0	150	0	0
T10	0	328	0	0
T14	139596	0	0	0
T15	448331	0	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T31	892429	0	0	0
T33	0	163	0	0
T34	0	299	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	1011	0	0
T8	30710	251	0	0
T9	0	120	0	0
T10	0	268	0	0
T14	139596	0	0	0
T15	448331	0	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T31	892429	0	0	0
T33	0	133	0	0
T34	0	239	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	656890505	656823380	0	0
T1	15552	15360	0	0
T2	24199	24100	0	0
T3	10164	10069	0	0
T4	306356	306187	0	0
T5	15550	15373	0	0
T6	611281	611195	0	0
T7	241229	241148	0	0
T11	63979	63896	0	0
T12	33030	32966	0	0
T17	726879	726783	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	656856599	0	0
T1	15552	15360	0	0
T2	24199	24100	0	0
T3	10164	10069	0	0
T4	306356	306187	0	0
T5	15550	15373	0	0
T6	611281	611195	0	0
T7	241229	241148	0	0
T11	63979	63896	0	0
T12	33030	32966	0	0
T17	726879	726783	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T13,T14,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T14,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T13,T14,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T13,T15
1	0	1	Covered	T4,T16,T14
1	1	0	Covered	T11,T13,T15
1	1	1	Covered	T13,T15,T22

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T22
0	1	Covered	T15,T22,T66
1	0	Covered	T22,T41,T30

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T13,T15,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T41,T30

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T22
1	0	Not Covered
1	1	Covered	T15,T22,T66

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T14,T15,T21
1	Covered	T13,T15,T39

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T15,T21,T38

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T15,T37,T84

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T13,T15,T21
1	Covered	T14,T15,T21

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T14,T15,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T13,T14,T15

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T13,T14,T15
Phase1St	198	Covered	T13,T14,T15
Phase2St	215	Covered	T13,T14,T15
Phase3St	233	Covered	T13,T14,T15
TerminalSt	249	Covered	T13,T14,T15
TimeoutSt	159	Covered	T13,T15,T22

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T13,T14,T15
IdleSt->TimeoutSt	159	Covered	T13,T15,T22
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T15,T25,T30
Phase0St->Phase1St	198	Covered	T13,T14,T15
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T85,T86,T87
Phase1St->Phase2St	215	Covered	T13,T14,T15
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T28,T71,T77
Phase2St->Phase3St	233	Covered	T13,T14,T15
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T15,T77,T50
Phase3St->TerminalSt	249	Covered	T13,T14,T15
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T15,T21,T22
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T13,T22,T37
TimeoutSt->Phase0St	172	Covered	T15,T22,T41

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T15,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T22,T41
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T13,T15,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T22,T37
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T30,T88
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T13,T14,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T13,T14,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T85,T86,T87
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T13,T14,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T13,T14,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T71,T77
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T13,T14,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T13,T14,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T15,T77,T50
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T13,T14,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T13,T14,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T15,T21,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T13,T14,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	657025895	246	0	0
CheckAccumTrig0_A	657025895	471	0	0
CheckAccumTrig1_A	657025895	15	0	0
CheckClr_A	657025895	199	0	0
CheckEn_A	656891199	288540315	0	0
CheckPhase0_A	657025895	531	0	0
CheckPhase1_A	657025895	527	0	0
CheckPhase2_A	657025895	513	0	0
CheckPhase3_A	657025895	500	0	0
CheckTimeout0_A	657025895	1446	0	0
CheckTimeoutSt1_A	657025895	139504	0	0
CheckTimeoutSt2_A	657025895	1375	0	0
CheckTimeoutStTrig_A	657025895	55	0	0
ErrorStAllEscAsserted_A	657025895	1346	0	0
ErrorStIsTerminal_A	657025895	1106	0	0
EscStateOut_A	656890505	656823380	0	0
u_state_regs_A	657025895	656856599	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	246	0	0
T8	30710	67	0	0
T9	0	31	0	0
T10	0	60	0	0
T14	139596	0	0	0
T15	448331	0	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T31	892429	0	0	0
T33	0	37	0	0
T34	0	51	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	471	0	0
T8	30710	0	0	0
T13	77693	1	0	0
T14	139596	1	0	0
T15	448331	3	0	0
T16	137082	0	0	0
T21	165733	2	0	0
T22	15952	0	0	0
T23	0	1	0	0
T31	892429	1	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	15	0	0
T19	112564	0	0	0
T20	160213	0	0	0
T22	15952	1	0	0
T28	0	1	0	0
T30	0	1	0	0
T36	18706	0	0	0
T37	80586	0	0	0
T38	391927	0	0	0
T39	433675	0	0	0
T41	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	279761	0	0	0
T55	4156	0	0	0
T56	124055	0	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	199	0	0
T15	448331	2	0	0
T19	112564	0	0	0
T21	165733	1	0	0
T22	15952	2	0	0
T25	0	1	0	0
T27	0	4	0	0
T30	0	3	0	0
T31	892429	0	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0
T45	0	1	0	0
T54	279761	0	0	0
T55	4156	0	0	0
T57	0	1	0	0
T61	0	1	0	0
T66	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	656891199	288540315	0	0
T1	15552	3657	0	0
T2	24199	22956	0	0
T3	10164	10068	0	0
T4	306356	302870	0	0
T5	15550	2179	0	0
T6	611281	611194	0	0
T7	241229	186106	0	0
T11	63979	63895	0	0
T12	33030	32965	0	0
T17	726879	726782	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	531	0	0
T8	30710	0	0	0
T13	77693	1	0	0
T14	139596	1	0	0
T15	448331	4	0	0
T16	137082	0	0	0
T21	165733	2	0	0
T22	15952	3	0	0
T31	892429	1	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	527	0	0
T8	30710	0	0	0
T13	77693	1	0	0
T14	139596	1	0	0
T15	448331	4	0	0
T16	137082	0	0	0
T21	165733	2	0	0
T22	15952	3	0	0
T31	892429	1	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	513	0	0
T8	30710	0	0	0
T13	77693	1	0	0
T14	139596	1	0	0
T15	448331	4	0	0
T16	137082	0	0	0
T21	165733	2	0	0
T22	15952	3	0	0
T31	892429	1	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	500	0	0
T8	30710	0	0	0
T13	77693	1	0	0
T14	139596	1	0	0
T15	448331	3	0	0
T16	137082	0	0	0
T21	165733	2	0	0
T22	15952	3	0	0
T31	892429	1	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	1446	0	0
T8	30710	0	0	0
T13	77693	4	0	0
T14	139596	0	0	0
T15	448331	2	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	5	0	0
T23	0	1	0	0
T25	0	11	0	0
T31	892429	0	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	0	2	0	0
T41	0	15	0	0
T45	0	7	0	0
T59	0	4	0	0
T66	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	139504	0	0
T8	30710	0	0	0
T13	77693	858	0	0
T14	139596	0	0	0
T15	448331	114	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	382	0	0
T23	0	45	0	0
T25	0	1005	0	0
T31	892429	0	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	0	258	0	0
T41	0	1725	0	0
T45	0	1122	0	0
T59	0	756	0	0
T66	0	985	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	1375	0	0
T8	30710	0	0	0
T13	77693	4	0	0
T14	139596	0	0	0
T15	448331	0	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	2	0	0
T23	0	1	0	0
T25	0	10	0	0
T27	0	47	0	0
T30	0	6	0	0
T31	892429	0	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	0	2	0	0
T41	0	14	0	0
T45	0	6	0	0
T59	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	55	0	0
T15	448331	2	0	0
T19	112564	0	0	0
T21	165733	0	0	0
T22	15952	2	0	0
T25	0	1	0	0
T27	0	1	0	0
T30	0	1	0	0
T31	892429	0	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T54	279761	0	0	0
T55	4156	0	0	0
T66	0	1	0	0
T71	0	1	0	0
T92	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	1346	0	0
T8	30710	343	0	0
T9	0	158	0	0
T10	0	347	0	0
T14	139596	0	0	0
T15	448331	0	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T31	892429	0	0	0
T33	0	178	0	0
T34	0	320	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	1106	0	0
T8	30710	283	0	0
T9	0	128	0	0
T10	0	287	0	0
T14	139596	0	0	0
T15	448331	0	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T31	892429	0	0	0
T33	0	148	0	0
T34	0	260	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	656890505	656823380	0	0
T1	15552	15360	0	0
T2	24199	24100	0	0
T3	10164	10069	0	0
T4	306356	306187	0	0
T5	15550	15373	0	0
T6	611281	611195	0	0
T7	241229	241148	0	0
T11	63979	63896	0	0
T12	33030	32966	0	0
T17	726879	726783	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	656856599	0	0
T1	15552	15360	0	0
T2	24199	24100	0	0
T3	10164	10069	0	0
T4	306356	306187	0	0
T5	15550	15373	0	0
T6	611281	611195	0	0
T7	241229	241148	0	0
T11	63979	63896	0	0
T12	33030	32966	0	0
T17	726879	726783	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T6,T11,T14
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T11,T14

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T11,T14

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T11,T15
1	0	1	Covered	T6,T4,T15
1	1	0	Covered	T11,T13,T15
1	1	1	Covered	T11,T15,T37

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T11,T15,T37
0	1	Covered	T64,T25,T27
1	0	Covered	T24,T85,T88

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T11,T15,T37
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T24,T85,T88

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T15,T37
1	0	Not Covered
1	1	Covered	T64,T25,T27

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T15,T54
1	Covered	T11,T14,T15

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T11,T14
1	Covered	T15,T64,T59

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T11,T14
1	Covered	T15,T54,T61

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T14,T15
1	Covered	T6,T15,T38

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T6,T11,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T6,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T15,T54

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T6,T11,T14
Phase1St	198	Covered	T6,T11,T14
Phase2St	215	Covered	T6,T11,T14
Phase3St	233	Covered	T6,T11,T14
TerminalSt	249	Covered	T6,T11,T14
TimeoutSt	159	Covered	T11,T15,T37

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T6,T11,T14
IdleSt->TimeoutSt	159	Covered	T11,T15,T37
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T32,T30,T48
Phase0St->Phase1St	198	Covered	T6,T11,T14
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T93,T94,T95
Phase1St->Phase2St	215	Covered	T6,T11,T14
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T96,T32,T97
Phase2St->Phase3St	233	Covered	T6,T11,T14
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T30,T98,T99
Phase3St->TerminalSt	249	Covered	T6,T11,T14
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T15,T54,T64
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T11,T15,T37
TimeoutSt->Phase0St	172	Covered	T64,T24,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T11,T14
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T15,T37
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T64,T24,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T11,T15,T37
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T11,T15,T37
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T30,T94
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T6,T11,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T6,T11,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T93,T94,T95
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T6,T11,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T6,T11,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T96,T32,T97
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T6,T11,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T6,T11,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T30,T98,T99
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T6,T11,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T6,T11,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T15,T54,T64
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T11,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	657025895	293	0	0
CheckAccumTrig0_A	657025895	509	0	0
CheckAccumTrig1_A	657025895	15	0	0
CheckClr_A	657025895	221	0	0
CheckEn_A	656891199	300519277	0	0
CheckPhase0_A	657025895	563	0	0
CheckPhase1_A	657025895	557	0	0
CheckPhase2_A	657025895	545	0	0
CheckPhase3_A	657025895	536	0	0
CheckTimeout0_A	657025895	1078	0	0
CheckTimeoutSt1_A	657025895	116632	0	0
CheckTimeoutSt2_A	657025895	1016	0	0
CheckTimeoutStTrig_A	657025895	45	0	0
ErrorStAllEscAsserted_A	657025895	1333	0	0
ErrorStIsTerminal_A	657025895	1093	0	0
EscStateOut_A	656890505	656823380	0	0
u_state_regs_A	657025895	656856599	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	293	0	0
T8	30710	90	0	0
T9	0	35	0	0
T10	0	72	0	0
T14	139596	0	0	0
T15	448331	0	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T31	892429	0	0	0
T33	0	29	0	0
T34	0	67	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	509	0	0
T4	306356	0	0	0
T5	15550	0	0	0
T6	611281	1	0	0
T7	241229	0	0	0
T8	30710	0	0	0
T11	63979	1	0	0
T12	33030	0	0	0
T13	77693	0	0	0
T14	0	1	0	0
T15	0	8	0	0
T17	726879	0	0	0
T18	308805	0	0	0
T38	0	1	0	0
T54	0	3	0	0
T55	0	1	0	0
T64	0	1	0	0
T84	0	1	0	0
T96	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	15	0	0
T24	285061	1	0	0
T25	198329	0	0	0
T26	63549	0	0	0
T45	326233	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T67	31767	0	0	0
T88	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	89851	0	0	0
T107	9639	0	0	0
T108	187937	0	0	0
T109	111452	0	0	0
T110	38898	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	221	0	0
T15	448331	5	0	0
T19	112564	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T24	0	5	0	0
T25	0	1	0	0
T31	892429	0	0	0
T32	0	2	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0
T42	0	1	0	0
T54	279761	2	0	0
T55	4156	0	0	0
T59	0	2	0	0
T62	0	1	0	0
T64	0	1	0	0
T96	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	656891199	300519277	0	0
T1	15552	3682	0	0
T2	24199	22956	0	0
T3	10164	10068	0	0
T4	306356	295377	0	0
T5	15550	2199	0	0
T6	611281	880	0	0
T7	241229	114497	0	0
T11	63979	18175	0	0
T12	33030	32965	0	0
T17	726879	726782	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	563	0	0
T4	306356	0	0	0
T5	15550	0	0	0
T6	611281	1	0	0
T7	241229	0	0	0
T8	30710	0	0	0
T11	63979	1	0	0
T12	33030	0	0	0
T13	77693	0	0	0
T14	0	1	0	0
T15	0	8	0	0
T17	726879	0	0	0
T18	308805	0	0	0
T38	0	1	0	0
T54	0	3	0	0
T55	0	1	0	0
T64	0	2	0	0
T84	0	1	0	0
T96	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	557	0	0
T4	306356	0	0	0
T5	15550	0	0	0
T6	611281	1	0	0
T7	241229	0	0	0
T8	30710	0	0	0
T11	63979	1	0	0
T12	33030	0	0	0
T13	77693	0	0	0
T14	0	1	0	0
T15	0	8	0	0
T17	726879	0	0	0
T18	308805	0	0	0
T38	0	1	0	0
T54	0	3	0	0
T55	0	1	0	0
T64	0	2	0	0
T84	0	1	0	0
T96	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	545	0	0
T4	306356	0	0	0
T5	15550	0	0	0
T6	611281	1	0	0
T7	241229	0	0	0
T8	30710	0	0	0
T11	63979	1	0	0
T12	33030	0	0	0
T13	77693	0	0	0
T14	0	1	0	0
T15	0	8	0	0
T17	726879	0	0	0
T18	308805	0	0	0
T38	0	1	0	0
T41	0	1	0	0
T54	0	3	0	0
T55	0	1	0	0
T64	0	2	0	0
T84	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	536	0	0
T4	306356	0	0	0
T5	15550	0	0	0
T6	611281	1	0	0
T7	241229	0	0	0
T8	30710	0	0	0
T11	63979	1	0	0
T12	33030	0	0	0
T13	77693	0	0	0
T14	0	1	0	0
T15	0	8	0	0
T17	726879	0	0	0
T18	308805	0	0	0
T38	0	1	0	0
T41	0	1	0	0
T54	0	3	0	0
T55	0	1	0	0
T64	0	2	0	0
T84	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	1078	0	0
T4	306356	0	0	0
T5	15550	0	0	0
T7	241229	0	0	0
T8	30710	0	0	0
T11	63979	2	0	0
T12	33030	0	0	0
T13	77693	0	0	0
T15	0	41	0	0
T16	137082	0	0	0
T17	726879	0	0	0
T18	308805	0	0	0
T24	0	3	0	0
T25	0	15	0	0
T27	0	3	0	0
T37	0	4	0	0
T41	0	1	0	0
T45	0	13	0	0
T59	0	9	0	0
T64	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	116632	0	0
T4	306356	0	0	0
T5	15550	0	0	0
T7	241229	0	0	0
T8	30710	0	0	0
T11	63979	78	0	0
T12	33030	0	0	0
T13	77693	0	0	0
T15	0	10654	0	0
T16	137082	0	0	0
T17	726879	0	0	0
T18	308805	0	0	0
T24	0	214	0	0
T25	0	1354	0	0
T27	0	1095	0	0
T37	0	561	0	0
T41	0	118	0	0
T45	0	1936	0	0
T59	0	1687	0	0
T64	0	299	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	1016	0	0
T4	306356	0	0	0
T5	15550	0	0	0
T7	241229	0	0	0
T8	30710	0	0	0
T11	63979	2	0	0
T12	33030	0	0	0
T13	77693	0	0	0
T15	0	41	0	0
T16	137082	0	0	0
T17	726879	0	0	0
T18	308805	0	0	0
T24	0	2	0	0
T25	0	14	0	0
T27	0	1	0	0
T37	0	4	0	0
T41	0	1	0	0
T45	0	13	0	0
T59	0	9	0	0
T64	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	45	0	0
T25	0	1	0	0
T27	0	2	0	0
T30	0	1	0	0
T41	305037	0	0	0
T42	106214	0	0	0
T43	714953	0	0	0
T52	0	1	0	0
T57	2389	0	0	0
T58	59047	0	0	0
T59	309356	0	0	0
T60	41429	0	0	0
T61	277760	0	0	0
T62	68222	0	0	0
T64	192695	1	0	0
T86	0	1	0	0
T99	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	1333	0	0
T8	30710	338	0	0
T9	0	165	0	0
T10	0	329	0	0
T14	139596	0	0	0
T15	448331	0	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T31	892429	0	0	0
T33	0	186	0	0
T34	0	315	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	1093	0	0
T8	30710	278	0	0
T9	0	135	0	0
T10	0	269	0	0
T14	139596	0	0	0
T15	448331	0	0	0
T16	137082	0	0	0
T21	165733	0	0	0
T22	15952	0	0	0
T31	892429	0	0	0
T33	0	156	0	0
T34	0	255	0	0
T35	33794	0	0	0
T36	18706	0	0	0
T37	80586	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	656890505	656823380	0	0
T1	15552	15360	0	0
T2	24199	24100	0	0
T3	10164	10069	0	0
T4	306356	306187	0	0
T5	15550	15373	0	0
T6	611281	611195	0	0
T7	241229	241148	0	0
T11	63979	63896	0	0
T12	33030	32966	0	0
T17	726879	726783	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657025895	656856599	0	0
T1	15552	15360	0	0
T2	24199	24100	0	0
T3	10164	10069	0	0
T4	306356	306187	0	0
T5	15550	15373	0	0
T6	611281	611195	0	0
T7	241229	241148	0	0
T11	63979	63896	0	0
T12	33030	32966	0	0
T17	726879	726783	0	0