Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65503231	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31961943

1

T1

137469

T2

138797

T3

2780

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14720264	1			T1	54392		T2	54531		T3	1440
values[0x0]	40151099	1			T1	190994		T2	192392		T3	3631
values[0x1]	42593811	1			T1	190638		T2	191552		T3	3625

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55696535	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41768639

1

T1

173771

T2

174880

T3

3540

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	306784	1			T1	1762		T2	1651		T3	42
valid_sources[0x01]	308656	1			T1	1588		T2	1741		T3	31
valid_sources[0x02]	318941	1			T1	1742		T2	1723		T3	46
valid_sources[0x03]	304971	1			T1	1723		T2	1711		T3	36
valid_sources[0x04]	733627	1			T1	1750		T2	1717		T3	44
valid_sources[0x05]	310902	1			T1	1710		T2	1706		T3	28
valid_sources[0x06]	326003	1			T1	1711		T2	1656		T3	34
valid_sources[0x07]	644631	1			T1	1854		T2	1708		T3	33
valid_sources[0x08]	308486	1			T1	1626		T2	1764		T3	49
valid_sources[0x09]	319492	1			T1	1660		T2	1672		T3	38
valid_sources[0x0a]	315023	1			T1	1728		T2	1743		T3	36
valid_sources[0x0b]	323047	1			T1	1725		T2	1773		T3	33
valid_sources[0x0c]	323319	1			T1	1629		T2	1714		T3	31
valid_sources[0x0d]	311886	1			T1	1738		T2	1727		T3	26
valid_sources[0x0e]	633243	1			T1	1681		T2	1709		T3	42
valid_sources[0x0f]	317660	1			T1	1679		T2	1612		T3	39
valid_sources[0x10]	605854	1			T1	1712		T2	1692		T3	32
valid_sources[0x11]	318370	1			T1	1753		T2	1728		T3	36
valid_sources[0x12]	307132	1			T1	1607		T2	1731		T3	36
valid_sources[0x13]	311381	1			T1	1585		T2	1773		T3	27
valid_sources[0x14]	322046	1			T1	1643		T2	1725		T3	34
valid_sources[0x15]	304055	1			T1	1674		T2	1649		T3	36
valid_sources[0x16]	310124	1			T1	1754		T2	1644		T3	25
valid_sources[0x17]	309430	1			T1	1665		T2	1772		T3	42
valid_sources[0x18]	318393	1			T1	1667		T2	1743		T3	42
valid_sources[0x19]	334590	1			T1	1720		T2	1694		T3	33
valid_sources[0x1a]	326660	1			T1	1615		T2	1786		T3	36
valid_sources[0x1b]	321274	1			T1	1793		T2	1716		T3	41
valid_sources[0x1c]	306783	1			T1	1633		T2	1721		T3	34
valid_sources[0x1d]	303187	1			T1	1820		T2	1782		T3	39
valid_sources[0x1e]	311409	1			T1	1662		T2	1678		T3	36
valid_sources[0x1f]	318218	1			T1	1761		T2	1675		T3	22
valid_sources[0x20]	310981	1			T1	1714		T2	1720		T3	33
valid_sources[0x21]	308765	1			T1	1745		T2	1731		T3	46
valid_sources[0x22]	599745	1			T1	1715		T2	1700		T3	40
valid_sources[0x23]	309086	1			T1	1781		T2	1768		T3	21
valid_sources[0x24]	305642	1			T1	1651		T2	1738		T3	34
valid_sources[0x25]	312353	1			T1	1783		T2	1805		T3	32
valid_sources[0x26]	306821	1			T1	1639		T2	1707		T3	32
valid_sources[0x27]	308414	1			T1	1686		T2	1734		T3	33
valid_sources[0x28]	715171	1			T1	1737		T2	1677		T3	44
valid_sources[0x29]	311386	1			T1	1706		T2	1725		T3	38
valid_sources[0x2a]	310667	1			T1	1783		T2	1672		T3	42
valid_sources[0x2b]	730887	1			T1	1744		T2	1656		T3	30
valid_sources[0x2c]	306151	1			T1	1729		T2	1822		T3	31
valid_sources[0x2d]	313722	1			T1	1661		T2	1789		T3	32
valid_sources[0x2e]	313176	1			T1	1639		T2	1695		T3	40
valid_sources[0x2f]	319345	1			T1	1760		T2	1712		T3	28
valid_sources[0x30]	690570	1			T1	1710		T2	1713		T3	35
valid_sources[0x31]	313438	1			T1	1726		T2	1688		T3	37
valid_sources[0x32]	1225464	1			T1	1700		T2	1747		T3	47
valid_sources[0x33]	316546	1			T1	1759		T2	1716		T3	18
valid_sources[0x34]	313974	1			T1	1619		T2	1779		T3	25
valid_sources[0x35]	311843	1			T1	1643		T2	1755		T3	41
valid_sources[0x36]	328042	1			T1	1701		T2	1712		T3	32
valid_sources[0x37]	306112	1			T1	1703		T2	1691		T3	28
valid_sources[0x38]	311355	1			T1	1711		T2	1679		T3	35
valid_sources[0x39]	312806	1			T1	1691		T2	1702		T3	41
valid_sources[0x3a]	761658	1			T1	1710		T2	1732		T3	44
valid_sources[0x3b]	314274	1			T1	1708		T2	1713		T3	25
valid_sources[0x3c]	311142	1			T1	1671		T2	1728		T3	38
valid_sources[0x3d]	319725	1			T1	1683		T2	1702		T3	46
valid_sources[0x3e]	308890	1			T1	1627		T2	1712		T3	21
valid_sources[0x3f]	795416	1			T1	1667		T2	1684		T3	31
valid_sources[0x40]	311345	1			T1	1793		T2	1764		T3	28
valid_sources[0x41]	643551	1			T1	1636		T2	1652		T3	38
valid_sources[0x42]	312001	1			T1	1624		T2	1689		T3	27
valid_sources[0x43]	791433	1			T1	1609		T2	1731		T3	34
valid_sources[0x44]	310882	1			T1	1668		T2	1642		T3	30
valid_sources[0x45]	744284	1			T1	1689		T2	1678		T3	28
valid_sources[0x46]	662360	1			T1	1687		T2	1748		T3	28
valid_sources[0x47]	311820	1			T1	1628		T2	1694		T3	39
valid_sources[0x48]	310889	1			T1	1656		T2	1693		T3	40
valid_sources[0x49]	322618	1			T1	1665		T2	1769		T3	36
valid_sources[0x4a]	1049893	1			T1	1820		T2	1654		T3	33
valid_sources[0x4b]	314876	1			T1	1729		T2	1678		T3	29
valid_sources[0x4c]	309071	1			T1	1671		T2	1707		T3	23
valid_sources[0x4d]	1030664	1			T1	1670		T2	1691		T3	28
valid_sources[0x4e]	312321	1			T1	1822		T2	1746		T3	40
valid_sources[0x4f]	305896	1			T1	1720		T2	1847		T3	21
valid_sources[0x50]	318966	1			T1	1692		T2	1753		T3	51
valid_sources[0x51]	341253	1			T1	1733		T2	1644		T3	28
valid_sources[0x52]	307928	1			T1	1718		T2	1674		T3	40
valid_sources[0x53]	306152	1			T1	1741		T2	1645		T3	36
valid_sources[0x54]	309031	1			T1	1691		T2	1704		T3	26
valid_sources[0x55]	322358	1			T1	1679		T2	1799		T3	36
valid_sources[0x56]	311619	1			T1	1686		T2	1774		T3	41
valid_sources[0x57]	309953	1			T1	1740		T2	1639		T3	31
valid_sources[0x58]	314053	1			T1	1718		T2	1675		T3	26
valid_sources[0x59]	306620	1			T1	1672		T2	1677		T3	35
valid_sources[0x5a]	304431	1			T1	1731		T2	1622		T3	30
valid_sources[0x5b]	305507	1			T1	1715		T2	1703		T3	28
valid_sources[0x5c]	316364	1			T1	1760		T2	1699		T3	46
valid_sources[0x5d]	312529	1			T1	1715		T2	1720		T3	27
valid_sources[0x5e]	312339	1			T1	1819		T2	1705		T3	39
valid_sources[0x5f]	311092	1			T1	1768		T2	1666		T3	34
valid_sources[0x60]	310693	1			T1	1614		T2	1699		T3	36
valid_sources[0x61]	319193	1			T1	1708		T2	1698		T3	40
valid_sources[0x62]	309808	1			T1	1643		T2	1751		T3	33
valid_sources[0x63]	309128	1			T1	1689		T2	1740		T3	41
valid_sources[0x64]	599706	1			T1	1664		T2	1755		T3	34
valid_sources[0x65]	317000	1			T1	1638		T2	1697		T3	28
valid_sources[0x66]	312920	1			T1	1727		T2	1707		T3	26
valid_sources[0x67]	316661	1			T1	1843		T2	1688		T3	39
valid_sources[0x68]	306787	1			T1	1571		T2	1716		T3	33
valid_sources[0x69]	738605	1			T1	1690		T2	1708		T3	33
valid_sources[0x6a]	311930	1			T1	1737		T2	1673		T3	34
valid_sources[0x6b]	316318	1			T1	1680		T2	1707		T3	33
valid_sources[0x6c]	306183	1			T1	1688		T2	1669		T3	33
valid_sources[0x6d]	308613	1			T1	1711		T2	1699		T3	38
valid_sources[0x6e]	320835	1			T1	1689		T2	1687		T3	32
valid_sources[0x6f]	307915	1			T1	1628		T2	1742		T3	32
valid_sources[0x70]	318727	1			T1	1751		T2	1753		T3	39
valid_sources[0x71]	320045	1			T1	1754		T2	1682		T3	36
valid_sources[0x72]	303690	1			T1	1712		T2	1754		T3	36
valid_sources[0x73]	305780	1			T1	1764		T2	1731		T3	37
valid_sources[0x74]	311713	1			T1	1801		T2	1657		T3	40
valid_sources[0x75]	306652	1			T1	1643		T2	1699		T3	32
valid_sources[0x76]	305175	1			T1	1698		T2	1726		T3	41
valid_sources[0x77]	308455	1			T1	1801		T2	1723		T3	21
valid_sources[0x78]	306697	1			T1	1705		T2	1712		T3	33
valid_sources[0x79]	306992	1			T1	1766		T2	1718		T3	28
valid_sources[0x7a]	304045	1			T1	1776		T2	1648		T3	27
valid_sources[0x7b]	314050	1			T1	1712		T2	1780		T3	30
valid_sources[0x7c]	317077	1			T1	1789		T2	1674		T3	36
valid_sources[0x7d]	312454	1			T1	1656		T2	1728		T3	43
valid_sources[0x7e]	312986	1			T1	1712		T2	1752		T3	26
valid_sources[0x7f]	581042	1			T1	1738		T2	1700		T3	42
valid_sources[0x80]	306441	1			T1	1654		T2	1757		T3	46

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7365455

1

T1

27001

T2

27261

T3

710

values[0x0]

all_enables

biggest_size

15480174

1

T1

70771

T2

71342

T3

1363

values[0x1]

all_enables

biggest_size

9116314

1

T1

39697

T2

40194

T3

707