Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T187,T188
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14404	0	0
DisabledNoTrigBkwd_A	2147483647	796930	0	0
DisabledNoTrigFwd_A	2147483647	1543999103	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14404	0	0
T12	0	445	0	0
T26	368122	0	0	0
T100	239263	0	0	0
T109	108745	0	0	0
T187	1608	785	0	0
T188	0	595	0	0
T189	2924	561	0	0
T190	0	671	0	0
T191	3727	844	0	0
T192	0	1525	0	0
T193	0	1130	0	0
T194	0	513	0	0
T195	0	345	0	0
T196	0	842	0	0
T197	0	1196	0	0
T198	0	262	0	0
T199	0	239	0	0
T200	0	923	0	0
T201	0	923	0	0
T202	0	567	0	0
T203	0	474	0	0
T204	0	355	0	0
T205	0	1209	0	0
T206	6470	0	0	0
T207	954946	0	0	0
T208	501994	0	0	0
T209	338468	0	0	0
T210	91717	0	0	0
T211	299265	0	0	0
T212	77791	0	0	0
T213	93634	0	0	0
T214	798894	0	0	0
T215	61805	0	0	0
T216	71998	0	0	0
T217	126193	0	0	0
T218	657156	0	0	0
T219	223818	0	0	0
T220	22127	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	796930	0	0
T1	302718	8416	0	0
T2	1541704	3240	0	0
T3	1822540	2	0	0
T4	24656	0	0	0
T5	0	6399	0	0
T6	0	24	0	0
T10	93504	16	0	0
T11	528232	404	0	0
T12	5348	20	0	0
T13	431032	0	0	0
T14	0	3845	0	0
T17	0	1818	0	0
T18	0	3346	0	0
T19	0	2559	0	0
T20	154268	887	0	0
T21	112196	0	0	0
T22	925728	115	0	0
T32	0	1	0	0
T44	0	12	0	0
T45	0	13	0	0
T46	0	84	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1543999103	0	0
T1	403624	204502	0	0
T2	1541704	788511	0	0
T3	1822540	1244803	0	0
T10	93504	80681	0	0
T11	528232	36556	0	0
T12	5348	2416	0	0
T13	431032	306490	0	0
T20	154268	74585	0	0
T21	112196	82172	0	0
T22	925728	467548	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T191,T192,T193
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T10

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	694191115	4896	0	0
DisabledNoTrigBkwd_A	694191115	218999	0	0
DisabledNoTrigFwd_A	694191115	346246194	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	4896	0	0
T26	368122	0	0	0
T109	108745	0	0	0
T191	3727	844	0	0
T192	0	1525	0	0
T193	0	1130	0	0
T201	0	923	0	0
T203	0	474	0	0
T214	798894	0	0	0
T215	61805	0	0	0
T216	71998	0	0	0
T217	126193	0	0	0
T218	657156	0	0	0
T219	223818	0	0	0
T220	22127	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	218999	0	0
T1	100906	9	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T5	0	459	0	0
T10	23376	16	0	0
T11	132058	118	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T17	0	18	0	0
T20	38567	3	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T32	0	1	0	0
T44	0	6	0	0
T45	0	13	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	346246194	0	0
T1	100906	100312	0	0
T2	385426	384816	0	0
T3	455635	408083	0	0
T10	23376	10757	0	0
T11	132058	13357	0	0
T12	1337	598	0	0
T13	107758	106064	0	0
T20	38567	29696	0	0
T21	28049	22360	0	0
T22	231432	217300	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T13
1	1	Covered	T2,T3,T13

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T189,T190,T194
1	1	Covered	T2,T3,T13

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T11

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	694191115	2907	0	0
DisabledNoTrigBkwd_A	694191115	169373	0	0
DisabledNoTrigFwd_A	694191115	405372064	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	2907	0	0
T100	239263	0	0	0
T189	2924	561	0	0
T190	0	671	0	0
T194	0	513	0	0
T199	0	239	0	0
T200	0	923	0	0
T206	6470	0	0	0
T207	954946	0	0	0
T208	501994	0	0	0
T209	338468	0	0	0
T210	91717	0	0	0
T211	299265	0	0	0
T212	77791	0	0	0
T213	93634	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	169373	0	0
T2	385426	1556	0	0
T3	455635	2	0	0
T4	24656	0	0	0
T5	0	3060	0	0
T6	0	6	0	0
T10	23376	0	0	0
T11	132058	66	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T14	0	2065	0	0
T18	0	1662	0	0
T19	0	1457	0	0
T20	38567	6	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T46	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	405372064	0	0
T1	100906	100900	0	0
T2	385426	8655	0	0
T3	455635	625	0	0
T10	23376	23308	0	0
T11	132058	5697	0	0
T12	1337	602	0	0
T13	107758	106053	0	0
T20	38567	5886	0	0
T21	28049	22361	0	0
T22	231432	227855	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T187,T188,T196
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T11

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	694191115	3051	0	0
DisabledNoTrigBkwd_A	694191115	195190	0	0
DisabledNoTrigFwd_A	694191115	414648658	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	3051	0	0
T71	40190	0	0	0
T72	150119	0	0	0
T76	13113	0	0	0
T187	1608	785	0	0
T188	0	595	0	0
T196	0	842	0	0
T198	0	262	0	0
T202	0	567	0	0
T221	349781	0	0	0
T222	9045	0	0	0
T223	197931	0	0	0
T224	48576	0	0	0
T225	115083	0	0	0
T226	125586	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	195190	0	0
T1	100906	3017	0	0
T2	385426	4	0	0
T3	455635	0	0	0
T5	0	117	0	0
T10	23376	0	0	0
T11	132058	142	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T14	0	1780	0	0
T17	0	1797	0	0
T18	0	1684	0	0
T19	0	1102	0	0
T20	38567	878	0	0
T21	28049	0	0	0
T22	231432	69	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	414648658	0	0
T1	100906	1643	0	0
T2	385426	383573	0	0
T3	455635	380514	0	0
T10	23376	23308	0	0
T11	132058	4795	0	0
T12	1337	606	0	0
T13	107758	2316	0	0
T20	38567	29502	0	0
T21	28049	9471	0	0
T22	231432	19785	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T195,T197
1	1	Covered	T1,T2,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	694191115	3550	0	0
DisabledNoTrigBkwd_A	694191115	213368	0	0
DisabledNoTrigFwd_A	694191115	377732187	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	3550	0	0
T4	24656	0	0	0
T5	564699	0	0	0
T10	23376	0	0	0
T11	132058	0	0	0
T12	1337	445	0	0
T13	107758	0	0	0
T20	38567	0	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T44	35273	0	0	0
T195	0	345	0	0
T197	0	1196	0	0
T204	0	355	0	0
T205	0	1209	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	213368	0	0
T1	100906	5390	0	0
T2	385426	1679	0	0
T3	455635	0	0	0
T5	0	2763	0	0
T6	0	18	0	0
T10	23376	0	0	0
T11	132058	78	0	0
T12	1337	20	0	0
T13	107758	0	0	0
T17	0	3	0	0
T20	38567	0	0	0
T21	28049	0	0	0
T22	231432	46	0	0
T44	0	6	0	0
T46	0	81	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	377732187	0	0
T1	100906	1647	0	0
T2	385426	11467	0	0
T3	455635	455581	0	0
T10	23376	23308	0	0
T11	132058	12707	0	0
T12	1337	610	0	0
T13	107758	92057	0	0
T20	38567	9501	0	0
T21	28049	27980	0	0
T22	231432	2608	0	0