Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T20,T21
1	0	1	Covered	T2,T3,T12
1	1	0	Covered	T10,T20,T21
1	1	1	Covered	T10,T20,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T20,T21
0	1	Covered	T20,T5,T16
1	0	Covered	T10,T23,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T20,T21
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T23,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T20,T21
1	0	Covered	T25,T26,T27
1	1	Covered	T20,T5,T16

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T11

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T2,T3,T11

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T10,T20,T21

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T10,T20,T21
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T14,T6,T16
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T18,T24,T28
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T10,T17,T18
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T29,T30,T31
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T2,T20,T5
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T20,T21,T5
TimeoutSt->Phase0St	172	Covered	T10,T20,T5

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T20,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T10,T20,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T20,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T14,T6,T16
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T18,T24,T28
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T17,T18
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T31
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T20,T32
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	847	0	0
CheckAccumTrig0_A	2147483647	2322	0	0
CheckAccumTrig1_A	2147483647	110	0	0
CheckClr_A	2147483647	1073	0	0
CheckEn_A	2147483647	1168670923	0	0
CheckPhase0_A	2147483647	2672	0	0
CheckPhase1_A	2147483647	2620	0	0
CheckPhase2_A	2147483647	2581	0	0
CheckPhase3_A	2147483647	2527	0	0
CheckTimeout0_A	2147483647	4782	0	0
CheckTimeoutSt1_A	2147483647	550895	0	0
CheckTimeoutSt2_A	2147483647	4389	0	0
CheckTimeoutStTrig_A	2147483647	279	0	0
ErrorStAllEscAsserted_A	2147483647	5144	0	0
ErrorStIsTerminal_A	2147483647	4184	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	847	0	0
T7	139676	237	0	0
T8	0	174	0	0
T9	0	117	0	0
T33	0	238	0	0
T34	0	81	0	0
T35	113840	0	0	0
T36	57844	0	0	0
T37	82548	0	0	0
T38	494244	0	0	0
T39	86540	0	0	0
T40	2401560	0	0	0
T41	416204	0	0	0
T42	34308	0	0	0
T43	628808	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2322	0	0
T1	302718	3	0	0
T2	1541704	5	0	0
T3	1822540	1	0	0
T4	24656	0	0	0
T5	0	16	0	0
T6	0	2	0	0
T10	93504	1	0	0
T11	528232	4	0	0
T12	5348	1	0	0
T13	431032	0	0	0
T14	0	7	0	0
T16	0	4	0	0
T17	0	5	0	0
T18	0	4	0	0
T19	0	4	0	0
T20	154268	2	0	0
T21	112196	0	0	0
T22	925728	2	0	0
T32	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	110	0	0
T4	24656	0	0	0
T5	564699	0	0	0
T10	23376	1	0	0
T11	132058	0	0	0
T13	107758	0	0	0
T15	358905	0	0	0
T20	38567	0	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T23	0	1	0	0
T24	586029	3	0	0
T26	0	2	0	0
T27	0	1	0	0
T29	0	3	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T47	282170	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	604054	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	3	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	26385	0	0	0
T63	256792	0	0	0
T64	546664	0	0	0
T65	19162	0	0	0
T66	102395	0	0	0
T67	240728	0	0	0
T68	641028	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1073	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T4	98624	0	0	0
T5	1694097	0	0	0
T6	0	4	0	0
T10	46752	1	0	0
T11	264116	0	0	0
T12	1337	0	0	0
T13	215516	0	0	0
T14	0	5	0	0
T16	0	11	0	0
T17	290204	2	0	0
T18	0	2	0	0
T19	0	2	0	0
T20	154268	3	0	0
T21	112196	0	0	0
T22	925728	0	0	0
T23	0	7	0	0
T24	0	22	0	0
T28	0	1	0	0
T32	67476	1	0	0
T44	105819	0	0	0
T45	50302	0	0	0
T46	0	1	0	0
T47	0	2	0	0
T64	0	1	0	0
T65	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	183724	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1168670923	0	0
T1	403624	110020	0	0
T2	1541704	27335	0	0
T3	1822540	1244800	0	0
T10	93504	78667	0	0
T11	528232	25824	0	0
T12	5348	2416	0	0
T13	431032	306489	0	0
T20	154268	71549	0	0
T21	112196	82169	0	0
T22	925728	467546	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2672	0	0
T1	302718	3	0	0
T2	1541704	5	0	0
T3	1822540	1	0	0
T4	24656	0	0	0
T5	0	19	0	0
T6	0	2	0	0
T10	93504	2	0	0
T11	528232	4	0	0
T12	5348	1	0	0
T13	431032	0	0	0
T14	0	5	0	0
T17	0	5	0	0
T18	0	4	0	0
T19	0	4	0	0
T20	154268	6	0	0
T21	112196	0	0	0
T22	925728	2	0	0
T32	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2620	0	0
T1	302718	3	0	0
T2	1541704	5	0	0
T3	1822540	1	0	0
T4	24656	0	0	0
T5	0	19	0	0
T6	0	2	0	0
T10	93504	2	0	0
T11	528232	4	0	0
T12	5348	1	0	0
T13	431032	0	0	0
T14	0	5	0	0
T17	0	5	0	0
T18	0	3	0	0
T19	0	4	0	0
T20	154268	6	0	0
T21	112196	0	0	0
T22	925728	2	0	0
T32	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2581	0	0
T1	302718	3	0	0
T2	1541704	5	0	0
T3	1822540	1	0	0
T4	24656	0	0	0
T5	0	19	0	0
T6	0	2	0	0
T10	93504	1	0	0
T11	528232	4	0	0
T12	5348	1	0	0
T13	431032	0	0	0
T14	0	5	0	0
T17	0	3	0	0
T18	0	2	0	0
T19	0	4	0	0
T20	154268	6	0	0
T21	112196	0	0	0
T22	925728	2	0	0
T32	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2527	0	0
T1	302718	3	0	0
T2	1541704	5	0	0
T3	1822540	1	0	0
T4	24656	0	0	0
T5	0	19	0	0
T6	0	2	0	0
T10	93504	1	0	0
T11	528232	4	0	0
T12	5348	1	0	0
T13	431032	0	0	0
T14	0	5	0	0
T17	0	3	0	0
T18	0	2	0	0
T19	0	4	0	0
T20	154268	6	0	0
T21	112196	0	0	0
T22	925728	2	0	0
T32	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4782	0	0
T4	98624	0	0	0
T5	2258796	10	0	0
T6	0	3	0	0
T10	23376	1	0	0
T11	132058	0	0	0
T13	107758	0	0	0
T16	0	40	0	0
T17	435306	3	0	0
T20	115701	5	0	0
T21	112196	4	0	0
T22	925728	0	0	0
T23	0	65	0	0
T24	0	144	0	0
T32	89968	0	0	0
T44	141092	0	0	0
T45	75453	0	0	0
T46	0	175	0	0
T63	0	5	0	0
T65	0	1	0	0
T70	0	1	0	0
T73	275586	7	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	71274	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	550895	0	0
T4	98624	0	0	0
T5	2258796	954	0	0
T6	0	145	0	0
T10	23376	1	0	0
T11	132058	0	0	0
T13	107758	0	0	0
T16	0	10904	0	0
T17	435306	86	0	0
T20	115701	1976	0	0
T21	112196	608	0	0
T22	925728	0	0	0
T23	0	9877	0	0
T24	0	13878	0	0
T32	89968	0	0	0
T44	141092	0	0	0
T45	75453	0	0	0
T46	0	20554	0	0
T63	0	1293	0	0
T65	0	110	0	0
T70	0	106	0	0
T73	275586	1331	0	0
T74	0	202	0	0
T75	0	146	0	0
T76	0	539	0	0
T77	71274	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4389	0	0
T4	49312	0	0	0
T5	2258796	7	0	0
T6	0	3	0	0
T14	387982	0	0	0
T16	0	28	0	0
T17	580408	3	0	0
T20	38567	1	0	0
T21	56098	4	0	0
T22	462864	0	0	0
T23	0	59	0	0
T24	0	135	0	0
T32	89968	0	0	0
T44	141092	0	0	0
T45	100604	0	0	0
T46	0	173	0	0
T50	0	1	0	0
T51	0	1	0	0
T63	0	5	0	0
T65	0	2	0	0
T73	367448	7	0	0
T74	0	2	0	0
T75	0	2	0	0
T77	213822	0	0	0
T78	0	2	0	0
T79	82392	0	0	0
T80	253764	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	279	0	0
T4	24656	0	0	0
T5	1129398	2	0	0
T15	358905	0	0	0
T16	755022	10	0	0
T17	290204	0	0	0
T20	38567	2	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T23	122752	2	0	0
T24	586029	3	0	0
T25	0	1	0	0
T26	0	3	0	0
T32	44984	0	0	0
T44	70546	0	0	0
T45	50302	0	0	0
T49	0	1	0	0
T54	0	3	0	0
T56	0	2	0	0
T62	26385	0	0	0
T63	256792	0	0	0
T64	546664	0	0	0
T65	19162	1	0	0
T66	102395	0	0	0
T70	37515	1	0	0
T73	183724	0	0	0
T76	0	2	0	0
T77	71274	0	0	0
T78	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	5	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5144	0	0
T7	139676	1283	0	0
T8	0	1298	0	0
T9	0	600	0	0
T33	0	1289	0	0
T34	0	674	0	0
T35	113840	0	0	0
T36	57844	0	0	0
T37	82548	0	0	0
T38	494244	0	0	0
T39	86540	0	0	0
T40	2401560	0	0	0
T41	416204	0	0	0
T42	34308	0	0	0
T43	628808	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4184	0	0
T7	139676	1043	0	0
T8	0	1058	0	0
T9	0	480	0	0
T33	0	1049	0	0
T34	0	554	0	0
T35	113840	0	0	0
T36	57844	0	0	0
T37	82548	0	0	0
T38	494244	0	0	0
T39	86540	0	0	0
T40	2401560	0	0	0
T41	416204	0	0	0
T42	34308	0	0	0
T43	628808	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	403624	403600	0	0
T2	1541704	1541672	0	0
T3	1822540	1822324	0	0
T10	93504	93232	0	0
T11	528232	528008	0	0
T12	5348	5048	0	0
T13	431032	430820	0	0
T20	154268	153992	0	0
T21	112196	111920	0	0
T22	925728	925352	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	403624	403600	0	0
T2	1541704	1541672	0	0
T3	1822540	1822324	0	0
T10	93504	93232	0	0
T11	528232	528008	0	0
T12	5348	5048	0	0
T13	431032	430820	0	0
T20	154268	153992	0	0
T21	112196	111920	0	0
T22	925728	925352	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T20,T5,T44
1	0	1	Covered	T12,T11,T22
1	1	0	Covered	T20,T21,T5
1	1	1	Covered	T20,T5,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T5,T17
0	1	Covered	T20,T46,T16
1	0	Covered	T5,T23,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T20,T5,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T23,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T5,T17
1	0	Not Covered
1	1	Covered	T20,T46,T16

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T12,T20,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T12,T20
1	Covered	T1,T11,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T20,T6,T46

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T12,T11
1	Covered	T2,T22,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T12,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T12,T11

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T12
Phase1St	198	Covered	T1,T2,T12
Phase2St	215	Covered	T1,T2,T12
Phase3St	233	Covered	T1,T2,T12
TerminalSt	249	Covered	T1,T2,T12
TimeoutSt	159	Covered	T20,T5,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T12
IdleSt->TimeoutSt	159	Covered	T20,T5,T17
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T84,T88,T89
Phase0St->Phase1St	198	Covered	T1,T2,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T23,T90,T91
Phase1St->Phase2St	215	Covered	T1,T2,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T17,T26,T92
Phase2St->Phase3St	233	Covered	T1,T2,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T93,T94,T95
Phase3St->TerminalSt	249	Covered	T1,T2,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T20,T5,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T5,T17,T73
TimeoutSt->Phase0St	172	Covered	T20,T5,T46

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T5,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T5,T46
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T20,T5,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T17,T73
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T88,T89,T96
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T23,T90,T91
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T17,T92,T97
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T93,T94,T95
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T46,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	694191115	204	0	0
CheckAccumTrig0_A	694191115	499	0	0
CheckAccumTrig1_A	694191115	32	0	0
CheckClr_A	694191115	241	0	0
CheckEn_A	694058875	305301950	0	0
CheckPhase0_A	694191115	597	0	0
CheckPhase1_A	694191115	584	0	0
CheckPhase2_A	694191115	577	0	0
CheckPhase3_A	694191115	566	0	0
CheckTimeout0_A	694191115	1013	0	0
CheckTimeoutSt1_A	694191115	128655	0	0
CheckTimeoutSt2_A	694191115	909	0	0
CheckTimeoutStTrig_A	694191115	72	0	0
ErrorStAllEscAsserted_A	694191115	1234	0	0
ErrorStIsTerminal_A	694191115	994	0	0
EscStateOut_A	694057524	693988317	0	0
u_state_regs_A	694191115	694019659	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	204	0	0
T7	34919	57	0	0
T8	0	52	0	0
T9	0	23	0	0
T33	0	46	0	0
T34	0	26	0	0
T35	28460	0	0	0
T36	14461	0	0	0
T37	20637	0	0	0
T38	123561	0	0	0
T39	21635	0	0	0
T40	600390	0	0	0
T41	104051	0	0	0
T42	8577	0	0	0
T43	157202	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	499	0	0
T1	100906	1	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T5	0	5	0	0
T6	0	1	0	0
T10	23376	0	0	0
T11	132058	1	0	0
T12	1337	1	0	0
T13	107758	0	0	0
T17	0	1	0	0
T20	38567	0	0	0
T21	28049	0	0	0
T22	231432	1	0	0
T44	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	32	0	0
T5	564699	1	0	0
T14	193991	0	0	0
T17	145102	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T30	0	1	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T45	25151	0	0	0
T51	0	1	0	0
T59	0	2	0	0
T73	91862	0	0	0
T76	0	1	0	0
T77	71274	0	0	0
T79	41196	0	0	0
T80	126882	0	0	0
T90	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	241	0	0
T4	24656	0	0	0
T5	564699	0	0	0
T16	0	1	0	0
T17	145102	1	0	0
T20	38567	1	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T23	0	7	0	0
T24	0	3	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T45	25151	0	0	0
T46	0	1	0	0
T70	0	1	0	0
T73	91862	0	0	0
T76	0	1	0	0
T78	0	3	0	0
T98	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694058875	305301950	0	0
T1	100906	1647	0	0
T2	385426	2124	0	0
T3	455635	455580	0	0
T10	23376	23307	0	0
T11	132058	12707	0	0
T12	1337	610	0	0
T13	107758	92057	0	0
T20	38567	7979	0	0
T21	28049	27979	0	0
T22	231432	2608	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	597	0	0
T1	100906	1	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T5	0	6	0	0
T6	0	1	0	0
T10	23376	0	0	0
T11	132058	1	0	0
T12	1337	1	0	0
T13	107758	0	0	0
T17	0	1	0	0
T20	38567	2	0	0
T21	28049	0	0	0
T22	231432	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	584	0	0
T1	100906	1	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T5	0	6	0	0
T6	0	1	0	0
T10	23376	0	0	0
T11	132058	1	0	0
T12	1337	1	0	0
T13	107758	0	0	0
T17	0	1	0	0
T20	38567	2	0	0
T21	28049	0	0	0
T22	231432	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	577	0	0
T1	100906	1	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T5	0	6	0	0
T6	0	1	0	0
T10	23376	0	0	0
T11	132058	1	0	0
T12	1337	1	0	0
T13	107758	0	0	0
T20	38567	2	0	0
T21	28049	0	0	0
T22	231432	1	0	0
T44	0	1	0	0
T46	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	566	0	0
T1	100906	1	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T5	0	6	0	0
T6	0	1	0	0
T10	23376	0	0	0
T11	132058	1	0	0
T12	1337	1	0	0
T13	107758	0	0	0
T20	38567	2	0	0
T21	28049	0	0	0
T22	231432	1	0	0
T44	0	1	0	0
T46	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	1013	0	0
T4	24656	0	0	0
T5	564699	4	0	0
T6	0	1	0	0
T16	0	5	0	0
T17	145102	1	0	0
T20	38567	2	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T23	0	10	0	0
T24	0	8	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T45	25151	0	0	0
T46	0	170	0	0
T63	0	1	0	0
T73	91862	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	128655	0	0
T4	24656	0	0	0
T5	564699	368	0	0
T6	0	44	0	0
T16	0	799	0	0
T17	145102	32	0	0
T20	38567	543	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T23	0	897	0	0
T24	0	415	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T45	25151	0	0	0
T46	0	19874	0	0
T63	0	156	0	0
T73	91862	173	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	909	0	0
T5	564699	3	0	0
T6	0	1	0	0
T14	193991	0	0	0
T16	0	3	0	0
T17	145102	1	0	0
T23	0	7	0	0
T24	0	5	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T45	25151	0	0	0
T46	0	168	0	0
T63	0	1	0	0
T65	0	1	0	0
T73	91862	1	0	0
T77	71274	0	0	0
T79	41196	0	0	0
T80	126882	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	72	0	0
T4	24656	0	0	0
T5	564699	0	0	0
T16	0	2	0	0
T17	145102	0	0	0
T20	38567	2	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T23	0	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T45	25151	0	0	0
T46	0	2	0	0
T54	0	1	0	0
T73	91862	0	0	0
T78	0	1	0	0
T82	0	2	0	0
T84	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	1234	0	0
T7	34919	326	0	0
T8	0	322	0	0
T9	0	132	0	0
T33	0	286	0	0
T34	0	168	0	0
T35	28460	0	0	0
T36	14461	0	0	0
T37	20637	0	0	0
T38	123561	0	0	0
T39	21635	0	0	0
T40	600390	0	0	0
T41	104051	0	0	0
T42	8577	0	0	0
T43	157202	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	994	0	0
T7	34919	266	0	0
T8	0	262	0	0
T9	0	102	0	0
T33	0	226	0	0
T34	0	138	0	0
T35	28460	0	0	0
T36	14461	0	0	0
T37	20637	0	0	0
T38	123561	0	0	0
T39	21635	0	0	0
T40	600390	0	0	0
T41	104051	0	0	0
T42	8577	0	0	0
T43	157202	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694057524	693988317	0	0
T1	100906	100900	0	0
T2	385426	385418	0	0
T3	455635	455581	0	0
T10	23376	23308	0	0
T11	132058	132002	0	0
T12	1337	1262	0	0
T13	107758	107705	0	0
T20	38567	38498	0	0
T21	28049	27980	0	0
T22	231432	231338	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	694019659	0	0
T1	100906	100900	0	0
T2	385426	385418	0	0
T3	455635	455581	0	0
T10	23376	23308	0	0
T11	132058	132002	0	0
T12	1337	1262	0	0
T13	107758	107705	0	0
T20	38567	38498	0	0
T21	28049	27980	0	0
T22	231432	231338	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T10

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T10

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T20,T21
1	0	1	Covered	T3,T13,T11
1	1	0	Covered	T10,T20,T21
1	1	1	Covered	T10,T20,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T20,T5
0	1	Covered	T16,T23,T24
1	0	Covered	T10,T23,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T10,T20,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T10,T23,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T20,T5
1	0	Covered	T25,T26
1	1	Covered	T16,T23,T24

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T10,T20,T44

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T5,T17,T45

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T10,T20
1	Covered	T1,T10,T11

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T10,T11
1	Covered	T2,T5,T80

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T11,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T10,T20,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T10
Phase1St	198	Covered	T1,T2,T10
Phase2St	215	Covered	T1,T2,T10
Phase3St	233	Covered	T1,T2,T10
TerminalSt	249	Covered	T1,T2,T10
TimeoutSt	159	Covered	T10,T20,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T10
IdleSt->TimeoutSt	159	Covered	T10,T20,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T16,T23
Phase0St->Phase1St	198	Covered	T1,T2,T10
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T24,T100,T101
Phase1St->Phase2St	215	Covered	T1,T2,T10
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T10,T24,T102
Phase2St->Phase3St	233	Covered	T1,T2,T10
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T29,T25,T56
Phase3St->TerminalSt	249	Covered	T1,T2,T10
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T20,T5,T32
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T20,T5,T6
TimeoutSt->Phase0St	172	Covered	T10,T16,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T20,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T10,T16,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T20,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T20,T5,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T16,T23
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T10
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T10
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T24,T100,T101
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T10
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T10
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T24,T102
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T10
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T25,T56
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T32,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T10
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	694191115	220	0	0
CheckAccumTrig0_A	694191115	849	0	0
CheckAccumTrig1_A	694191115	36	0	0
CheckClr_A	694191115	408	0	0
CheckEn_A	694058875	224249516	0	0
CheckPhase0_A	694191115	945	0	0
CheckPhase1_A	694191115	922	0	0
CheckPhase2_A	694191115	909	0	0
CheckPhase3_A	694191115	891	0	0
CheckTimeout0_A	694191115	1182	0	0
CheckTimeoutSt1_A	694191115	112548	0	0
CheckTimeoutSt2_A	694191115	1069	0	0
CheckTimeoutStTrig_A	694191115	74	0	0
ErrorStAllEscAsserted_A	694191115	1341	0	0
ErrorStIsTerminal_A	694191115	1101	0	0
EscStateOut_A	694057524	693988317	0	0
u_state_regs_A	694191115	694019659	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	220	0	0
T7	34919	67	0	0
T8	0	38	0	0
T9	0	39	0	0
T33	0	56	0	0
T34	0	20	0	0
T35	28460	0	0	0
T36	14461	0	0	0
T37	20637	0	0	0
T38	123561	0	0	0
T39	21635	0	0	0
T40	600390	0	0	0
T41	104051	0	0	0
T42	8577	0	0	0
T43	157202	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	849	0	0
T1	100906	1	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T5	0	6	0	0
T10	23376	1	0	0
T11	132058	1	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T17	0	2	0	0
T20	38567	1	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T32	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	36	0	0
T4	24656	0	0	0
T5	564699	0	0	0
T10	23376	1	0	0
T11	132058	0	0	0
T13	107758	0	0	0
T20	38567	0	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T23	0	1	0	0
T24	0	2	0	0
T27	0	1	0	0
T29	0	3	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T58	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	408	0	0
T4	24656	0	0	0
T5	564699	0	0	0
T6	0	4	0	0
T10	23376	1	0	0
T11	132058	0	0	0
T13	107758	0	0	0
T16	0	4	0	0
T17	0	1	0	0
T20	38567	1	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T23	0	5	0	0
T24	0	12	0	0
T32	22492	1	0	0
T44	35273	0	0	0
T47	0	2	0	0
T64	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694058875	224249516	0	0
T1	100906	5830	0	0
T2	385426	11123	0	0
T3	455635	408082	0	0
T10	23376	8746	0	0
T11	132058	2625	0	0
T12	1337	598	0	0
T13	107758	106063	0	0
T20	38567	29695	0	0
T21	28049	22359	0	0
T22	231432	217299	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	945	0	0
T1	100906	1	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T5	0	6	0	0
T10	23376	2	0	0
T11	132058	1	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T17	0	2	0	0
T20	38567	1	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T32	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	922	0	0
T1	100906	1	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T5	0	6	0	0
T10	23376	2	0	0
T11	132058	1	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T17	0	2	0	0
T20	38567	1	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T32	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	909	0	0
T1	100906	1	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T5	0	6	0	0
T10	23376	1	0	0
T11	132058	1	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T17	0	2	0	0
T20	38567	1	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T32	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	891	0	0
T1	100906	1	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T5	0	6	0	0
T10	23376	1	0	0
T11	132058	1	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T17	0	2	0	0
T20	38567	1	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T32	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	1182	0	0
T4	24656	0	0	0
T5	564699	3	0	0
T6	0	1	0	0
T10	23376	1	0	0
T11	132058	0	0	0
T13	107758	0	0	0
T16	0	8	0	0
T20	38567	1	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T23	0	21	0	0
T24	0	73	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T46	0	2	0	0
T63	0	1	0	0
T74	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	112548	0	0
T4	24656	0	0	0
T5	564699	210	0	0
T6	0	57	0	0
T10	23376	1	0	0
T11	132058	0	0	0
T13	107758	0	0	0
T16	0	1788	0	0
T20	38567	73	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T23	0	2810	0	0
T24	0	6932	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T46	0	309	0	0
T63	0	419	0	0
T74	0	202	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	1069	0	0
T4	24656	0	0	0
T5	564699	3	0	0
T6	0	1	0	0
T16	0	5	0	0
T17	145102	0	0	0
T20	38567	1	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T23	0	18	0	0
T24	0	69	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T45	25151	0	0	0
T46	0	2	0	0
T63	0	1	0	0
T65	0	1	0	0
T73	91862	0	0	0
T74	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	74	0	0
T15	358905	0	0	0
T16	755022	3	0	0
T23	122752	2	0	0
T24	586029	2	0	0
T49	0	1	0	0
T54	0	1	0	0
T62	26385	0	0	0
T63	256792	0	0	0
T64	546664	0	0	0
T65	19162	0	0	0
T66	102395	0	0	0
T70	37515	0	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	1341	0	0
T7	34919	307	0	0
T8	0	344	0	0
T9	0	150	0	0
T33	0	362	0	0
T34	0	178	0	0
T35	28460	0	0	0
T36	14461	0	0	0
T37	20637	0	0	0
T38	123561	0	0	0
T39	21635	0	0	0
T40	600390	0	0	0
T41	104051	0	0	0
T42	8577	0	0	0
T43	157202	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	1101	0	0
T7	34919	247	0	0
T8	0	284	0	0
T9	0	120	0	0
T33	0	302	0	0
T34	0	148	0	0
T35	28460	0	0	0
T36	14461	0	0	0
T37	20637	0	0	0
T38	123561	0	0	0
T39	21635	0	0	0
T40	600390	0	0	0
T41	104051	0	0	0
T42	8577	0	0	0
T43	157202	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694057524	693988317	0	0
T1	100906	100900	0	0
T2	385426	385418	0	0
T3	455635	455581	0	0
T10	23376	23308	0	0
T11	132058	132002	0	0
T12	1337	1262	0	0
T13	107758	107705	0	0
T20	38567	38498	0	0
T21	28049	27980	0	0
T22	231432	231338	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	694019659	0	0
T1	100906	100900	0	0
T2	385426	385418	0	0
T3	455635	455581	0	0
T10	23376	23308	0	0
T11	132058	132002	0	0
T12	1337	1262	0	0
T13	107758	107705	0	0
T20	38567	38498	0	0
T21	28049	27980	0	0
T22	231432	231338	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T11

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T20,T21,T5
1	0	1	Covered	T2,T3,T13
1	1	0	Covered	T21,T5,T44
1	1	1	Covered	T20,T5,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T5,T17
0	1	Covered	T20,T5,T16
1	0	Covered	T24,T49,T52

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T20,T5,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T24,T49,T52

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T5,T17
1	0	Covered	T103
1	1	Covered	T20,T5,T16

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T14,T16,T23

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T11,T20
1	Covered	T2,T5,T18

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T20,T16,T24

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T20,T5
1	Covered	T3,T11,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T11,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T11,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T11

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T11
Phase1St	198	Covered	T2,T3,T11
Phase2St	215	Covered	T2,T3,T11
Phase3St	233	Covered	T2,T3,T11
TerminalSt	249	Covered	T2,T3,T11
TimeoutSt	159	Covered	T20,T5,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T2,T3,T11
IdleSt->TimeoutSt	159	Covered	T20,T5,T17
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T57,T104,T103
Phase0St->Phase1St	198	Covered	T2,T3,T11
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T18,T24,T105
Phase1St->Phase2St	215	Covered	T2,T3,T11
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T24,T50,T106
Phase2St->Phase3St	233	Covered	T2,T3,T11
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T30,T93,T105
Phase3St->TerminalSt	249	Covered	T2,T3,T11
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T20,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T5,T17,T73
TimeoutSt->Phase0St	172	Covered	T20,T5,T16

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T5,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T5,T16
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T20,T5,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T17,T73
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T57,T103,T107
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T18,T24,T105
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T24,T50,T106
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T30,T93,T105
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T20,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	694191115	198	0	0
CheckAccumTrig0_A	694191115	462	0	0
CheckAccumTrig1_A	694191115	26	0	0
CheckClr_A	694191115	204	0	0
CheckEn_A	694058875	315326743	0	0
CheckPhase0_A	694191115	534	0	0
CheckPhase1_A	694191115	526	0	0
CheckPhase2_A	694191115	519	0	0
CheckPhase3_A	694191115	505	0	0
CheckTimeout0_A	694191115	1578	0	0
CheckTimeoutSt1_A	694191115	170619	0	0
CheckTimeoutSt2_A	694191115	1496	0	0
CheckTimeoutStTrig_A	694191115	55	0	0
ErrorStAllEscAsserted_A	694191115	1264	0	0
ErrorStIsTerminal_A	694191115	1024	0	0
EscStateOut_A	694057524	693988317	0	0
u_state_regs_A	694191115	694019659	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	198	0	0
T7	34919	49	0	0
T8	0	29	0	0
T9	0	38	0	0
T33	0	61	0	0
T34	0	21	0	0
T35	28460	0	0	0
T36	14461	0	0	0
T37	20637	0	0	0
T38	123561	0	0	0
T39	21635	0	0	0
T40	600390	0	0	0
T41	104051	0	0	0
T42	8577	0	0	0
T43	157202	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	462	0	0
T2	385426	2	0	0
T3	455635	1	0	0
T4	24656	0	0	0
T5	0	2	0	0
T6	0	1	0	0
T10	23376	0	0	0
T11	132058	1	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T14	0	2	0	0
T16	0	4	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	38567	0	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	26	0	0
T15	358905	0	0	0
T24	586029	1	0	0
T26	0	1	0	0
T47	282170	0	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	26385	0	0	0
T63	256792	0	0	0
T64	546664	0	0	0
T65	19162	0	0	0
T66	102395	0	0	0
T67	240728	0	0	0
T68	641028	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	204	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T4	24656	0	0	0
T10	23376	0	0	0
T11	132058	0	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T14	0	1	0	0
T16	0	1	0	0
T18	0	1	0	0
T20	38567	1	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T24	0	10	0	0
T28	0	1	0	0
T65	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694058875	315326743	0	0
T1	100906	100900	0	0
T2	385426	8655	0	0
T3	455635	625	0	0
T10	23376	23307	0	0
T11	132058	5697	0	0
T12	1337	602	0	0
T13	107758	106053	0	0
T20	38567	5886	0	0
T21	28049	22360	0	0
T22	231432	227854	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	534	0	0
T2	385426	2	0	0
T3	455635	1	0	0
T4	24656	0	0	0
T5	0	3	0	0
T6	0	1	0	0
T10	23376	0	0	0
T11	132058	1	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T14	0	2	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	38567	2	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	526	0	0
T2	385426	2	0	0
T3	455635	1	0	0
T4	24656	0	0	0
T5	0	3	0	0
T6	0	1	0	0
T10	23376	0	0	0
T11	132058	1	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T14	0	2	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	38567	2	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T46	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	519	0	0
T2	385426	2	0	0
T3	455635	1	0	0
T4	24656	0	0	0
T5	0	3	0	0
T6	0	1	0	0
T10	23376	0	0	0
T11	132058	1	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T14	0	2	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	38567	2	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T46	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	505	0	0
T2	385426	2	0	0
T3	455635	1	0	0
T4	24656	0	0	0
T5	0	3	0	0
T6	0	1	0	0
T10	23376	0	0	0
T11	132058	1	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T14	0	2	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	38567	2	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T46	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	1578	0	0
T4	24656	0	0	0
T5	564699	2	0	0
T16	0	11	0	0
T17	145102	1	0	0
T20	38567	2	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T23	0	14	0	0
T24	0	62	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T45	25151	0	0	0
T65	0	1	0	0
T73	91862	6	0	0
T75	0	1	0	0
T76	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	170619	0	0
T4	24656	0	0	0
T5	564699	138	0	0
T16	0	1934	0	0
T17	145102	15	0	0
T20	38567	1360	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T23	0	2914	0	0
T24	0	6439	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T45	25151	0	0	0
T65	0	110	0	0
T73	91862	1158	0	0
T75	0	146	0	0
T76	0	539	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	1496	0	0
T5	564699	1	0	0
T14	193991	0	0	0
T16	0	9	0	0
T17	145102	1	0	0
T23	0	14	0	0
T24	0	60	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T45	25151	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T73	91862	6	0	0
T75	0	1	0	0
T77	71274	0	0	0
T78	0	1	0	0
T79	41196	0	0	0
T80	126882	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	55	0	0
T4	24656	0	0	0
T5	564699	1	0	0
T16	0	2	0	0
T17	145102	0	0	0
T20	38567	2	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	3	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T45	25151	0	0	0
T65	0	1	0	0
T73	91862	0	0	0
T76	0	1	0	0
T78	0	1	0	0
T84	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	1264	0	0
T7	34919	316	0	0
T8	0	311	0	0
T9	0	168	0	0
T33	0	310	0	0
T34	0	159	0	0
T35	28460	0	0	0
T36	14461	0	0	0
T37	20637	0	0	0
T38	123561	0	0	0
T39	21635	0	0	0
T40	600390	0	0	0
T41	104051	0	0	0
T42	8577	0	0	0
T43	157202	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	1024	0	0
T7	34919	256	0	0
T8	0	251	0	0
T9	0	138	0	0
T33	0	250	0	0
T34	0	129	0	0
T35	28460	0	0	0
T36	14461	0	0	0
T37	20637	0	0	0
T38	123561	0	0	0
T39	21635	0	0	0
T40	600390	0	0	0
T41	104051	0	0	0
T42	8577	0	0	0
T43	157202	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694057524	693988317	0	0
T1	100906	100900	0	0
T2	385426	385418	0	0
T3	455635	455581	0	0
T10	23376	23308	0	0
T11	132058	132002	0	0
T12	1337	1262	0	0
T13	107758	107705	0	0
T20	38567	38498	0	0
T21	28049	27980	0	0
T22	231432	231338	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	694019659	0	0
T1	100906	100900	0	0
T2	385426	385418	0	0
T3	455635	455581	0	0
T10	23376	23308	0	0
T11	132058	132002	0	0
T12	1337	1262	0	0
T13	107758	107705	0	0
T20	38567	38498	0	0
T21	28049	27980	0	0
T22	231432	231338	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T11

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T20,T21,T5
1	0	1	Covered	T2,T3,T11
1	1	0	Covered	T20,T5,T44
1	1	1	Covered	T21,T5,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T5,T17
0	1	Covered	T5,T16,T70
1	0	Covered	T76,T50,T51

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T21,T5,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T76,T50,T51

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T5,T17
1	0	Covered	T27
1	1	Covered	T5,T16,T70

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T20
1	Covered	T11,T5,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T20,T5,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T20
1	Covered	T1,T22,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T11,T20
1	Covered	T2,T5,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T11,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T11,T20,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T11,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T22

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T11
Phase1St	198	Covered	T1,T2,T11
Phase2St	215	Covered	T1,T2,T11
Phase3St	233	Covered	T1,T2,T11
TerminalSt	249	Covered	T1,T2,T11
TimeoutSt	159	Covered	T21,T5,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T11
IdleSt->TimeoutSt	159	Covered	T21,T5,T17
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T14,T54,T108
Phase0St->Phase1St	198	Covered	T1,T2,T11
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T28,T105,T59
Phase1St->Phase2St	215	Covered	T1,T2,T11
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T17,T18,T16
Phase2St->Phase3St	233	Covered	T1,T2,T11
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T31,T109,T110
Phase3St->TerminalSt	249	Covered	T1,T2,T11
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T20,T5,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T21,T17,T6
TimeoutSt->Phase0St	172	Covered	T5,T16,T70

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T5,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T16,T70
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T21,T5,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T21,T17,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T14,T54,T108
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T28,T105,T59
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T11,T20
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T17,T18,T16
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T31,T109,T110
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T14,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	694191115	225	0	0
CheckAccumTrig0_A	694191115	512	0	0
CheckAccumTrig1_A	694191115	16	0	0
CheckClr_A	694191115	220	0	0
CheckEn_A	694058875	323792714	0	0
CheckPhase0_A	694191115	596	0	0
CheckPhase1_A	694191115	588	0	0
CheckPhase2_A	694191115	576	0	0
CheckPhase3_A	694191115	565	0	0
CheckTimeout0_A	694191115	1009	0	0
CheckTimeoutSt1_A	694191115	139073	0	0
CheckTimeoutSt2_A	694191115	915	0	0
CheckTimeoutStTrig_A	694191115	78	0	0
ErrorStAllEscAsserted_A	694191115	1305	0	0
ErrorStIsTerminal_A	694191115	1065	0	0
EscStateOut_A	694057524	693988317	0	0
u_state_regs_A	694191115	694019659	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	225	0	0
T7	34919	64	0	0
T8	0	55	0	0
T9	0	17	0	0
T33	0	75	0	0
T34	0	14	0	0
T35	28460	0	0	0
T36	14461	0	0	0
T37	20637	0	0	0
T38	123561	0	0	0
T39	21635	0	0	0
T40	600390	0	0	0
T41	104051	0	0	0
T42	8577	0	0	0
T43	157202	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	512	0	0
T1	100906	1	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T5	0	3	0	0
T10	23376	0	0	0
T11	132058	1	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T14	0	5	0	0
T17	0	2	0	0
T18	0	2	0	0
T19	0	3	0	0
T20	38567	1	0	0
T21	28049	0	0	0
T22	231432	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	16	0	0
T26	0	1	0	0
T29	21880	0	0	0
T50	604054	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T59	0	1	0	0
T82	883874	0	0	0
T88	0	1	0	0
T90	436540	0	0	0
T98	7341	0	0	0
T104	0	1	0	0
T108	0	1	0	0
T111	0	1	0	0
T112	15485	0	0	0
T113	102336	0	0	0
T114	18973	0	0	0
T115	9904	0	0	0
T116	312143	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	220	0	0
T4	24656	0	0	0
T5	564699	0	0	0
T14	0	4	0	0
T16	0	6	0	0
T17	145102	1	0	0
T18	0	1	0	0
T19	0	2	0	0
T20	38567	1	0	0
T21	28049	0	0	0
T22	231432	0	0	0
T23	0	2	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T45	25151	0	0	0
T46	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T73	91862	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694058875	323792714	0	0
T1	100906	1643	0	0
T2	385426	5433	0	0
T3	455635	380513	0	0
T10	23376	23307	0	0
T11	132058	4795	0	0
T12	1337	606	0	0
T13	107758	2316	0	0
T20	38567	27989	0	0
T21	28049	9471	0	0
T22	231432	19785	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	596	0	0
T1	100906	1	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T5	0	4	0	0
T10	23376	0	0	0
T11	132058	1	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T14	0	3	0	0
T17	0	2	0	0
T18	0	2	0	0
T19	0	3	0	0
T20	38567	1	0	0
T21	28049	0	0	0
T22	231432	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	588	0	0
T1	100906	1	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T5	0	4	0	0
T10	23376	0	0	0
T11	132058	1	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T14	0	3	0	0
T17	0	2	0	0
T18	0	2	0	0
T19	0	3	0	0
T20	38567	1	0	0
T21	28049	0	0	0
T22	231432	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	576	0	0
T1	100906	1	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T5	0	4	0	0
T10	23376	0	0	0
T11	132058	1	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T14	0	3	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	3	0	0
T20	38567	1	0	0
T21	28049	0	0	0
T22	231432	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	565	0	0
T1	100906	1	0	0
T2	385426	1	0	0
T3	455635	0	0	0
T5	0	4	0	0
T10	23376	0	0	0
T11	132058	1	0	0
T12	1337	0	0	0
T13	107758	0	0	0
T14	0	3	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	3	0	0
T20	38567	1	0	0
T21	28049	0	0	0
T22	231432	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	1009	0	0
T4	24656	0	0	0
T5	564699	1	0	0
T6	0	1	0	0
T16	0	16	0	0
T17	145102	1	0	0
T21	28049	4	0	0
T22	231432	0	0	0
T23	0	20	0	0
T24	0	1	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T45	25151	0	0	0
T46	0	3	0	0
T63	0	3	0	0
T70	0	1	0	0
T73	91862	0	0	0
T77	71274	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	139073	0	0
T4	24656	0	0	0
T5	564699	238	0	0
T6	0	44	0	0
T16	0	6383	0	0
T17	145102	39	0	0
T21	28049	608	0	0
T22	231432	0	0	0
T23	0	3256	0	0
T24	0	92	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T45	25151	0	0	0
T46	0	371	0	0
T63	0	718	0	0
T70	0	106	0	0
T73	91862	0	0	0
T77	71274	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	915	0	0
T4	24656	0	0	0
T5	564699	0	0	0
T6	0	1	0	0
T16	0	11	0	0
T17	145102	1	0	0
T21	28049	4	0	0
T22	231432	0	0	0
T23	0	20	0	0
T24	0	1	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T45	25151	0	0	0
T46	0	3	0	0
T63	0	3	0	0
T73	91862	0	0	0
T75	0	1	0	0
T77	71274	0	0	0
T78	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	78	0	0
T5	564699	1	0	0
T14	193991	0	0	0
T16	0	5	0	0
T17	145102	0	0	0
T32	22492	0	0	0
T44	35273	0	0	0
T45	25151	0	0	0
T54	0	2	0	0
T56	0	2	0	0
T70	0	1	0	0
T73	91862	0	0	0
T76	0	1	0	0
T77	71274	0	0	0
T79	41196	0	0	0
T80	126882	0	0	0
T84	0	2	0	0
T86	0	1	0	0
T87	0	2	0	0
T117	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	1305	0	0
T7	34919	334	0	0
T8	0	321	0	0
T9	0	150	0	0
T33	0	331	0	0
T34	0	169	0	0
T35	28460	0	0	0
T36	14461	0	0	0
T37	20637	0	0	0
T38	123561	0	0	0
T39	21635	0	0	0
T40	600390	0	0	0
T41	104051	0	0	0
T42	8577	0	0	0
T43	157202	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	1065	0	0
T7	34919	274	0	0
T8	0	261	0	0
T9	0	120	0	0
T33	0	271	0	0
T34	0	139	0	0
T35	28460	0	0	0
T36	14461	0	0	0
T37	20637	0	0	0
T38	123561	0	0	0
T39	21635	0	0	0
T40	600390	0	0	0
T41	104051	0	0	0
T42	8577	0	0	0
T43	157202	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694057524	693988317	0	0
T1	100906	100900	0	0
T2	385426	385418	0	0
T3	455635	455581	0	0
T10	23376	23308	0	0
T11	132058	132002	0	0
T12	1337	1262	0	0
T13	107758	107705	0	0
T20	38567	38498	0	0
T21	28049	27980	0	0
T22	231432	231338	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694191115	694019659	0	0
T1	100906	100900	0	0
T2	385426	385418	0	0
T3	455635	455581	0	0
T10	23376	23308	0	0
T11	132058	132002	0	0
T12	1337	1262	0	0
T13	107758	107705	0	0
T20	38567	38498	0	0
T21	28049	27980	0	0
T22	231432	231338	0	0