Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T111,T202,T203
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15316	0	0
DisabledNoTrigBkwd_A	2147483647	815268	0	0
DisabledNoTrigFwd_A	2147483647	1653845181	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15316	0	0
T24	765068	0	0	0
T28	230818	0	0	0
T29	46456	0	0	0
T57	459406	0	0	0
T79	20649	0	0	0
T88	38120	0	0	0
T111	3038	752	0	0
T112	202593	0	0	0
T113	58872	0	0	0
T114	99156	0	0	0
T115	116445	0	0	0
T200	439747	0	0	0
T202	0	870	0	0
T203	0	612	0	0
T204	1256	424	0	0
T205	0	1685	0	0
T206	0	960	0	0
T207	0	579	0	0
T208	0	367	0	0
T209	0	574	0	0
T210	0	552	0	0
T211	0	596	0	0
T212	0	795	0	0
T213	0	759	0	0
T214	0	869	0	0
T215	0	805	0	0
T216	0	834	0	0
T217	0	178	0	0
T218	0	1385	0	0
T219	3183	387	0	0
T220	4902	1333	0	0
T221	70433	0	0	0
T222	39822	0	0	0
T223	69463	0	0	0
T224	116980	0	0	0
T225	38976	0	0	0
T226	13137	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	815268	0	0
T1	590460	210	0	0
T2	386490	1	0	0
T3	2285348	5883	0	0
T4	1668080	1699	0	0
T6	410068	6927	0	0
T10	0	2457	0	0
T11	374882	2	0	0
T12	0	3	0	0
T13	1252504	2023	0	0
T14	0	6187	0	0
T15	0	13861	0	0
T16	218888	1	0	0
T17	569012	405	0	0
T18	339376	0	0	0
T19	44092	1	0	0
T20	36188	46	0	0
T23	0	3	0	0
T41	0	2805	0	0
T42	0	2	0	0
T43	0	18	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1653845181	0	0
T1	787280	218108	0	0
T2	515320	1259540	0	0
T3	2285348	2086809	0	0
T4	1668080	1176694	0	0
T6	410068	121158	0	0
T13	1252504	943493	0	0
T16	218888	162559	0	0
T17	569012	178277	0	0
T18	339376	223533	0	0
T19	44092	29378	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T111,T207,T212
1	1	Covered	T1,T3,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	731707716	6518	0	0
DisabledNoTrigBkwd_A	731707716	230544	0	0
DisabledNoTrigFwd_A	731707716	378590527	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	6518	0	0
T24	765068	0	0	0
T28	230818	0	0	0
T29	46456	0	0	0
T79	20649	0	0	0
T88	38120	0	0	0
T111	3038	752	0	0
T112	202593	0	0	0
T113	58872	0	0	0
T114	99156	0	0	0
T115	116445	0	0	0
T207	0	579	0	0
T212	0	795	0	0
T214	0	869	0	0
T215	0	805	0	0
T218	0	1385	0	0
T220	0	1333	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	230544	0	0
T1	196820	61	0	0
T2	128830	0	0	0
T3	571337	137	0	0
T4	417020	313	0	0
T6	102517	2452	0	0
T13	313126	0	0	0
T16	54722	1	0	0
T17	142253	153	0	0
T18	84844	0	0	0
T19	11023	1	0	0
T23	0	3	0	0
T42	0	2	0	0
T43	0	18	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	378590527	0	0
T1	196820	13027	0	0
T2	128830	128822	0	0
T3	571337	515768	0	0
T4	417020	221952	0	0
T6	102517	17726	0	0
T13	313126	312228	0	0
T16	54722	2106	0	0
T17	142253	22917	0	0
T18	84844	80001	0	0
T19	11023	5400	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T219
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	731707716	387	0	0
DisabledNoTrigBkwd_A	731707716	196223	0	0
DisabledNoTrigFwd_A	731707716	434658918	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	387	0	0
T200	439747	0	0	0
T219	3183	387	0	0
T220	4902	0	0	0
T223	69463	0	0	0
T224	116980	0	0	0
T225	38976	0	0	0
T226	13137	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	196223	0	0
T1	196820	29	0	0
T2	128830	0	0	0
T3	571337	1855	0	0
T4	417020	88	0	0
T6	102517	1867	0	0
T11	0	2	0	0
T13	313126	2015	0	0
T14	0	2185	0	0
T15	0	1431	0	0
T16	54722	0	0	0
T17	142253	165	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	0	28	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	434658918	0	0
T1	196820	9627	0	0
T2	128830	125525	0	0
T3	571337	686625	0	0
T4	417020	407354	0	0
T6	102517	586	0	0
T13	313126	6789	0	0
T16	54722	54657	0	0
T17	142253	602	0	0
T18	84844	12840	0	0
T19	11023	10971	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T204,T205,T206
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	731707716	5832	0	0
DisabledNoTrigBkwd_A	731707716	225537	0	0
DisabledNoTrigFwd_A	731707716	424702432	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	5832	0	0
T57	459406	0	0	0
T58	99209	0	0	0
T204	1256	424	0	0
T205	0	1685	0	0
T206	0	960	0	0
T209	0	574	0	0
T211	0	596	0	0
T213	0	759	0	0
T216	0	834	0	0
T221	70433	0	0	0
T222	39822	0	0	0
T227	411133	0	0	0
T228	9640	0	0	0
T229	6848	0	0	0
T230	55316	0	0	0
T231	191053	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	225537	0	0
T1	196820	120	0	0
T2	128830	1	0	0
T3	571337	3889	0	0
T4	417020	1277	0	0
T6	102517	4	0	0
T10	0	2453	0	0
T12	0	3	0	0
T13	313126	3	0	0
T14	0	1729	0	0
T15	0	10389	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	0	0	0
T19	11023	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	424702432	0	0
T1	196820	5312	0	0
T2	128830	884121	0	0
T3	571337	328047	0	0
T4	417020	133011	0	0
T6	102517	102252	0	0
T13	313126	312647	0	0
T16	54722	54657	0	0
T17	142253	142191	0	0
T18	84844	79406	0	0
T19	11023	2036	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T202,T203,T208
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	731707716	2579	0	0
DisabledNoTrigBkwd_A	731707716	162964	0	0
DisabledNoTrigFwd_A	731707716	415893304	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	2579	0	0
T44	6872	0	0	0
T80	394107	0	0	0
T89	6539	0	0	0
T90	235703	0	0	0
T202	3762	870	0	0
T203	0	612	0	0
T208	0	367	0	0
T210	0	552	0	0
T217	0	178	0	0
T232	30712	0	0	0
T233	380426	0	0	0
T234	376070	0	0	0
T235	16537	0	0	0
T236	7224	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	162964	0	0
T3	571337	2	0	0
T4	417020	21	0	0
T6	102517	2604	0	0
T10	0	4	0	0
T11	374882	0	0	0
T13	313126	5	0	0
T14	0	2273	0	0
T15	0	2041	0	0
T16	54722	0	0	0
T17	142253	87	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	36188	18	0	0
T41	0	2805	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	415893304	0	0
T1	196820	190142	0	0
T2	128830	121072	0	0
T3	571337	556369	0	0
T4	417020	414377	0	0
T6	102517	594	0	0
T13	313126	311829	0	0
T16	54722	51139	0	0
T17	142253	12567	0	0
T18	84844	51286	0	0
T19	11023	10971	0	0