Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.39	100.00	97.78	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T21,T22
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T6,T4
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T3,T6,T4
1	1	1	Covered	T3,T6,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T18
0	1	Covered	T3,T18,T13
1	0	Covered	T15,T23,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T6,T18
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T15,T23,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T18
1	0	Covered	T25,T26
1	1	Covered	T3,T18,T13

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T2,T3,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T6,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T3,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T6

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T3,T6
Phase3St	233	Covered	T1,T3,T6
TerminalSt	249	Covered	T1,T3,T6
TimeoutSt	159	Covered	T3,T6,T18

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T3,T6,T18
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T6,T23,T27
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T2,T16,T10
Phase1St->Phase2St	215	Covered	T1,T3,T6
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T3,T6,T28
Phase2St->Phase3St	233	Covered	T1,T3,T6
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T6,T13,T29
Phase3St->TerminalSt	249	Covered	T1,T3,T6
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T3,T6,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T3,T6,T18
TimeoutSt->Phase0St	172	Covered	T3,T18,T13

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T13
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T23,T27
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T16,T10
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T6,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T13,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T6,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1074	0	0
CheckAccumTrig0_A	2147483647	2468	0	0
CheckAccumTrig1_A	2147483647	99	0	0
CheckClr_A	2147483647	1125	0	0
CheckEn_A	2147483647	1304934506	0	0
CheckPhase0_A	2147483647	2779	0	0
CheckPhase1_A	2147483647	2712	0	0
CheckPhase2_A	2147483647	2661	0	0
CheckPhase3_A	2147483647	2619	0	0
CheckTimeout0_A	2147483647	5905	0	0
CheckTimeoutSt1_A	2147483647	647842	0	0
CheckTimeoutSt2_A	2147483647	5529	0	0
CheckTimeoutStTrig_A	2147483647	268	0	0
ErrorStAllEscAsserted_A	2147483647	5028	0	0
ErrorStIsTerminal_A	2147483647	4068	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1074	0	0
T7	137452	275	0	0
T8	0	249	0	0
T9	0	117	0	0
T30	0	299	0	0
T31	0	134	0	0
T32	247996	0	0	0
T33	1314444	0	0	0
T34	86744	0	0	0
T35	500260	0	0	0
T36	33768	0	0	0
T37	423912	0	0	0
T38	1678100	0	0	0
T39	195820	0	0	0
T40	1367980	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2468	0	0
T1	590460	3	0	0
T2	386490	1	0	0
T3	2285348	27	0	0
T4	1668080	19	0	0
T6	410068	10	0	0
T10	0	3	0	0
T11	374882	1	0	0
T12	0	1	0	0
T13	1252504	5	0	0
T14	0	7	0	0
T15	0	9	0	0
T16	218888	1	0	0
T17	569012	3	0	0
T18	339376	0	0	0
T19	44092	1	0	0
T20	36188	2	0	0
T23	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	99	0	0
T15	417871	1	0	0
T23	1639434	1	0	0
T24	765068	1	0	0
T27	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	29426	0	0	0
T62	114367	0	0	0
T63	32589	0	0	0
T64	153290	0	0	0
T65	33371	0	0	0
T66	72824	0	0	0
T67	32825	0	0	0
T68	356897	0	0	0
T69	276506	0	0	0
T70	942046	0	0	0
T71	135323	0	0	0
T72	131543	0	0	0
T73	106608	0	0	0
T74	105808	0	0	0
T75	112102	0	0	0
T76	22367	0	0	0
T77	181610	0	0	0
T78	156451	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1125	0	0
T2	128830	1	0	0
T3	1142674	14	0	0
T4	1668080	9	0	0
T6	410068	4	0	0
T10	258356	1	0	0
T11	1124646	0	0	0
T13	1252504	2	0	0
T16	218888	1	0	0
T17	569012	0	0	0
T18	339376	0	0	0
T19	44092	0	0	0
T20	144752	0	0	0
T24	0	6	0	0
T29	0	3	0	0
T41	0	1	0	0
T45	0	2	0	0
T61	0	1	0	0
T63	0	1	0	0
T66	0	1	0	0
T68	0	4	0	0
T70	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1304934506	0	0
T1	787280	218107	0	0
T2	515320	1259539	0	0
T3	2285348	1711059	0	0
T4	1668080	1107917	0	0
T6	410068	20429	0	0
T13	1252504	27168	0	0
T16	218888	162556	0	0
T17	569012	178276	0	0
T18	339376	213582	0	0
T19	44092	25984	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2779	0	0
T1	590460	3	0	0
T2	386490	1	0	0
T3	2285348	28	0	0
T4	1668080	19	0	0
T6	410068	8	0	0
T10	0	2	0	0
T11	374882	1	0	0
T13	1252504	6	0	0
T14	0	7	0	0
T15	0	7	0	0
T16	218888	1	0	0
T17	569012	3	0	0
T18	339376	1	0	0
T19	44092	1	0	0
T20	36188	3	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T84	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2712	0	0
T1	590460	3	0	0
T2	386490	0	0	0
T3	2285348	28	0	0
T4	1668080	19	0	0
T6	410068	8	0	0
T10	0	1	0	0
T11	374882	1	0	0
T13	1252504	6	0	0
T14	0	5	0	0
T15	0	10	0	0
T16	218888	0	0	0
T17	569012	3	0	0
T18	339376	1	0	0
T19	44092	1	0	0
T20	36188	3	0	0
T23	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T84	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2661	0	0
T1	590460	3	0	0
T2	386490	0	0	0
T3	2285348	27	0	0
T4	1668080	19	0	0
T6	410068	7	0	0
T10	0	1	0	0
T11	374882	1	0	0
T13	1252504	6	0	0
T14	0	4	0	0
T15	0	10	0	0
T16	218888	0	0	0
T17	569012	3	0	0
T18	339376	1	0	0
T19	44092	1	0	0
T20	36188	3	0	0
T23	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T84	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2619	0	0
T1	590460	3	0	0
T2	386490	0	0	0
T3	2285348	27	0	0
T4	1668080	18	0	0
T6	410068	6	0	0
T10	0	1	0	0
T11	374882	1	0	0
T13	1252504	5	0	0
T14	0	4	0	0
T15	0	10	0	0
T16	218888	0	0	0
T17	569012	3	0	0
T18	339376	1	0	0
T19	44092	1	0	0
T20	36188	3	0	0
T23	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T84	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5905	0	0
T3	1714011	11	0	0
T4	1251060	0	0	0
T5	20462	0	0	0
T6	307551	1	0	0
T10	129178	0	0	0
T11	1499528	0	0	0
T13	1252504	1	0	0
T14	154459	4	0	0
T15	417871	2	0	0
T16	164166	0	0	0
T17	426759	0	0	0
T18	339376	6	0	0
T19	44092	0	0	0
T20	144752	2	0	0
T23	0	7	0	0
T24	0	255	0	0
T28	0	1	0	0
T29	0	7	0	0
T63	0	1	0	0
T68	0	64	0	0
T84	73557	8	0	0
T85	0	5	0	0
T86	0	11	0	0
T87	0	3	0	0
T88	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	647842	0	0
T3	1714011	731	0	0
T4	1251060	0	0	0
T5	20462	0	0	0
T6	307551	90	0	0
T10	129178	0	0	0
T11	1499528	0	0	0
T13	1252504	82	0	0
T14	154459	109	0	0
T15	417871	173	0	0
T16	164166	0	0	0
T17	426759	0	0	0
T18	339376	1094	0	0
T19	44092	0	0	0
T20	144752	38	0	0
T23	0	339	0	0
T24	0	18476	0	0
T28	0	37	0	0
T29	0	932	0	0
T63	0	4	0	0
T68	0	8402	0	0
T84	73557	1314	0	0
T85	0	310	0	0
T86	0	729	0	0
T87	0	178	0	0
T88	0	112	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5529	0	0
T3	1714011	10	0	0
T4	1251060	0	0	0
T5	20462	0	0	0
T6	307551	1	0	0
T10	129178	0	0	0
T11	1499528	0	0	0
T13	1252504	0	0	0
T14	154459	4	0	0
T15	417871	0	0	0
T16	164166	0	0	0
T17	426759	0	0	0
T18	339376	5	0	0
T19	44092	0	0	0
T20	144752	1	0	0
T23	0	1	0	0
T24	0	619	0	0
T29	0	3	0	0
T46	0	1	0	0
T68	0	63	0	0
T74	0	16	0	0
T76	0	3	0	0
T81	0	1	0	0
T82	0	16	0	0
T84	73557	5	0	0
T85	0	4	0	0
T86	0	11	0	0
T87	0	2	0	0
T88	0	2	0	0
T89	0	1	0	0
T90	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	268	0	0
T3	571337	1	0	0
T4	417020	0	0	0
T5	61386	0	0	0
T6	102517	0	0	0
T10	258356	0	0	0
T11	1124646	0	0	0
T12	229862	0	0	0
T13	626252	1	0	0
T14	308918	0	0	0
T15	1253613	1	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	169688	1	0	0
T19	22046	0	0	0
T20	108564	1	0	0
T24	0	2	0	0
T28	0	1	0	0
T29	0	4	0	0
T41	911442	0	0	0
T42	572800	0	0	0
T43	25903	0	0	0
T46	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T68	0	1	0	0
T81	0	2	0	0
T84	220671	2	0	0
T85	0	1	0	0
T91	0	1	0	0
T92	0	4	0	0
T93	0	2	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	111006	0	0	0
T97	118558	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5028	0	0
T7	137452	1263	0	0
T8	0	1196	0	0
T9	0	628	0	0
T30	0	1299	0	0
T31	0	642	0	0
T32	247996	0	0	0
T33	1314444	0	0	0
T34	86744	0	0	0
T35	500260	0	0	0
T36	33768	0	0	0
T37	423912	0	0	0
T38	1678100	0	0	0
T39	195820	0	0	0
T40	1367980	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4068	0	0
T7	137452	1023	0	0
T8	0	956	0	0
T9	0	508	0	0
T30	0	1059	0	0
T31	0	522	0	0
T32	247996	0	0	0
T33	1314444	0	0	0
T34	86744	0	0	0
T35	500260	0	0	0
T36	33768	0	0	0
T37	423912	0	0	0
T38	1678100	0	0	0
T39	195820	0	0	0
T40	1367980	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	787280	786976	0	0
T2	515320	515288	0	0
T3	2285348	2285064	0	0
T4	1668080	1668032	0	0
T6	410068	410028	0	0
T13	1252504	1252476	0	0
T16	218888	218628	0	0
T17	569012	568764	0	0
T18	339376	339056	0	0
T19	44092	43884	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	787280	786976	0	0
T2	515320	515288	0	0
T3	2285348	2285064	0	0
T4	1668080	1668032	0	0
T6	410068	410028	0	0
T13	1252504	1252476	0	0
T16	218888	218628	0	0
T17	569012	568764	0	0
T18	339376	339056	0	0
T19	44092	43884	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T6,T4
1	0	1	Covered	T1,T4,T17
1	1	0	Covered	T3,T6,T18
1	1	1	Covered	T3,T18,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T18,T13
0	1	Covered	T3,T13,T68
1	0	Covered	T24,T44,T46

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T18,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T24,T44,T46

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T18,T13
1	0	Not Covered
1	1	Covered	T3,T13,T68

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T3,T4,T16

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T3,T6,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T6,T42,T62

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T4
1	Covered	T1,T3,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T6,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T6,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T6
Phase1St	198	Covered	T1,T3,T6
Phase2St	215	Covered	T1,T3,T6
Phase3St	233	Covered	T1,T3,T6
TerminalSt	249	Covered	T1,T3,T6
TimeoutSt	159	Covered	T3,T18,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T3,T6
IdleSt->TimeoutSt	159	Covered	T3,T18,T13
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T91,T92
Phase0St->Phase1St	198	Covered	T1,T3,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T16,T79,T24
Phase1St->Phase2St	215	Covered	T1,T3,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T6,T70,T98
Phase2St->Phase3St	233	Covered	T1,T3,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T29,T24,T46
Phase3St->TerminalSt	249	Covered	T1,T3,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T6,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T18,T85
TimeoutSt->Phase0St	172	Covered	T3,T13,T68

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T68
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T85
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T94,T99
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T16,T79,T24
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T70,T98
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T24,T46
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T4,T61
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	731707716	283	0	0
CheckAccumTrig0_A	731707716	857	0	0
CheckAccumTrig1_A	731707716	36	0	0
CheckClr_A	731707716	393	0	0
CheckEn_A	731462374	291740751	0	0
CheckPhase0_A	731707716	934	0	0
CheckPhase1_A	731707716	910	0	0
CheckPhase2_A	731707716	888	0	0
CheckPhase3_A	731707716	874	0	0
CheckTimeout0_A	731707716	1766	0	0
CheckTimeoutSt1_A	731707716	186644	0	0
CheckTimeoutSt2_A	731707716	1660	0	0
CheckTimeoutStTrig_A	731707716	65	0	0
ErrorStAllEscAsserted_A	731707716	1192	0	0
ErrorStIsTerminal_A	731707716	952	0	0
EscStateOut_A	731460799	731390320	0	0
u_state_regs_A	731707716	731534806	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	283	0	0
T7	34363	73	0	0
T8	0	66	0	0
T9	0	33	0	0
T30	0	81	0	0
T31	0	30	0	0
T32	61999	0	0	0
T33	328611	0	0	0
T34	21686	0	0	0
T35	125065	0	0	0
T36	8442	0	0	0
T37	105978	0	0	0
T38	419525	0	0	0
T39	48955	0	0	0
T40	341995	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	857	0	0
T1	196820	1	0	0
T2	128830	0	0	0
T3	571337	4	0	0
T4	417020	4	0	0
T6	102517	4	0	0
T13	313126	0	0	0
T16	54722	1	0	0
T17	142253	1	0	0
T18	84844	0	0	0
T19	11023	1	0	0
T23	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	36	0	0
T24	765068	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T57	0	2	0	0
T59	0	2	0	0
T70	942046	0	0	0
T71	135323	0	0	0
T72	131543	0	0	0
T73	106608	0	0	0
T74	105808	0	0	0
T75	112102	0	0	0
T76	22367	0	0	0
T77	181610	0	0	0
T78	156451	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	393	0	0
T4	417020	2	0	0
T6	102517	3	0	0
T10	129178	0	0	0
T11	374882	0	0	0
T13	313126	0	0	0
T16	54722	1	0	0
T17	142253	0	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	36188	0	0	0
T24	0	6	0	0
T29	0	3	0	0
T61	0	1	0	0
T66	0	1	0	0
T68	0	3	0	0
T70	0	1	0	0
T79	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731462374	291740751	0	0
T1	196820	13027	0	0
T2	128830	128822	0	0
T3	571337	504207	0	0
T4	417020	221952	0	0
T6	102517	6775	0	0
T13	313126	16187	0	0
T16	54722	2106	0	0
T17	142253	22917	0	0
T18	84844	80000	0	0
T19	11023	2008	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	934	0	0
T1	196820	1	0	0
T2	128830	0	0	0
T3	571337	5	0	0
T4	417020	4	0	0
T6	102517	3	0	0
T13	313126	1	0	0
T16	54722	1	0	0
T17	142253	1	0	0
T18	84844	0	0	0
T19	11023	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	910	0	0
T1	196820	1	0	0
T2	128830	0	0	0
T3	571337	5	0	0
T4	417020	4	0	0
T6	102517	3	0	0
T13	313126	1	0	0
T16	54722	0	0	0
T17	142253	1	0	0
T18	84844	0	0	0
T19	11023	1	0	0
T23	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	888	0	0
T1	196820	1	0	0
T2	128830	0	0	0
T3	571337	5	0	0
T4	417020	4	0	0
T6	102517	2	0	0
T13	313126	1	0	0
T16	54722	0	0	0
T17	142253	1	0	0
T18	84844	0	0	0
T19	11023	1	0	0
T23	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	874	0	0
T1	196820	1	0	0
T2	128830	0	0	0
T3	571337	5	0	0
T4	417020	4	0	0
T6	102517	2	0	0
T13	313126	1	0	0
T16	54722	0	0	0
T17	142253	1	0	0
T18	84844	0	0	0
T19	11023	1	0	0
T23	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	1766	0	0
T3	571337	3	0	0
T4	417020	0	0	0
T6	102517	0	0	0
T11	374882	0	0	0
T13	313126	1	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	1	0	0
T19	11023	0	0	0
T20	36188	0	0	0
T23	0	1	0	0
T28	0	1	0	0
T29	0	3	0	0
T68	0	4	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	186644	0	0
T3	571337	220	0	0
T4	417020	0	0	0
T6	102517	0	0	0
T11	374882	0	0	0
T13	313126	82	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	166	0	0
T19	11023	0	0	0
T20	36188	0	0	0
T23	0	101	0	0
T28	0	37	0	0
T29	0	117	0	0
T68	0	406	0	0
T85	0	62	0	0
T86	0	60	0	0
T87	0	148	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	1660	0	0
T3	571337	2	0	0
T4	417020	0	0	0
T6	102517	0	0	0
T11	374882	0	0	0
T13	313126	0	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	1	0	0
T19	11023	0	0	0
T20	36188	0	0	0
T23	0	1	0	0
T24	0	293	0	0
T68	0	3	0	0
T74	0	6	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	65	0	0
T3	571337	1	0	0
T4	417020	0	0	0
T6	102517	0	0	0
T11	374882	0	0	0
T13	313126	1	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	36188	0	0	0
T28	0	1	0	0
T29	0	3	0	0
T50	0	1	0	0
T68	0	1	0	0
T81	0	1	0	0
T91	0	1	0	0
T92	0	3	0	0
T93	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	1192	0	0
T7	34363	311	0	0
T8	0	279	0	0
T9	0	147	0	0
T30	0	308	0	0
T31	0	147	0	0
T32	61999	0	0	0
T33	328611	0	0	0
T34	21686	0	0	0
T35	125065	0	0	0
T36	8442	0	0	0
T37	105978	0	0	0
T38	419525	0	0	0
T39	48955	0	0	0
T40	341995	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	952	0	0
T7	34363	251	0	0
T8	0	219	0	0
T9	0	117	0	0
T30	0	248	0	0
T31	0	117	0	0
T32	61999	0	0	0
T33	328611	0	0	0
T34	21686	0	0	0
T35	125065	0	0	0
T36	8442	0	0	0
T37	105978	0	0	0
T38	419525	0	0	0
T39	48955	0	0	0
T40	341995	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731460799	731390320	0	0
T1	196820	196744	0	0
T2	128830	128822	0	0
T3	571337	571266	0	0
T4	417020	417008	0	0
T6	102517	102507	0	0
T13	313126	313119	0	0
T16	54722	54657	0	0
T17	142253	142191	0	0
T18	84844	84764	0	0
T19	11023	10971	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	731534806	0	0
T1	196820	196744	0	0
T2	128830	128822	0	0
T3	571337	571266	0	0
T4	417020	417008	0	0
T6	102517	102507	0	0
T13	313126	313119	0	0
T16	54722	54657	0	0
T17	142253	142191	0	0
T18	84844	84764	0	0
T19	11023	10971	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T6,T18
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T3,T18,T85
1	1	1	Covered	T3,T6,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T18
0	1	Covered	T20,T84,T15
1	0	Covered	T15,T46,T47

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T6,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T46,T47

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T18
1	0	Covered	T26
1	1	Covered	T20,T84,T15

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T2,T3,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T4
1	Covered	T1,T4,T41

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T3,T84,T96

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T6,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T4,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T3,T6
Phase3St	233	Covered	T1,T3,T6
TerminalSt	249	Covered	T1,T3,T6
TimeoutSt	159	Covered	T3,T6,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T3,T6,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T23,T27,T92
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T2,T10,T14
Phase1St->Phase2St	215	Covered	T1,T3,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T28,T21,T57
Phase2St->Phase3St	233	Covered	T1,T3,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T92,T100,T101
Phase3St->TerminalSt	249	Covered	T1,T3,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T4,T84
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T6,T18
TimeoutSt->Phase0St	172	Covered	T20,T84,T15

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T84,T15
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T23,T27,T92
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T10,T14
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T21,T57
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T92,T100,T101
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T84
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	731707716	238	0	0
CheckAccumTrig0_A	731707716	531	0	0
CheckAccumTrig1_A	731707716	25	0	0
CheckClr_A	731707716	247	0	0
CheckEn_A	731462374	343282688	0	0
CheckPhase0_A	731707716	626	0	0
CheckPhase1_A	731707716	608	0	0
CheckPhase2_A	731707716	598	0	0
CheckPhase3_A	731707716	590	0	0
CheckTimeout0_A	731707716	1222	0	0
CheckTimeoutSt1_A	731707716	143879	0	0
CheckTimeoutSt2_A	731707716	1116	0	0
CheckTimeoutStTrig_A	731707716	79	0	0
ErrorStAllEscAsserted_A	731707716	1287	0	0
ErrorStIsTerminal_A	731707716	1047	0	0
EscStateOut_A	731460799	731390320	0	0
u_state_regs_A	731707716	731534806	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	238	0	0
T7	34363	63	0	0
T8	0	52	0	0
T9	0	32	0	0
T30	0	57	0	0
T31	0	34	0	0
T32	61999	0	0	0
T33	328611	0	0	0
T34	21686	0	0	0
T35	125065	0	0	0
T36	8442	0	0	0
T37	105978	0	0	0
T38	419525	0	0	0
T39	48955	0	0	0
T40	341995	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	531	0	0
T1	196820	1	0	0
T2	128830	1	0	0
T3	571337	8	0	0
T4	417020	10	0	0
T6	102517	1	0	0
T10	0	2	0	0
T12	0	1	0	0
T13	313126	1	0	0
T14	0	3	0	0
T15	0	1	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	0	0	0
T19	11023	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	25	0	0
T12	114931	0	0	0
T15	417871	1	0	0
T23	819717	0	0	0
T27	0	1	0	0
T41	455721	0	0	0
T42	572800	0	0	0
T43	25903	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T61	14713	0	0	0
T85	28548	0	0	0
T91	0	1	0	0
T96	55503	0	0	0
T97	118558	0	0	0
T98	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	247	0	0
T2	128830	1	0	0
T3	571337	4	0	0
T4	417020	7	0	0
T6	102517	0	0	0
T10	0	1	0	0
T13	313126	0	0	0
T14	0	2	0	0
T15	0	2	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	36188	0	0	0
T23	0	4	0	0
T28	0	1	0	0
T68	0	1	0	0
T84	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731462374	343282688	0	0
T1	196820	5312	0	0
T2	128830	884120	0	0
T3	571337	301993	0	0
T4	417020	133011	0	0
T6	102517	12474	0	0
T13	313126	2088	0	0
T16	54722	54656	0	0
T17	142253	142190	0	0
T18	84844	79405	0	0
T19	11023	2036	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	626	0	0
T1	196820	1	0	0
T2	128830	1	0	0
T3	571337	8	0	0
T4	417020	10	0	0
T6	102517	1	0	0
T10	0	2	0	0
T13	313126	1	0	0
T14	0	3	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	0	1	0	0
T84	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	608	0	0
T1	196820	1	0	0
T2	128830	0	0	0
T3	571337	8	0	0
T4	417020	10	0	0
T6	102517	1	0	0
T10	0	1	0	0
T13	313126	1	0	0
T14	0	1	0	0
T15	0	3	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	0	1	0	0
T84	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	598	0	0
T1	196820	1	0	0
T2	128830	0	0	0
T3	571337	8	0	0
T4	417020	10	0	0
T6	102517	1	0	0
T10	0	1	0	0
T13	313126	1	0	0
T14	0	1	0	0
T15	0	3	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	0	1	0	0
T84	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	590	0	0
T1	196820	1	0	0
T2	128830	0	0	0
T3	571337	8	0	0
T4	417020	10	0	0
T6	102517	1	0	0
T10	0	1	0	0
T13	313126	1	0	0
T14	0	1	0	0
T15	0	3	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	0	1	0	0
T84	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	1222	0	0
T3	571337	6	0	0
T4	417020	0	0	0
T6	102517	1	0	0
T11	374882	0	0	0
T13	313126	0	0	0
T14	0	2	0	0
T15	0	2	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	1	0	0
T19	11023	0	0	0
T20	36188	1	0	0
T23	0	5	0	0
T29	0	1	0	0
T68	0	21	0	0
T84	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	143879	0	0
T3	571337	267	0	0
T4	417020	0	0	0
T6	102517	90	0	0
T11	374882	0	0	0
T13	313126	0	0	0
T14	0	59	0	0
T15	0	173	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	225	0	0
T19	11023	0	0	0
T20	36188	9	0	0
T23	0	235	0	0
T29	0	208	0	0
T68	0	2690	0	0
T84	0	186	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	1116	0	0
T3	571337	6	0	0
T4	417020	0	0	0
T6	102517	1	0	0
T11	374882	0	0	0
T13	313126	0	0	0
T14	0	2	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	1	0	0
T19	11023	0	0	0
T20	36188	0	0	0
T24	0	72	0	0
T46	0	1	0	0
T68	0	21	0	0
T74	0	1	0	0
T81	0	1	0	0
T82	0	16	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	79	0	0
T5	20462	0	0	0
T10	129178	0	0	0
T11	374882	0	0	0
T12	114931	0	0	0
T14	154459	0	0	0
T15	417871	1	0	0
T20	36188	1	0	0
T23	0	5	0	0
T24	0	1	0	0
T29	0	1	0	0
T41	455721	0	0	0
T74	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0
T84	73557	2	0	0
T90	0	1	0	0
T96	55503	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	1287	0	0
T7	34363	335	0	0
T8	0	302	0	0
T9	0	164	0	0
T30	0	322	0	0
T31	0	164	0	0
T32	61999	0	0	0
T33	328611	0	0	0
T34	21686	0	0	0
T35	125065	0	0	0
T36	8442	0	0	0
T37	105978	0	0	0
T38	419525	0	0	0
T39	48955	0	0	0
T40	341995	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	1047	0	0
T7	34363	275	0	0
T8	0	242	0	0
T9	0	134	0	0
T30	0	262	0	0
T31	0	134	0	0
T32	61999	0	0	0
T33	328611	0	0	0
T34	21686	0	0	0
T35	125065	0	0	0
T36	8442	0	0	0
T37	105978	0	0	0
T38	419525	0	0	0
T39	48955	0	0	0
T40	341995	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731460799	731390320	0	0
T1	196820	196744	0	0
T2	128830	128822	0	0
T3	571337	571266	0	0
T4	417020	417008	0	0
T6	102517	102507	0	0
T13	313126	313119	0	0
T16	54722	54657	0	0
T17	142253	142191	0	0
T18	84844	84764	0	0
T19	11023	10971	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	731534806	0	0
T1	196820	196744	0	0
T2	128830	128822	0	0
T3	571337	571266	0	0
T4	417020	417008	0	0
T6	102517	102507	0	0
T13	313126	313119	0	0
T16	54722	54657	0	0
T17	142253	142191	0	0
T18	84844	84764	0	0
T19	11023	10971	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T6,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T22
1	1	1	Covered	T3,T6,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T16
1	0	1	Covered	T4,T17,T96
1	1	0	Covered	T3,T4,T18
1	1	1	Covered	T18,T14,T84

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T18,T14,T84
0	1	Covered	T84,T63,T44
1	0	Covered	T87,T82,T46

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T18,T14,T84
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T87,T82,T46

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T14,T84
1	0	Not Covered
1	1	Covered	T84,T63,T44

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T17
1	Covered	T6,T13,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T4
1	Covered	T4,T84,T41

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T4,T13
1	Covered	T3,T4,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T4
1	Covered	T4,T20,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T6,T4,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T4,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T6,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T13,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T6,T4
Phase1St	198	Covered	T3,T6,T4
Phase2St	215	Covered	T3,T6,T4
Phase3St	233	Covered	T3,T6,T4
TerminalSt	249	Covered	T3,T6,T4
TimeoutSt	159	Covered	T18,T14,T84

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T3,T6,T4
IdleSt->TimeoutSt	159	Covered	T18,T14,T84
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T10,T44
Phase0St->Phase1St	198	Covered	T3,T6,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T87,T81,T104
Phase1St->Phase2St	215	Covered	T3,T6,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T14,T92,T105
Phase2St->Phase3St	233	Covered	T3,T6,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T4,T81,T54
Phase3St->TerminalSt	249	Covered	T3,T6,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T6,T4,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T18,T14,T68
TimeoutSt->Phase0St	172	Covered	T84,T63,T87

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T14,T84
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T84,T63,T87
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T18,T14,T84
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T18,T14,T68
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T10,T44
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T6,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T6,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T87,T81,T104
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T6,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T6,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T14,T92,T105
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T6,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T6,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T81,T54
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T6,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T6,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T4,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T6,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	731707716	267	0	0
CheckAccumTrig0_A	731707716	550	0	0
CheckAccumTrig1_A	731707716	19	0	0
CheckClr_A	731707716	251	0	0
CheckEn_A	731462374	320380453	0	0
CheckPhase0_A	731707716	617	0	0
CheckPhase1_A	731707716	600	0	0
CheckPhase2_A	731707716	588	0	0
CheckPhase3_A	731707716	579	0	0
CheckTimeout0_A	731707716	1991	0	0
CheckTimeoutSt1_A	731707716	212636	0	0
CheckTimeoutSt2_A	731707716	1907	0	0
CheckTimeoutStTrig_A	731707716	63	0	0
ErrorStAllEscAsserted_A	731707716	1262	0	0
ErrorStIsTerminal_A	731707716	1022	0	0
EscStateOut_A	731460799	731390320	0	0
u_state_regs_A	731707716	731534806	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	267	0	0
T7	34363	69	0	0
T8	0	63	0	0
T9	0	30	0	0
T30	0	76	0	0
T31	0	29	0	0
T32	61999	0	0	0
T33	328611	0	0	0
T34	21686	0	0	0
T35	125065	0	0	0
T36	8442	0	0	0
T37	105978	0	0	0
T38	419525	0	0	0
T39	48955	0	0	0
T40	341995	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	550	0	0
T3	571337	1	0	0
T4	417020	4	0	0
T6	102517	3	0	0
T10	0	1	0	0
T11	374882	0	0	0
T13	313126	1	0	0
T14	0	3	0	0
T15	0	7	0	0
T16	54722	0	0	0
T17	142253	1	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	36188	1	0	0
T41	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	19	0	0
T27	0	1	0	0
T46	0	1	0	0
T50	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T79	20649	0	0	0
T82	0	1	0	0
T87	29010	1	0	0
T91	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	316399	0	0	0
T109	92181	0	0	0
T110	182251	0	0	0
T111	3038	0	0	0
T112	202593	0	0	0
T113	58872	0	0	0
T114	99156	0	0	0
T115	116445	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	251	0	0
T4	417020	2	0	0
T6	102517	2	0	0
T10	129178	1	0	0
T11	374882	0	0	0
T13	313126	0	0	0
T14	0	2	0	0
T15	0	6	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	36188	0	0	0
T41	0	1	0	0
T62	0	1	0	0
T70	0	1	0	0
T87	0	2	0	0
T88	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731462374	320380453	0	0
T1	196820	190141	0	0
T2	128830	121072	0	0
T3	571337	525210	0	0
T4	417020	345601	0	0
T6	102517	594	0	0
T13	313126	2104	0	0
T16	54722	51138	0	0
T17	142253	12567	0	0
T18	84844	51285	0	0
T19	11023	10970	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	617	0	0
T3	571337	1	0	0
T4	417020	4	0	0
T6	102517	2	0	0
T11	374882	0	0	0
T13	313126	1	0	0
T14	0	3	0	0
T15	0	7	0	0
T16	54722	0	0	0
T17	142253	1	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	36188	1	0	0
T41	0	2	0	0
T84	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	600	0	0
T3	571337	1	0	0
T4	417020	4	0	0
T6	102517	2	0	0
T11	374882	0	0	0
T13	313126	1	0	0
T14	0	3	0	0
T15	0	7	0	0
T16	54722	0	0	0
T17	142253	1	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	36188	1	0	0
T41	0	2	0	0
T84	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	588	0	0
T3	571337	1	0	0
T4	417020	4	0	0
T6	102517	2	0	0
T11	374882	0	0	0
T13	313126	1	0	0
T14	0	2	0	0
T15	0	7	0	0
T16	54722	0	0	0
T17	142253	1	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	36188	1	0	0
T41	0	2	0	0
T84	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	579	0	0
T3	571337	1	0	0
T4	417020	3	0	0
T6	102517	2	0	0
T11	374882	0	0	0
T13	313126	1	0	0
T14	0	2	0	0
T15	0	7	0	0
T16	54722	0	0	0
T17	142253	1	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	36188	1	0	0
T41	0	2	0	0
T84	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	1991	0	0
T5	20462	0	0	0
T10	129178	0	0	0
T11	374882	0	0	0
T13	313126	0	0	0
T14	154459	2	0	0
T15	417871	0	0	0
T18	84844	3	0	0
T19	11023	0	0	0
T20	36188	0	0	0
T24	0	251	0	0
T29	0	1	0	0
T63	0	1	0	0
T68	0	5	0	0
T84	73557	1	0	0
T86	0	8	0	0
T87	0	2	0	0
T88	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	212636	0	0
T5	20462	0	0	0
T10	129178	0	0	0
T11	374882	0	0	0
T13	313126	0	0	0
T14	154459	50	0	0
T15	417871	0	0	0
T18	84844	502	0	0
T19	11023	0	0	0
T20	36188	0	0	0
T24	0	17969	0	0
T29	0	185	0	0
T63	0	4	0	0
T68	0	530	0	0
T84	73557	12	0	0
T86	0	548	0	0
T87	0	30	0	0
T88	0	112	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	1907	0	0
T5	20462	0	0	0
T10	129178	0	0	0
T11	374882	0	0	0
T13	313126	0	0	0
T14	154459	2	0	0
T15	417871	0	0	0
T18	84844	3	0	0
T19	11023	0	0	0
T20	36188	0	0	0
T24	0	251	0	0
T29	0	1	0	0
T68	0	5	0	0
T84	73557	0	0	0
T86	0	8	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	63	0	0
T5	20462	0	0	0
T12	114931	0	0	0
T15	417871	0	0	0
T41	455721	0	0	0
T42	572800	0	0	0
T43	25903	0	0	0
T44	0	1	0	0
T46	0	3	0	0
T49	0	2	0	0
T51	0	1	0	0
T63	0	1	0	0
T82	0	3	0	0
T84	73557	1	0	0
T85	28548	0	0	0
T92	0	1	0	0
T96	55503	0	0	0
T97	118558	0	0	0
T116	0	1	0	0
T117	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	1262	0	0
T7	34363	297	0	0
T8	0	300	0	0
T9	0	175	0	0
T30	0	325	0	0
T31	0	165	0	0
T32	61999	0	0	0
T33	328611	0	0	0
T34	21686	0	0	0
T35	125065	0	0	0
T36	8442	0	0	0
T37	105978	0	0	0
T38	419525	0	0	0
T39	48955	0	0	0
T40	341995	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	1022	0	0
T7	34363	237	0	0
T8	0	240	0	0
T9	0	145	0	0
T30	0	265	0	0
T31	0	135	0	0
T32	61999	0	0	0
T33	328611	0	0	0
T34	21686	0	0	0
T35	125065	0	0	0
T36	8442	0	0	0
T37	105978	0	0	0
T38	419525	0	0	0
T39	48955	0	0	0
T40	341995	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731460799	731390320	0	0
T1	196820	196744	0	0
T2	128830	128822	0	0
T3	571337	571266	0	0
T4	417020	417008	0	0
T6	102517	102507	0	0
T13	313126	313119	0	0
T16	54722	54657	0	0
T17	142253	142191	0	0
T18	84844	84764	0	0
T19	11023	10971	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	731534806	0	0
T1	196820	196744	0	0
T2	128830	128822	0	0
T3	571337	571266	0	0
T4	417020	417008	0	0
T6	102517	102507	0	0
T13	313126	313119	0	0
T16	54722	54657	0	0
T17	142253	142191	0	0
T18	84844	84764	0	0
T19	11023	10971	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T21
1	1	1	Covered	T1,T3,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T18,T13
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T84,T15,T85
1	1	1	Covered	T3,T18,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T18,T20
0	1	Covered	T18,T85,T24
1	0	Covered	T23,T45,T46

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T18,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T45,T46

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T18,T20
1	0	Covered	T25
1	1	Covered	T18,T85,T24

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T3,T6,T24

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T4
1	Covered	T1,T3,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T6,T4,T14

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T3,T20,T11

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T6,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T6,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T6
Phase1St	198	Covered	T1,T3,T6
Phase2St	215	Covered	T1,T3,T6
Phase3St	233	Covered	T1,T3,T6
TerminalSt	249	Covered	T1,T3,T6
TimeoutSt	159	Covered	T3,T18,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T3,T6
IdleSt->TimeoutSt	159	Covered	T3,T18,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T53,T118,T119
Phase0St->Phase1St	198	Covered	T1,T3,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T120,T99,T121
Phase1St->Phase2St	215	Covered	T1,T3,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T3,T46,T57
Phase2St->Phase3St	233	Covered	T1,T3,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T6,T13,T49
Phase3St->TerminalSt	249	Covered	T1,T3,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T4,T13
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T20,T84
TimeoutSt->Phase0St	172	Covered	T18,T85,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T85,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T20,T84
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T53,T118,T119
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T120,T99,T121
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T46,T57
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T13,T49
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T13,T41
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	731707716	286	0	0
CheckAccumTrig0_A	731707716	530	0	0
CheckAccumTrig1_A	731707716	19	0	0
CheckClr_A	731707716	234	0	0
CheckEn_A	731462374	349530614	0	0
CheckPhase0_A	731707716	602	0	0
CheckPhase1_A	731707716	594	0	0
CheckPhase2_A	731707716	587	0	0
CheckPhase3_A	731707716	576	0	0
CheckTimeout0_A	731707716	926	0	0
CheckTimeoutSt1_A	731707716	104683	0	0
CheckTimeoutSt2_A	731707716	846	0	0
CheckTimeoutStTrig_A	731707716	61	0	0
ErrorStAllEscAsserted_A	731707716	1287	0	0
ErrorStIsTerminal_A	731707716	1047	0	0
EscStateOut_A	731460799	731390320	0	0
u_state_regs_A	731707716	731534806	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	286	0	0
T7	34363	70	0	0
T8	0	68	0	0
T9	0	22	0	0
T30	0	85	0	0
T31	0	41	0	0
T32	61999	0	0	0
T33	328611	0	0	0
T34	21686	0	0	0
T35	125065	0	0	0
T36	8442	0	0	0
T37	105978	0	0	0
T38	419525	0	0	0
T39	48955	0	0	0
T40	341995	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	530	0	0
T1	196820	1	0	0
T2	128830	0	0	0
T3	571337	14	0	0
T4	417020	1	0	0
T6	102517	2	0	0
T11	0	1	0	0
T13	313126	3	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	54722	0	0	0
T17	142253	1	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	19	0	0
T23	819717	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T56	0	1	0	0
T58	0	1	0	0
T60	0	1	0	0
T61	14713	0	0	0
T62	114367	0	0	0
T63	32589	0	0	0
T64	153290	0	0	0
T65	33371	0	0	0
T66	72824	0	0	0
T67	32825	0	0	0
T68	356897	0	0	0
T69	276506	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	234	0	0
T3	571337	10	0	0
T4	417020	0	0	0
T6	102517	1	0	0
T11	374882	0	0	0
T13	313126	2	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	36188	0	0	0
T41	0	1	0	0
T45	0	2	0	0
T63	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731462374	349530614	0	0
T1	196820	9627	0	0
T2	128830	125525	0	0
T3	571337	379649	0	0
T4	417020	407353	0	0
T6	102517	586	0	0
T13	313126	6789	0	0
T16	54722	54656	0	0
T17	142253	602	0	0
T18	84844	2892	0	0
T19	11023	10970	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	602	0	0
T1	196820	1	0	0
T2	128830	0	0	0
T3	571337	14	0	0
T4	417020	1	0	0
T6	102517	2	0	0
T11	0	1	0	0
T13	313126	3	0	0
T14	0	1	0	0
T16	54722	0	0	0
T17	142253	1	0	0
T18	84844	1	0	0
T19	11023	0	0	0
T20	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	594	0	0
T1	196820	1	0	0
T2	128830	0	0	0
T3	571337	14	0	0
T4	417020	1	0	0
T6	102517	2	0	0
T11	0	1	0	0
T13	313126	3	0	0
T14	0	1	0	0
T16	54722	0	0	0
T17	142253	1	0	0
T18	84844	1	0	0
T19	11023	0	0	0
T20	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	587	0	0
T1	196820	1	0	0
T2	128830	0	0	0
T3	571337	13	0	0
T4	417020	1	0	0
T6	102517	2	0	0
T11	0	1	0	0
T13	313126	3	0	0
T14	0	1	0	0
T16	54722	0	0	0
T17	142253	1	0	0
T18	84844	1	0	0
T19	11023	0	0	0
T20	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	576	0	0
T1	196820	1	0	0
T2	128830	0	0	0
T3	571337	13	0	0
T4	417020	1	0	0
T6	102517	1	0	0
T11	0	1	0	0
T13	313126	2	0	0
T14	0	1	0	0
T16	54722	0	0	0
T17	142253	1	0	0
T18	84844	1	0	0
T19	11023	0	0	0
T20	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	926	0	0
T3	571337	2	0	0
T4	417020	0	0	0
T6	102517	0	0	0
T11	374882	0	0	0
T13	313126	0	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	1	0	0
T19	11023	0	0	0
T20	36188	1	0	0
T23	0	1	0	0
T24	0	4	0	0
T29	0	2	0	0
T68	0	34	0	0
T84	0	5	0	0
T85	0	4	0	0
T86	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	104683	0	0
T3	571337	244	0	0
T4	417020	0	0	0
T6	102517	0	0	0
T11	374882	0	0	0
T13	313126	0	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	201	0	0
T19	11023	0	0	0
T20	36188	29	0	0
T23	0	3	0	0
T24	0	507	0	0
T29	0	422	0	0
T68	0	4776	0	0
T84	0	1116	0	0
T85	0	248	0	0
T86	0	121	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	846	0	0
T3	571337	2	0	0
T4	417020	0	0	0
T6	102517	0	0	0
T11	374882	0	0	0
T13	313126	0	0	0
T16	54722	0	0	0
T17	142253	0	0	0
T18	84844	0	0	0
T19	11023	0	0	0
T20	36188	1	0	0
T24	0	3	0	0
T29	0	2	0	0
T68	0	34	0	0
T74	0	9	0	0
T76	0	3	0	0
T84	0	5	0	0
T85	0	3	0	0
T86	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	61	0	0
T5	20462	0	0	0
T10	129178	0	0	0
T11	374882	0	0	0
T13	313126	0	0	0
T14	154459	0	0	0
T15	417871	0	0	0
T18	84844	1	0	0
T19	11023	0	0	0
T20	36188	0	0	0
T24	0	1	0	0
T46	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T84	73557	0	0	0
T85	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	1287	0	0
T7	34363	320	0	0
T8	0	315	0	0
T9	0	142	0	0
T30	0	344	0	0
T31	0	166	0	0
T32	61999	0	0	0
T33	328611	0	0	0
T34	21686	0	0	0
T35	125065	0	0	0
T36	8442	0	0	0
T37	105978	0	0	0
T38	419525	0	0	0
T39	48955	0	0	0
T40	341995	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	1047	0	0
T7	34363	260	0	0
T8	0	255	0	0
T9	0	112	0	0
T30	0	284	0	0
T31	0	136	0	0
T32	61999	0	0	0
T33	328611	0	0	0
T34	21686	0	0	0
T35	125065	0	0	0
T36	8442	0	0	0
T37	105978	0	0	0
T38	419525	0	0	0
T39	48955	0	0	0
T40	341995	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731460799	731390320	0	0
T1	196820	196744	0	0
T2	128830	128822	0	0
T3	571337	571266	0	0
T4	417020	417008	0	0
T6	102517	102507	0	0
T13	313126	313119	0	0
T16	54722	54657	0	0
T17	142253	142191	0	0
T18	84844	84764	0	0
T19	11023	10971	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731707716	731534806	0	0
T1	196820	196744	0	0
T2	128830	128822	0	0
T3	571337	571266	0	0
T4	417020	417008	0	0
T6	102517	102507	0	0
T13	313126	313119	0	0
T16	54722	54657	0	0
T17	142253	142191	0	0
T18	84844	84764	0	0
T19	11023	10971	0	0