Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65174921	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31763274

1

T1

1073

T2

2679

T3

93147

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14715065	1			T1	383		T2	1179		T3	36996
values[0x0]	39960069	1			T1	1497		T2	3675		T3	128560
values[0x1]	42263061	1			T1	1525		T2	3543		T3	128404

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55480926	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41457269

1

T1

1369

T2

3405

T3

117689

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	311300	1			T1	11		T2	35		T4	1525
valid_sources[0x01]	307359	1			T1	10		T2	40		T4	1502
valid_sources[0x02]	316396	1			T1	13		T2	25		T4	1825
valid_sources[0x03]	317030	1			T1	13		T2	27		T4	1801
valid_sources[0x04]	308092	1			T1	12		T2	26		T4	1930
valid_sources[0x05]	312541	1			T1	12		T2	28		T4	1704
valid_sources[0x06]	310030	1			T1	22		T2	42		T4	1498
valid_sources[0x07]	392772	1			T1	10		T2	25		T4	1955
valid_sources[0x08]	324944	1			T1	6		T2	31		T4	2327
valid_sources[0x09]	331115	1			T1	12		T2	31		T4	1848
valid_sources[0x0a]	687543	1			T1	7		T2	26		T4	1986
valid_sources[0x0b]	317836	1			T1	8		T2	38		T4	2001
valid_sources[0x0c]	316215	1			T1	12		T2	39		T4	1697
valid_sources[0x0d]	309997	1			T1	14		T2	18		T4	1558
valid_sources[0x0e]	410391	1			T1	14		T2	55		T4	2078
valid_sources[0x0f]	320244	1			T1	15		T2	33		T4	1809
valid_sources[0x10]	329264	1			T1	16		T2	34		T4	1897
valid_sources[0x11]	312949	1			T1	18		T2	20		T4	1333
valid_sources[0x12]	309652	1			T1	10		T2	43		T4	1304
valid_sources[0x13]	318661	1			T1	15		T2	17		T4	1687
valid_sources[0x14]	323985	1			T1	17		T2	25		T4	1606
valid_sources[0x15]	311711	1			T1	23		T2	43		T4	1481
valid_sources[0x16]	312261	1			T1	9		T2	38		T4	1751
valid_sources[0x17]	746987	1			T1	13		T2	36		T4	1525
valid_sources[0x18]	314420	1			T1	24		T2	23		T4	1477
valid_sources[0x19]	324498	1			T1	16		T2	23		T4	1967
valid_sources[0x1a]	300387	1			T1	9		T2	32		T4	1644
valid_sources[0x1b]	328892	1			T1	18		T2	31		T4	2208
valid_sources[0x1c]	318096	1			T1	12		T2	24		T4	1651
valid_sources[0x1d]	320440	1			T1	8		T2	32		T4	1981
valid_sources[0x1e]	305647	1			T1	17		T2	35		T4	1583
valid_sources[0x1f]	1005253	1			T1	13		T2	23		T4	1908
valid_sources[0x20]	323206	1			T1	10		T2	34		T4	1829
valid_sources[0x21]	306243	1			T1	11		T2	36		T4	1808
valid_sources[0x22]	313356	1			T1	15		T2	33		T4	1723
valid_sources[0x23]	311548	1			T1	13		T2	15		T4	1677
valid_sources[0x24]	314224	1			T1	12		T2	36		T4	1855
valid_sources[0x25]	325146	1			T1	19		T2	25		T4	1611
valid_sources[0x26]	656185	1			T1	12		T2	34		T4	1823
valid_sources[0x27]	301367	1			T1	8		T2	21		T4	1985
valid_sources[0x28]	324994	1			T1	17		T2	32		T4	1631
valid_sources[0x29]	330524	1			T1	10		T2	40		T4	1896
valid_sources[0x2a]	315222	1			T1	7		T2	29		T4	1974
valid_sources[0x2b]	330983	1			T1	10		T2	21		T4	1921
valid_sources[0x2c]	317992	1			T1	13		T2	33		T4	1839
valid_sources[0x2d]	389128	1			T1	10		T2	38		T4	1360
valid_sources[0x2e]	324957	1			T1	12		T2	36		T4	1732
valid_sources[0x2f]	320699	1			T1	13		T2	39		T4	2313
valid_sources[0x30]	317344	1			T1	9		T2	49		T4	1852
valid_sources[0x31]	328262	1			T1	15		T2	39		T4	1991
valid_sources[0x32]	315413	1			T1	17		T2	45		T4	1612
valid_sources[0x33]	315163	1			T1	14		T2	15		T4	1699
valid_sources[0x34]	684970	1			T1	19		T2	32		T4	1651
valid_sources[0x35]	320303	1			T1	20		T2	42		T4	1957
valid_sources[0x36]	624726	1			T1	19		T2	45		T4	2194
valid_sources[0x37]	305750	1			T1	13		T2	52		T4	2015
valid_sources[0x38]	663257	1			T1	9		T2	25		T4	1675
valid_sources[0x39]	314799	1			T1	12		T2	32		T4	1607
valid_sources[0x3a]	312032	1			T1	13		T2	30		T4	1760
valid_sources[0x3b]	331647	1			T1	9		T2	47		T4	1622
valid_sources[0x3c]	743160	1			T1	18		T2	42		T4	1391
valid_sources[0x3d]	642430	1			T1	16		T2	30		T4	1851
valid_sources[0x3e]	307972	1			T1	10		T2	33		T4	1519
valid_sources[0x3f]	316220	1			T1	19		T2	31		T4	1358
valid_sources[0x40]	323099	1			T1	24		T2	30		T4	1827
valid_sources[0x41]	332354	1			T1	8		T2	37		T4	1628
valid_sources[0x42]	301148	1			T1	11		T2	44		T4	1760
valid_sources[0x43]	312600	1			T1	13		T2	32		T4	1546
valid_sources[0x44]	326397	1			T1	10		T2	36		T4	1637
valid_sources[0x45]	322634	1			T1	15		T2	42		T4	1568
valid_sources[0x46]	555110	1			T1	10		T2	40		T4	1712
valid_sources[0x47]	323359	1			T1	10		T2	28		T4	1643
valid_sources[0x48]	310764	1			T1	14		T2	22		T4	1948
valid_sources[0x49]	319928	1			T1	11		T2	40		T4	1878
valid_sources[0x4a]	318464	1			T1	13		T2	53		T4	1737
valid_sources[0x4b]	338312	1			T1	14		T2	24		T4	1912
valid_sources[0x4c]	573624	1			T1	12		T2	46		T4	1521
valid_sources[0x4d]	319295	1			T1	11		T2	38		T4	1586
valid_sources[0x4e]	314969	1			T1	15		T2	41		T4	1897
valid_sources[0x4f]	320077	1			T1	20		T2	40		T4	1665
valid_sources[0x50]	312864	1			T1	18		T2	47		T4	2183
valid_sources[0x51]	320726	1			T1	9		T2	38		T4	2099
valid_sources[0x52]	719246	1			T1	22		T2	27		T4	1723
valid_sources[0x53]	309344	1			T1	10		T2	36		T4	1606
valid_sources[0x54]	659055	1			T1	11		T2	43		T4	1834
valid_sources[0x55]	310971	1			T1	9		T2	26		T4	1436
valid_sources[0x56]	552772	1			T1	13		T2	33		T4	2314
valid_sources[0x57]	309081	1			T1	8		T2	34		T4	1785
valid_sources[0x58]	320779	1			T1	13		T2	31		T4	1521
valid_sources[0x59]	318233	1			T1	13		T2	35		T4	1831
valid_sources[0x5a]	898532	1			T1	16		T2	37		T4	1905
valid_sources[0x5b]	328726	1			T1	10		T2	37		T4	2035
valid_sources[0x5c]	334634	1			T1	15		T2	38		T4	1488
valid_sources[0x5d]	629060	1			T1	19		T2	44		T4	1589
valid_sources[0x5e]	308388	1			T1	15		T2	30		T4	1898
valid_sources[0x5f]	343525	1			T1	13		T2	22		T4	1922
valid_sources[0x60]	307568	1			T1	14		T2	34		T4	1523
valid_sources[0x61]	322458	1			T1	17		T2	35		T4	2239
valid_sources[0x62]	310857	1			T1	6		T2	45		T4	1696
valid_sources[0x63]	309371	1			T1	11		T2	16		T4	1603
valid_sources[0x64]	313880	1			T1	19		T2	35		T4	1293
valid_sources[0x65]	309425	1			T1	6		T2	29		T4	2052
valid_sources[0x66]	314676	1			T1	5		T2	23		T4	1696
valid_sources[0x67]	316987	1			T1	14		T2	25		T4	1457
valid_sources[0x68]	310260	1			T1	28		T2	28		T4	1788
valid_sources[0x69]	775012	1			T1	10		T2	35		T4	1545
valid_sources[0x6a]	314317	1			T1	19		T2	37		T4	1797
valid_sources[0x6b]	322033	1			T1	8		T2	25		T4	1935
valid_sources[0x6c]	778468	1			T1	10		T2	34		T4	1918
valid_sources[0x6d]	310231	1			T1	8		T2	26		T4	1783
valid_sources[0x6e]	322766	1			T1	19		T2	41		T4	1430
valid_sources[0x6f]	303363	1			T1	11		T2	32		T4	1812
valid_sources[0x70]	620880	1			T1	7		T2	46		T4	1697
valid_sources[0x71]	303053	1			T1	15		T2	24		T4	1391
valid_sources[0x72]	320267	1			T1	5		T2	30		T4	1759
valid_sources[0x73]	319371	1			T1	17		T2	35		T4	1437
valid_sources[0x74]	307964	1			T1	20		T2	34		T4	2159
valid_sources[0x75]	322499	1			T1	9		T2	45		T4	1535
valid_sources[0x76]	313272	1			T1	15		T2	31		T4	1794
valid_sources[0x77]	800405	1			T1	19		T2	24		T4	1701
valid_sources[0x78]	317424	1			T1	15		T2	26		T4	2105
valid_sources[0x79]	805839	1			T1	11		T2	40		T4	1922
valid_sources[0x7a]	319468	1			T1	24		T2	44		T4	2106
valid_sources[0x7b]	321786	1			T1	21		T2	39		T4	2124
valid_sources[0x7c]	306625	1			T1	12		T2	33		T4	1750
valid_sources[0x7d]	536750	1			T1	16		T2	17		T4	1735
valid_sources[0x7e]	321957	1			T1	9		T2	25		T4	1908
valid_sources[0x7f]	332080	1			T1	7		T2	19		T4	2008
valid_sources[0x80]	319342	1			T1	21		T2	33		T4	1778

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7346948

1

T1

186

T2

544

T3

18626

values[0x0]

all_enables

biggest_size

15382831

1

T1

544

T2

1373

T3

47813

values[0x1]

all_enables

biggest_size

9033495

1

T1

343

T2

762

T3

26708