Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T199,T200,T201
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15799	0	0
DisabledNoTrigBkwd_A	2147483647	774180	0	0
DisabledNoTrigFwd_A	2147483647	1426432467	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15799	0	0
T32	783818	0	0	0
T50	43914	0	0	0
T51	14051	0	0	0
T121	441282	0	0	0
T123	37120	0	0	0
T184	0	1901	0	0
T199	0	653	0	0
T200	2927	640	0	0
T201	1730	182	0	0
T202	4149	626	0	0
T203	2657	418	0	0
T204	0	553	0	0
T205	0	697	0	0
T206	0	829	0	0
T207	0	466	0	0
T208	0	1341	0	0
T209	0	271	0	0
T210	0	1066	0	0
T211	0	1261	0	0
T212	0	1380	0	0
T213	0	442	0	0
T214	0	1519	0	0
T215	0	643	0	0
T216	0	527	0	0
T217	0	384	0	0
T218	12019	0	0	0
T219	519670	0	0	0
T220	1579572	0	0	0
T221	497354	0	0	0
T222	275912	0	0	0
T223	205964	0	0	0
T224	47664	0	0	0
T225	89559	0	0	0
T226	6409	0	0	0
T227	39616	0	0	0
T228	6963	0	0	0
T229	103030	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	774180	0	0
T1	41929	3	0	0
T2	70413	0	0	0
T3	456976	2950	0	0
T4	467016	1528	0	0
T5	3423488	10655	0	0
T6	0	7465	0	0
T7	877596	666	0	0
T8	0	23	0	0
T12	471272	38	0	0
T13	0	276	0	0
T14	0	1390	0	0
T16	0	1	0	0
T17	0	5398	0	0
T18	0	1020	0	0
T19	320124	4	0	0
T20	170808	8	0	0
T21	338564	8	0	0
T22	76038	0	0	0
T23	204354	63	0	0
T45	0	74	0	0
T46	0	27	0	0
T47	0	156	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1426432467	0	0
T1	167716	128766	0	0
T2	281652	101658	0	0
T3	456976	232950	0	0
T4	467016	459366	0	0
T5	3423488	1973998	0	0
T7	877596	252659	0	0
T12	471272	324887	0	0
T19	320124	242852	0	0
T20	170808	152344	0	0
T21	338564	172777	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T200,T203,T205
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	658293941	3543	0	0
DisabledNoTrigBkwd_A	658293941	268129	0	0
DisabledNoTrigFwd_A	658293941	297807599	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	3543	0	0
T32	391909	0	0	0
T123	18560	0	0	0
T200	2927	640	0	0
T201	865	0	0	0
T203	0	418	0	0
T205	0	697	0	0
T211	0	1261	0	0
T216	0	527	0	0
T218	12019	0	0	0
T219	259835	0	0	0
T220	789786	0	0	0
T221	248677	0	0	0
T222	137956	0	0	0
T223	102982	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	268129	0	0
T1	41929	3	0	0
T2	70413	0	0	0
T3	114244	0	0	0
T4	116754	1354	0	0
T5	855872	8063	0	0
T7	219399	428	0	0
T12	117818	2	0	0
T17	0	1859	0	0
T19	80031	4	0	0
T20	42702	8	0	0
T21	84641	8	0	0
T23	0	63	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	297807599	0	0
T1	41929	3132	0	0
T2	70413	9231	0	0
T3	114244	114239	0	0
T4	116754	130259	0	0
T5	855872	111530	0	0
T7	219399	25188	0	0
T12	117818	111600	0	0
T19	80031	3059	0	0
T20	42702	24397	0	0
T21	84641	7745	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T202,T208,T215
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	658293941	2610	0	0
DisabledNoTrigBkwd_A	658293941	172252	0	0
DisabledNoTrigFwd_A	658293941	382184642	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	2610	0	0
T50	43914	0	0	0
T51	14051	0	0	0
T121	441282	0	0	0
T202	4149	626	0	0
T203	2657	0	0	0
T208	0	1341	0	0
T215	0	643	0	0
T225	89559	0	0	0
T226	6409	0	0	0
T227	39616	0	0	0
T228	6963	0	0	0
T229	103030	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	172252	0	0
T3	114244	1093	0	0
T4	116754	20	0	0
T5	855872	564	0	0
T6	0	4152	0	0
T7	219399	238	0	0
T8	0	1	0	0
T12	117818	0	0	0
T13	0	276	0	0
T14	0	729	0	0
T17	0	1821	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T46	0	11	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	382184642	0	0
T1	41929	41878	0	0
T2	70413	12189	0	0
T3	114244	3069	0	0
T4	116754	107270	0	0
T5	855872	788427	0	0
T7	219399	2160	0	0
T12	117818	117731	0	0
T19	80031	79931	0	0
T20	42702	42649	0	0
T21	84641	7761	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T204,T206
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	658293941	3991	0	0
DisabledNoTrigBkwd_A	658293941	168676	0	0
DisabledNoTrigFwd_A	658293941	367408939	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	3991	0	0
T32	391909	0	0	0
T123	18560	0	0	0
T201	865	182	0	0
T204	0	553	0	0
T206	0	829	0	0
T207	0	466	0	0
T213	0	442	0	0
T214	0	1519	0	0
T219	259835	0	0	0
T220	789786	0	0	0
T221	248677	0	0	0
T222	137956	0	0	0
T223	102982	0	0	0
T224	47664	0	0	0
T230	29528	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	168676	0	0
T3	114244	1854	0	0
T4	116754	23	0	0
T5	855872	384	0	0
T6	0	3313	0	0
T7	219399	0	0	0
T12	117818	27	0	0
T14	0	1	0	0
T17	0	1706	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T45	0	74	0	0
T46	0	10	0	0
T47	0	156	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	367408939	0	0
T1	41929	41878	0	0
T2	70413	17113	0	0
T3	114244	1652	0	0
T4	116754	111812	0	0
T5	855872	760393	0	0
T7	219399	217840	0	0
T12	117818	3110	0	0
T19	80031	79931	0	0
T20	42702	42649	0	0
T21	84641	78505	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T199,T184,T209
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	658293941	5655	0	0
DisabledNoTrigBkwd_A	658293941	165123	0	0
DisabledNoTrigFwd_A	658293941	379031287	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	5655	0	0
T31	303434	0	0	0
T184	0	1901	0	0
T199	1503	653	0	0
T209	0	271	0	0
T210	0	1066	0	0
T212	0	1380	0	0
T217	0	384	0	0
T231	125996	0	0	0
T232	4693	0	0	0
T233	720585	0	0	0
T234	841487	0	0	0
T235	433438	0	0	0
T236	82118	0	0	0
T237	217083	0	0	0
T238	345632	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	165123	0	0
T3	114244	3	0	0
T4	116754	131	0	0
T5	855872	1644	0	0
T7	219399	0	0	0
T8	0	22	0	0
T12	117818	9	0	0
T14	0	660	0	0
T16	0	1	0	0
T17	0	12	0	0
T18	0	1020	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T46	0	6	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	379031287	0	0
T1	41929	41878	0	0
T2	70413	63125	0	0
T3	114244	113990	0	0
T4	116754	110025	0	0
T5	855872	313648	0	0
T7	219399	7471	0	0
T12	117818	92446	0	0
T19	80031	79931	0	0
T20	42702	42649	0	0
T21	84641	78766	0	0