Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T24,T25
1	1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T4,T22
1	0	Covered	T12,T5,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T12,T5,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T4,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T12,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T12
1	Covered	T2,T3,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T4,T12

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T3,T4
IdleSt->TimeoutSt	159	Covered	T2,T3,T4
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T5,T6,T27
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T28,T29,T30
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T6,T31,T32
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T5,T31,T33
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T4,T12,T20
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T3,T4
TimeoutSt->Phase0St	172	Covered	T2,T4,T12

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T12
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T6,T27
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T28,T29,T30
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T31,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T31,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T12,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	739	0	0
CheckAccumTrig0_A	2147483647	2252	0	0
CheckAccumTrig1_A	2147483647	89	0	0
CheckClr_A	2147483647	1008	0	0
CheckEn_A	2147483647	1161759623	0	0
CheckPhase0_A	2147483647	2498	0	0
CheckPhase1_A	2147483647	2447	0	0
CheckPhase2_A	2147483647	2402	0	0
CheckPhase3_A	2147483647	2358	0	0
CheckTimeout0_A	2147483647	3429	0	0
CheckTimeoutSt1_A	2147483647	401775	0	0
CheckTimeoutSt2_A	2147483647	3134	0	0
CheckTimeoutStTrig_A	2147483647	200	0	0
ErrorStAllEscAsserted_A	2147483647	3876	0	0
ErrorStIsTerminal_A	2147483647	3156	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	739	0	0
T9	169344	255	0	0
T10	0	91	0	0
T11	0	126	0	0
T34	0	129	0	0
T35	0	138	0	0
T36	145476	0	0	0
T37	595876	0	0	0
T38	48300	0	0	0
T39	324148	0	0	0
T40	302292	0	0	0
T41	203112	0	0	0
T42	115568	0	0	0
T43	17556	0	0	0
T44	64616	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2252	0	0
T1	41929	1	0	0
T2	70413	0	0	0
T3	456976	3	0	0
T4	467016	13	0	0
T5	3423488	22	0	0
T6	0	23	0	0
T7	877596	2	0	0
T8	0	2	0	0
T12	471272	4	0	0
T13	0	1	0	0
T14	0	3	0	0
T16	0	1	0	0
T17	0	3	0	0
T18	0	1	0	0
T19	320124	1	0	0
T20	170808	3	0	0
T21	338564	1	0	0
T22	76038	0	0	0
T23	204354	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	89	0	0
T5	1711744	2	0	0
T6	0	1	0	0
T8	292042	0	0	0
T12	117818	1	0	0
T13	203752	0	0	0
T14	313826	0	0	0
T15	497813	0	0	0
T17	370348	0	0	0
T22	50692	0	0	0
T23	136236	0	0	0
T26	35505	2	0	0
T27	0	1	0	0
T30	0	2	0	0
T31	0	4	0	0
T36	0	1	0	0
T44	0	1	0	0
T45	165198	0	0	0
T49	62474	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	133598	0	0	0
T62	376353	0	0	0
T63	23579	0	0	0
T64	156303	0	0	0
T65	513131	0	0	0
T66	122252	0	0	0
T67	151142	0	0	0
T68	355203	0	0	0
T69	54111	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1008	0	0
T4	350262	7	0	0
T5	2567616	7	0	0
T6	102533	16	0	0
T7	658197	0	0	0
T8	438063	0	0	0
T12	353454	4	0	0
T16	371153	0	0	0
T18	142985	1	0	0
T19	240093	0	0	0
T20	128106	3	0	0
T21	253923	0	0	0
T22	76038	0	0	0
T23	204354	0	0	0
T26	0	3	0	0
T29	0	2	0	0
T31	0	3	0	0
T46	10614	0	0	0
T47	111153	0	0	0
T48	66711	0	0	0
T49	62474	0	0	0
T50	0	2	0	0
T61	133598	1	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	86818	0	0	0
T78	31311	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1161759623	0	0
T1	167716	128763	0	0
T2	281652	91532	0	0
T3	456976	119554	0	0
T4	467016	410893	0	0
T5	3423488	2021538	0	0
T7	877596	229619	0	0
T12	471272	235576	0	0
T19	320124	242849	0	0
T20	170808	152341	0	0
T21	338564	172775	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2498	0	0
T1	41929	1	0	0
T2	140826	1	0	0
T3	456976	3	0	0
T4	467016	18	0	0
T5	3423488	23	0	0
T6	0	15	0	0
T7	877596	2	0	0
T8	0	2	0	0
T12	471272	6	0	0
T13	0	1	0	0
T14	0	3	0	0
T16	0	1	0	0
T17	0	3	0	0
T19	320124	1	0	0
T20	170808	3	0	0
T21	338564	1	0	0
T22	76038	1	0	0
T23	136236	1	0	0
T45	0	1	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2447	0	0
T1	41929	1	0	0
T2	140826	1	0	0
T3	456976	3	0	0
T4	467016	18	0	0
T5	3423488	23	0	0
T6	0	15	0	0
T7	877596	2	0	0
T8	0	2	0	0
T12	471272	6	0	0
T13	0	1	0	0
T14	0	3	0	0
T16	0	1	0	0
T17	0	3	0	0
T19	320124	1	0	0
T20	170808	3	0	0
T21	338564	1	0	0
T22	76038	1	0	0
T23	136236	1	0	0
T45	0	1	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2402	0	0
T1	41929	1	0	0
T2	140826	1	0	0
T3	456976	3	0	0
T4	467016	18	0	0
T5	3423488	23	0	0
T6	0	13	0	0
T7	877596	2	0	0
T8	0	2	0	0
T12	471272	6	0	0
T13	0	1	0	0
T14	0	3	0	0
T16	0	1	0	0
T17	0	3	0	0
T19	320124	1	0	0
T20	170808	3	0	0
T21	338564	1	0	0
T22	76038	1	0	0
T23	136236	1	0	0
T45	0	1	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2358	0	0
T1	41929	1	0	0
T2	140826	1	0	0
T3	456976	3	0	0
T4	467016	18	0	0
T5	3423488	22	0	0
T6	0	13	0	0
T7	877596	2	0	0
T8	0	2	0	0
T12	471272	6	0	0
T13	0	1	0	0
T14	0	3	0	0
T16	0	1	0	0
T17	0	3	0	0
T19	320124	1	0	0
T20	170808	3	0	0
T21	338564	1	0	0
T22	76038	1	0	0
T23	136236	1	0	0
T45	0	1	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3429	0	0
T2	281652	17	0	0
T3	456976	4	0	0
T4	467016	21	0	0
T5	3423488	19	0	0
T6	0	6	0	0
T7	877596	0	0	0
T12	471272	4	0	0
T17	0	1	0	0
T19	320124	1	0	0
T20	170808	0	0	0
T21	338564	0	0	0
T22	101384	9	0	0
T26	0	2	0	0
T31	0	3	0	0
T46	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T66	0	1	0	0
T67	0	28	0	0
T68	0	113	0	0
T69	0	2	0	0
T71	0	1	0	0
T79	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	401775	0	0
T2	281652	2901	0	0
T3	456976	210	0	0
T4	467016	1713	0	0
T5	3423488	819	0	0
T6	0	664	0	0
T7	877596	0	0	0
T12	471272	295	0	0
T17	0	42	0	0
T19	320124	39	0	0
T20	170808	0	0	0
T21	338564	0	0	0
T22	101384	1022	0	0
T26	0	4	0	0
T31	0	394	0	0
T46	0	511	0	0
T48	0	153	0	0
T49	0	122	0	0
T66	0	42	0	0
T67	0	1341	0	0
T68	0	18107	0	0
T69	0	275	0	0
T71	0	506	0	0
T79	0	139	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3134	0	0
T2	211239	16	0	0
T3	456976	4	0	0
T4	467016	16	0	0
T5	3423488	17	0	0
T6	0	4	0	0
T7	877596	0	0	0
T12	471272	2	0	0
T19	320124	1	0	0
T20	170808	0	0	0
T21	338564	0	0	0
T22	101384	8	0	0
T23	68118	0	0	0
T27	0	279	0	0
T31	0	2	0	0
T33	0	13	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T66	0	1	0	0
T67	0	28	0	0
T68	0	113	0	0
T69	0	1	0	0
T79	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	200	0	0
T2	70413	1	0	0
T3	114244	0	0	0
T4	233508	4	0	0
T5	1711744	0	0	0
T6	102533	1	0	0
T7	438798	0	0	0
T8	146021	0	0	0
T12	235636	0	0	0
T17	0	1	0	0
T19	160062	0	0	0
T20	85404	0	0	0
T21	169282	0	0	0
T22	50692	1	0	0
T23	68118	0	0	0
T27	0	1	0	0
T30	0	1	0	0
T31	0	2	0	0
T46	0	2	0	0
T47	111153	0	0	0
T48	66711	0	0	0
T49	62474	0	0	0
T53	0	1	0	0
T61	133598	0	0	0
T62	376353	0	0	0
T63	23579	0	0	0
T64	156303	0	0	0
T68	0	1	0	0
T69	0	2	0	0
T71	0	2	0	0
T75	0	1	0	0
T78	31311	0	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3876	0	0
T9	169344	1248	0	0
T10	0	655	0	0
T11	0	656	0	0
T34	0	686	0	0
T35	0	631	0	0
T36	145476	0	0	0
T37	595876	0	0	0
T38	48300	0	0	0
T39	324148	0	0	0
T40	302292	0	0	0
T41	203112	0	0	0
T42	115568	0	0	0
T43	17556	0	0	0
T44	64616	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3156	0	0
T9	169344	1008	0	0
T10	0	535	0	0
T11	0	536	0	0
T34	0	566	0	0
T35	0	511	0	0
T36	145476	0	0	0
T37	595876	0	0	0
T38	48300	0	0	0
T39	324148	0	0	0
T40	302292	0	0	0
T41	203112	0	0	0
T42	115568	0	0	0
T43	17556	0	0	0
T44	64616	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	167716	167512	0	0
T2	281652	281308	0	0
T3	456976	456956	0	0
T4	467016	466776	0	0
T5	3423488	3423448	0	0
T7	877596	877576	0	0
T12	471272	470924	0	0
T19	320124	319724	0	0
T20	170808	170596	0	0
T21	338564	338260	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	167716	167512	0	0
T2	281652	281308	0	0
T3	456976	456956	0	0
T4	467016	466776	0	0
T5	3423488	3423448	0	0
T7	877596	877576	0	0
T12	471272	470924	0	0
T19	320124	319724	0	0
T20	170808	170596	0	0
T21	338564	338260	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T12
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T4,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T19
0	1	Covered	T4,T22,T46
1	0	Covered	T5,T26,T31

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T26,T31

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T19
1	0	Not Covered
1	1	Covered	T4,T22,T46

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T4,T12,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T12
1	Covered	T4,T5,T22

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T12
1	Covered	T4,T7,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T12,T7
1	Covered	T1,T19,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T7,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T7,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T12,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T12
Phase1St	198	Covered	T1,T4,T12
Phase2St	215	Covered	T1,T4,T12
Phase3St	233	Covered	T1,T4,T12
TerminalSt	249	Covered	T1,T4,T12
TimeoutSt	159	Covered	T2,T4,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T4,T12
IdleSt->TimeoutSt	159	Covered	T2,T4,T19
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T24,T89,T90
Phase0St->Phase1St	198	Covered	T1,T4,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T30,T91,T52
Phase1St->Phase2St	215	Covered	T1,T4,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T44,T92
Phase2St->Phase3St	233	Covered	T1,T4,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T5,T33,T93
Phase3St->TerminalSt	249	Covered	T1,T4,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T12,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T4,T19
TimeoutSt->Phase0St	172	Covered	T4,T5,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T90,T94
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T30,T91,T52
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T44,T92
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T33,T93
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T12,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	658293941	218	0	0
CheckAccumTrig0_A	658293941	876	0	0
CheckAccumTrig1_A	658293941	28	0	0
CheckClr_A	658293941	435	0	0
CheckEn_A	658168769	232463522	0	0
CheckPhase0_A	658293941	945	0	0
CheckPhase1_A	658293941	923	0	0
CheckPhase2_A	658293941	908	0	0
CheckPhase3_A	658293941	891	0	0
CheckTimeout0_A	658293941	878	0	0
CheckTimeoutSt1_A	658293941	90077	0	0
CheckTimeoutSt2_A	658293941	792	0	0
CheckTimeoutStTrig_A	658293941	56	0	0
ErrorStAllEscAsserted_A	658293941	984	0	0
ErrorStIsTerminal_A	658293941	804	0	0
EscStateOut_A	658166773	658099325	0	0
u_state_regs_A	658293941	658149647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	218	0	0
T9	42336	62	0	0
T10	0	37	0	0
T11	0	36	0	0
T34	0	33	0	0
T35	0	50	0	0
T36	36369	0	0	0
T37	148969	0	0	0
T38	12075	0	0	0
T39	81037	0	0	0
T40	75573	0	0	0
T41	50778	0	0	0
T42	28892	0	0	0
T43	4389	0	0	0
T44	16154	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	876	0	0
T1	41929	1	0	0
T2	70413	0	0	0
T3	114244	0	0	0
T4	116754	4	0	0
T5	855872	10	0	0
T7	219399	1	0	0
T12	117818	1	0	0
T17	0	1	0	0
T19	80031	1	0	0
T20	42702	3	0	0
T21	84641	1	0	0
T23	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	28	0	0
T5	855872	1	0	0
T8	146021	0	0	0
T13	101876	0	0	0
T14	313826	0	0	0
T15	497813	0	0	0
T17	370348	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T26	35505	2	0	0
T27	0	1	0	0
T30	0	2	0	0
T31	0	2	0	0
T36	0	1	0	0
T44	0	1	0	0
T45	165198	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	435	0	0
T4	116754	2	0	0
T5	855872	4	0	0
T6	0	4	0	0
T7	219399	0	0	0
T8	146021	0	0	0
T12	117818	1	0	0
T18	0	1	0	0
T19	80031	0	0	0
T20	42702	3	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T26	0	3	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658168769	232463522	0	0
T1	41929	3132	0	0
T2	70413	9231	0	0
T3	114244	114239	0	0
T4	116754	129556	0	0
T5	855872	579702	0	0
T7	219399	2148	0	0
T12	117818	111599	0	0
T19	80031	3059	0	0
T20	42702	24397	0	0
T21	84641	7745	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	945	0	0
T1	41929	1	0	0
T2	70413	0	0	0
T3	114244	0	0	0
T4	116754	5	0	0
T5	855872	11	0	0
T7	219399	1	0	0
T12	117818	1	0	0
T19	80031	1	0	0
T20	42702	3	0	0
T21	84641	1	0	0
T22	0	1	0	0
T23	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	923	0	0
T1	41929	1	0	0
T2	70413	0	0	0
T3	114244	0	0	0
T4	116754	5	0	0
T5	855872	11	0	0
T7	219399	1	0	0
T12	117818	1	0	0
T19	80031	1	0	0
T20	42702	3	0	0
T21	84641	1	0	0
T22	0	1	0	0
T23	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	908	0	0
T1	41929	1	0	0
T2	70413	0	0	0
T3	114244	0	0	0
T4	116754	5	0	0
T5	855872	11	0	0
T7	219399	1	0	0
T12	117818	1	0	0
T19	80031	1	0	0
T20	42702	3	0	0
T21	84641	1	0	0
T22	0	1	0	0
T23	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	891	0	0
T1	41929	1	0	0
T2	70413	0	0	0
T3	114244	0	0	0
T4	116754	5	0	0
T5	855872	10	0	0
T7	219399	1	0	0
T12	117818	1	0	0
T19	80031	1	0	0
T20	42702	3	0	0
T21	84641	1	0	0
T22	0	1	0	0
T23	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	878	0	0
T2	70413	6	0	0
T3	114244	0	0	0
T4	116754	2	0	0
T5	855872	3	0	0
T6	0	2	0	0
T7	219399	0	0	0
T12	117818	0	0	0
T19	80031	1	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	5	0	0
T26	0	2	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	90077	0	0
T2	70413	1081	0	0
T3	114244	0	0	0
T4	116754	157	0	0
T5	855872	40	0	0
T6	0	232	0	0
T7	219399	0	0	0
T12	117818	0	0	0
T19	80031	39	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	553	0	0
T26	0	4	0	0
T46	0	325	0	0
T48	0	153	0	0
T49	0	119	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	792	0	0
T2	70413	6	0	0
T3	114244	0	0	0
T4	116754	1	0	0
T5	855872	2	0	0
T6	0	2	0	0
T7	219399	0	0	0
T12	117818	0	0	0
T19	80031	1	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	4	0	0
T48	0	1	0	0
T49	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	56	0	0
T4	116754	1	0	0
T5	855872	0	0	0
T7	219399	0	0	0
T8	146021	0	0	0
T12	117818	0	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	1	0	0
T23	68118	0	0	0
T31	0	1	0	0
T46	0	1	0	0
T68	0	1	0	0
T69	0	2	0	0
T71	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	984	0	0
T9	42336	300	0	0
T10	0	183	0	0
T11	0	168	0	0
T34	0	163	0	0
T35	0	170	0	0
T36	36369	0	0	0
T37	148969	0	0	0
T38	12075	0	0	0
T39	81037	0	0	0
T40	75573	0	0	0
T41	50778	0	0	0
T42	28892	0	0	0
T43	4389	0	0	0
T44	16154	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	804	0	0
T9	42336	240	0	0
T10	0	153	0	0
T11	0	138	0	0
T34	0	133	0	0
T35	0	140	0	0
T36	36369	0	0	0
T37	148969	0	0	0
T38	12075	0	0	0
T39	81037	0	0	0
T40	75573	0	0	0
T41	50778	0	0	0
T42	28892	0	0	0
T43	4389	0	0	0
T44	16154	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658166773	658099325	0	0
T1	41929	41878	0	0
T2	70413	70327	0	0
T3	114244	114239	0	0
T4	116754	116694	0	0
T5	855872	855862	0	0
T7	219399	219394	0	0
T12	117818	117731	0	0
T19	80031	79931	0	0
T20	42702	42649	0	0
T21	84641	84565	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	658149647	0	0
T1	41929	41878	0	0
T2	70413	70327	0	0
T3	114244	114239	0	0
T4	116754	116694	0	0
T5	855872	855862	0	0
T7	219399	219394	0	0
T12	117818	117731	0	0
T19	80031	79931	0	0
T20	42702	42649	0	0
T21	84641	84565	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T4,T5,T45
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T2,T4,T12

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T12
0	1	Covered	T6,T31,T85
1	0	Covered	T12,T5,T6

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T12,T5,T6

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T12
1	0	Not Covered
1	1	Covered	T6,T31,T85

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T12
1	Covered	T4,T17,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T12
1	Covered	T4,T5,T45

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T12,T5
1	Covered	T3,T5,T14

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T4,T12,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T5,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T6,T47

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T12

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T4,T12
Phase1St	198	Covered	T3,T4,T12
Phase2St	215	Covered	T3,T4,T12
Phase3St	233	Covered	T3,T4,T12
TerminalSt	249	Covered	T3,T4,T12
TimeoutSt	159	Covered	T2,T4,T12

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T3,T4,T12
IdleSt->TimeoutSt	159	Covered	T2,T4,T12
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T5,T6,T27
Phase0St->Phase1St	198	Covered	T3,T4,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T28,T95,T37
Phase1St->Phase2St	215	Covered	T3,T4,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T6,T31,T32
Phase2St->Phase3St	233	Covered	T3,T4,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T75,T52,T96
Phase3St->TerminalSt	249	Covered	T3,T4,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T12,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T4,T12
TimeoutSt->Phase0St	172	Covered	T12,T5,T6

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T12
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T5,T6
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T12
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T12
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T6,T27
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T28,T95,T37
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T31,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T75,T52,T96
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T12,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	658293941	186	0	0
CheckAccumTrig0_A	658293941	453	0	0
CheckAccumTrig1_A	658293941	24	0	0
CheckClr_A	658293941	210	0	0
CheckEn_A	658168769	306624049	0	0
CheckPhase0_A	658293941	511	0	0
CheckPhase1_A	658293941	499	0	0
CheckPhase2_A	658293941	486	0	0
CheckPhase3_A	658293941	479	0	0
CheckTimeout0_A	658293941	1033	0	0
CheckTimeoutSt1_A	658293941	138140	0	0
CheckTimeoutSt2_A	658293941	958	0	0
CheckTimeoutStTrig_A	658293941	50	0	0
ErrorStAllEscAsserted_A	658293941	943	0	0
ErrorStIsTerminal_A	658293941	763	0	0
EscStateOut_A	658166773	658099325	0	0
u_state_regs_A	658293941	658149647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	186	0	0
T9	42336	70	0	0
T10	0	17	0	0
T11	0	23	0	0
T34	0	49	0	0
T35	0	27	0	0
T36	36369	0	0	0
T37	148969	0	0	0
T38	12075	0	0	0
T39	81037	0	0	0
T40	75573	0	0	0
T41	50778	0	0	0
T42	28892	0	0	0
T43	4389	0	0	0
T44	16154	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	453	0	0
T3	114244	1	0	0
T4	116754	4	0	0
T5	855872	5	0	0
T6	0	15	0	0
T7	219399	0	0	0
T12	117818	3	0	0
T14	0	1	0	0
T17	0	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	24	0	0
T5	855872	1	0	0
T6	0	1	0	0
T7	219399	0	0	0
T8	146021	0	0	0
T12	117818	1	0	0
T13	101876	0	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T53	0	1	0	0
T56	0	1	0	0
T75	0	1	0	0
T86	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	210	0	0
T4	116754	2	0	0
T5	855872	3	0	0
T6	0	12	0	0
T7	219399	0	0	0
T8	146021	0	0	0
T12	117818	3	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T28	0	2	0	0
T31	0	1	0	0
T32	0	3	0	0
T61	0	1	0	0
T67	0	2	0	0
T82	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658168769	306624049	0	0
T1	41929	41877	0	0
T2	70413	17113	0	0
T3	114244	1652	0	0
T4	116754	114096	0	0
T5	855872	357650	0	0
T7	219399	217840	0	0
T12	117818	3110	0	0
T19	80031	79930	0	0
T20	42702	42648	0	0
T21	84641	78504	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	511	0	0
T3	114244	1	0	0
T4	116754	4	0	0
T5	855872	5	0	0
T6	0	15	0	0
T7	219399	0	0	0
T12	117818	4	0	0
T14	0	1	0	0
T17	0	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	499	0	0
T3	114244	1	0	0
T4	116754	4	0	0
T5	855872	5	0	0
T6	0	15	0	0
T7	219399	0	0	0
T12	117818	4	0	0
T14	0	1	0	0
T17	0	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	486	0	0
T3	114244	1	0	0
T4	116754	4	0	0
T5	855872	5	0	0
T6	0	13	0	0
T7	219399	0	0	0
T12	117818	4	0	0
T14	0	1	0	0
T17	0	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	479	0	0
T3	114244	1	0	0
T4	116754	4	0	0
T5	855872	5	0	0
T6	0	13	0	0
T7	219399	0	0	0
T12	117818	4	0	0
T14	0	1	0	0
T17	0	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	1033	0	0
T2	70413	8	0	0
T3	114244	0	0	0
T4	116754	6	0	0
T5	855872	4	0	0
T6	0	2	0	0
T7	219399	0	0	0
T12	117818	3	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	2	0	0
T66	0	1	0	0
T67	0	7	0	0
T68	0	95	0	0
T79	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	138140	0	0
T2	70413	1312	0	0
T3	114244	0	0	0
T4	116754	291	0	0
T5	855872	161	0	0
T6	0	108	0	0
T7	219399	0	0	0
T12	117818	285	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	263	0	0
T66	0	42	0	0
T67	0	273	0	0
T68	0	15939	0	0
T79	0	139	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	958	0	0
T2	70413	8	0	0
T3	114244	0	0	0
T4	116754	6	0	0
T5	855872	3	0	0
T7	219399	0	0	0
T12	117818	2	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	2	0	0
T33	0	12	0	0
T66	0	1	0	0
T67	0	7	0	0
T68	0	95	0	0
T79	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	50	0	0
T6	102533	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T42	0	1	0	0
T47	111153	0	0	0
T48	66711	0	0	0
T49	62474	0	0	0
T61	133598	0	0	0
T62	376353	0	0	0
T63	23579	0	0	0
T64	156303	0	0	0
T65	513131	0	0	0
T78	31311	0	0	0
T81	0	1	0	0
T85	0	1	0	0
T87	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	943	0	0
T9	42336	304	0	0
T10	0	150	0	0
T11	0	172	0	0
T34	0	176	0	0
T35	0	141	0	0
T36	36369	0	0	0
T37	148969	0	0	0
T38	12075	0	0	0
T39	81037	0	0	0
T40	75573	0	0	0
T41	50778	0	0	0
T42	28892	0	0	0
T43	4389	0	0	0
T44	16154	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	763	0	0
T9	42336	244	0	0
T10	0	120	0	0
T11	0	142	0	0
T34	0	146	0	0
T35	0	111	0	0
T36	36369	0	0	0
T37	148969	0	0	0
T38	12075	0	0	0
T39	81037	0	0	0
T40	75573	0	0	0
T41	50778	0	0	0
T42	28892	0	0	0
T43	4389	0	0	0
T44	16154	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658166773	658099325	0	0
T1	41929	41878	0	0
T2	70413	70327	0	0
T3	114244	114239	0	0
T4	116754	116694	0	0
T5	855872	855862	0	0
T7	219399	219394	0	0
T12	117818	117731	0	0
T19	80031	79931	0	0
T20	42702	42649	0	0
T21	84641	84565	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	658149647	0	0
T1	41929	41878	0	0
T2	70413	70327	0	0
T3	114244	114239	0	0
T4	116754	116694	0	0
T5	855872	855862	0	0
T7	219399	219394	0	0
T12	117818	117731	0	0
T19	80031	79931	0	0
T20	42702	42649	0	0
T21	84641	84565	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T25
1	1	1	Covered	T3,T4,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T4,T5,T8
1	1	0	Covered	T4,T12,T5
1	1	1	Covered	T2,T3,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T4,T17
1	0	Covered	T49,T31,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T49,T31,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T4,T17

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T4,T49,T82

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T4,T7,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T7,T5
1	Covered	T2,T3,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T4,T5,T8

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T5,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T4
Phase1St	198	Covered	T2,T3,T4
Phase2St	215	Covered	T2,T3,T4
Phase3St	233	Covered	T2,T3,T4
TerminalSt	249	Covered	T2,T3,T4
TimeoutSt	159	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T3,T4,T7
IdleSt->TimeoutSt	159	Covered	T2,T3,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T103,T104,T102
Phase0St->Phase1St	198	Covered	T2,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T29,T105,T106
Phase1St->Phase2St	215	Covered	T2,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T107,T108,T109
Phase2St->Phase3St	233	Covered	T2,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T31,T110,T109
Phase3St->TerminalSt	249	Covered	T2,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T5,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T4,T22
TimeoutSt->Phase0St	172	Covered	T2,T4,T17

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T17
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T103,T111,T112
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T105,T106
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T107,T108,T109
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T31,T110,T109
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T31,T71
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	658293941	184	0	0
CheckAccumTrig0_A	658293941	463	0	0
CheckAccumTrig1_A	658293941	15	0	0
CheckClr_A	658293941	174	0	0
CheckEn_A	658168769	308037139	0	0
CheckPhase0_A	658293941	510	0	0
CheckPhase1_A	658293941	501	0	0
CheckPhase2_A	658293941	496	0	0
CheckPhase3_A	658293941	490	0	0
CheckTimeout0_A	658293941	617	0	0
CheckTimeoutSt1_A	658293941	83897	0	0
CheckTimeoutSt2_A	658293941	560	0	0
CheckTimeoutStTrig_A	658293941	40	0	0
ErrorStAllEscAsserted_A	658293941	962	0	0
ErrorStIsTerminal_A	658293941	782	0	0
EscStateOut_A	658166773	658099325	0	0
u_state_regs_A	658293941	658149647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	184	0	0
T9	42336	67	0	0
T10	0	26	0	0
T11	0	35	0	0
T34	0	27	0	0
T35	0	29	0	0
T36	36369	0	0	0
T37	148969	0	0	0
T38	12075	0	0	0
T39	81037	0	0	0
T40	75573	0	0	0
T41	50778	0	0	0
T42	28892	0	0	0
T43	4389	0	0	0
T44	16154	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	463	0	0
T3	114244	1	0	0
T4	116754	4	0	0
T5	855872	3	0	0
T6	0	5	0	0
T7	219399	1	0	0
T8	0	1	0	0
T12	117818	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	15	0	0
T31	0	2	0	0
T49	62474	1	0	0
T50	0	1	0	0
T53	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	133598	0	0	0
T62	376353	0	0	0
T63	23579	0	0	0
T64	156303	0	0	0
T65	513131	0	0	0
T66	122252	0	0	0
T67	151142	0	0	0
T68	355203	0	0	0
T69	54111	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	174	0	0
T4	116754	3	0	0
T5	855872	0	0	0
T7	219399	0	0	0
T8	146021	0	0	0
T12	117818	0	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T29	0	2	0	0
T31	0	2	0	0
T50	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658168769	308037139	0	0
T1	41929	41877	0	0
T2	70413	2064	0	0
T3	114244	3069	0	0
T4	116754	85894	0	0
T5	855872	770538	0	0
T7	219399	2160	0	0
T12	117818	117730	0	0
T19	80031	79930	0	0
T20	42702	42648	0	0
T21	84641	7761	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	510	0	0
T2	70413	1	0	0
T3	114244	1	0	0
T4	116754	7	0	0
T5	855872	3	0	0
T7	219399	1	0	0
T8	0	1	0	0
T12	117818	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T17	0	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	501	0	0
T2	70413	1	0	0
T3	114244	1	0	0
T4	116754	7	0	0
T5	855872	3	0	0
T7	219399	1	0	0
T8	0	1	0	0
T12	117818	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T17	0	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T46	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	496	0	0
T2	70413	1	0	0
T3	114244	1	0	0
T4	116754	7	0	0
T5	855872	3	0	0
T7	219399	1	0	0
T8	0	1	0	0
T12	117818	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T17	0	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T46	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	490	0	0
T2	70413	1	0	0
T3	114244	1	0	0
T4	116754	7	0	0
T5	855872	3	0	0
T7	219399	1	0	0
T8	0	1	0	0
T12	117818	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T17	0	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T46	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	617	0	0
T2	70413	1	0	0
T3	114244	4	0	0
T4	116754	8	0	0
T5	855872	0	0	0
T7	219399	0	0	0
T12	117818	0	0	0
T17	0	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	2	0	0
T46	0	1	0	0
T49	0	1	0	0
T67	0	10	0	0
T68	0	8	0	0
T69	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	83897	0	0
T2	70413	162	0	0
T3	114244	210	0	0
T4	116754	890	0	0
T5	855872	0	0	0
T7	219399	0	0	0
T12	117818	0	0	0
T17	0	42	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	206	0	0
T46	0	186	0	0
T49	0	3	0	0
T67	0	537	0	0
T68	0	618	0	0
T69	0	262	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	560	0	0
T3	114244	4	0	0
T4	116754	5	0	0
T5	855872	0	0	0
T7	219399	0	0	0
T12	117818	0	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	2	0	0
T23	68118	0	0	0
T27	0	101	0	0
T31	0	1	0	0
T33	0	1	0	0
T50	0	1	0	0
T67	0	10	0	0
T68	0	8	0	0
T69	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	40	0	0
T2	70413	1	0	0
T3	114244	0	0	0
T4	116754	3	0	0
T5	855872	0	0	0
T7	219399	0	0	0
T12	117818	0	0	0
T17	0	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T27	0	1	0	0
T46	0	1	0	0
T53	0	1	0	0
T75	0	1	0	0
T82	0	1	0	0
T86	0	1	0	0
T88	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	962	0	0
T9	42336	321	0	0
T10	0	160	0	0
T11	0	154	0	0
T34	0	168	0	0
T35	0	159	0	0
T36	36369	0	0	0
T37	148969	0	0	0
T38	12075	0	0	0
T39	81037	0	0	0
T40	75573	0	0	0
T41	50778	0	0	0
T42	28892	0	0	0
T43	4389	0	0	0
T44	16154	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	782	0	0
T9	42336	261	0	0
T10	0	130	0	0
T11	0	124	0	0
T34	0	138	0	0
T35	0	129	0	0
T36	36369	0	0	0
T37	148969	0	0	0
T38	12075	0	0	0
T39	81037	0	0	0
T40	75573	0	0	0
T41	50778	0	0	0
T42	28892	0	0	0
T43	4389	0	0	0
T44	16154	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658166773	658099325	0	0
T1	41929	41878	0	0
T2	70413	70327	0	0
T3	114244	114239	0	0
T4	116754	116694	0	0
T5	855872	855862	0	0
T7	219399	219394	0	0
T12	117818	117731	0	0
T19	80031	79931	0	0
T20	42702	42649	0	0
T21	84641	84565	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	658149647	0	0
T1	41929	41878	0	0
T2	70413	70327	0	0
T3	114244	114239	0	0
T4	116754	116694	0	0
T5	855872	855862	0	0
T7	219399	219394	0	0
T12	117818	117731	0	0
T19	80031	79931	0	0
T20	42702	42649	0	0
T21	84641	84565	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T24
1	1	1	Covered	T3,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T12
1	0	1	Covered	T4,T8,T14
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T2,T4,T12

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T12
0	1	Covered	T4,T68,T69
1	0	Covered	T12,T67,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T12,T67,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T12
1	0	Not Covered
1	1	Covered	T4,T68,T69

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T12
1	Covered	T4,T5,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T12
1	Covered	T5,T8,T16

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T12
1	Covered	T4,T5,T14

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T3,T12,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T12,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T12,T5,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T5,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T12

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T4,T12
Phase1St	198	Covered	T3,T4,T12
Phase2St	215	Covered	T3,T4,T12
Phase3St	233	Covered	T3,T4,T12
TerminalSt	249	Covered	T3,T4,T12
TimeoutSt	159	Covered	T2,T4,T12

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T3,T4,T5
IdleSt->TimeoutSt	159	Covered	T2,T4,T12
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T31,T80,T113
Phase0St->Phase1St	198	Covered	T3,T4,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T30,T80,T53
Phase1St->Phase2St	215	Covered	T3,T4,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T33,T52,T54
Phase2St->Phase3St	233	Covered	T3,T4,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T95,T24,T114
Phase3St->TerminalSt	249	Covered	T3,T4,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T5,T16
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T4,T5
TimeoutSt->Phase0St	172	Covered	T4,T12,T67

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T12
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T67
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T12
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T80,T113,T115
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T80,T53,T116
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T33,T52,T54
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T95,T24,T114
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T16,T6,T68
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	658293941	151	0	0
CheckAccumTrig0_A	658293941	460	0	0
CheckAccumTrig1_A	658293941	22	0	0
CheckClr_A	658293941	189	0	0
CheckEn_A	658168769	314634913	0	0
CheckPhase0_A	658293941	532	0	0
CheckPhase1_A	658293941	524	0	0
CheckPhase2_A	658293941	512	0	0
CheckPhase3_A	658293941	498	0	0
CheckTimeout0_A	658293941	901	0	0
CheckTimeoutSt1_A	658293941	89661	0	0
CheckTimeoutSt2_A	658293941	824	0	0
CheckTimeoutStTrig_A	658293941	54	0	0
ErrorStAllEscAsserted_A	658293941	987	0	0
ErrorStIsTerminal_A	658293941	807	0	0
EscStateOut_A	658166773	658099325	0	0
u_state_regs_A	658293941	658149647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	151	0	0
T9	42336	56	0	0
T10	0	11	0	0
T11	0	32	0	0
T34	0	20	0	0
T35	0	32	0	0
T36	36369	0	0	0
T37	148969	0	0	0
T38	12075	0	0	0
T39	81037	0	0	0
T40	75573	0	0	0
T41	50778	0	0	0
T42	28892	0	0	0
T43	4389	0	0	0
T44	16154	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	460	0	0
T3	114244	1	0	0
T4	116754	1	0	0
T5	855872	4	0	0
T6	0	3	0	0
T7	219399	0	0	0
T8	0	1	0	0
T12	117818	0	0	0
T14	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	22	0	0
T5	855872	0	0	0
T7	219399	0	0	0
T8	146021	0	0	0
T12	117818	1	0	0
T13	101876	0	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T37	0	1	0	0
T50	0	1	0	0
T53	0	1	0	0
T67	0	1	0	0
T80	0	2	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	189	0	0
T6	102533	1	0	0
T16	371153	1	0	0
T18	142985	0	0	0
T28	0	1	0	0
T31	0	1	0	0
T33	0	3	0	0
T46	10614	0	0	0
T47	111153	0	0	0
T48	66711	0	0	0
T49	62474	0	0	0
T50	0	1	0	0
T61	133598	0	0	0
T68	0	1	0	0
T72	0	2	0	0
T77	86818	0	0	0
T78	31311	0	0	0
T121	0	1	0	0
T122	0	6	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658168769	314634913	0	0
T1	41929	41877	0	0
T2	70413	63124	0	0
T3	114244	594	0	0
T4	116754	81347	0	0
T5	855872	313648	0	0
T7	219399	7471	0	0
T12	117818	3137	0	0
T19	80031	79930	0	0
T20	42702	42648	0	0
T21	84641	78765	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	532	0	0
T3	114244	1	0	0
T4	116754	2	0	0
T5	855872	4	0	0
T7	219399	0	0	0
T8	0	1	0	0
T12	117818	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	524	0	0
T3	114244	1	0	0
T4	116754	2	0	0
T5	855872	4	0	0
T7	219399	0	0	0
T8	0	1	0	0
T12	117818	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T46	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	512	0	0
T3	114244	1	0	0
T4	116754	2	0	0
T5	855872	4	0	0
T7	219399	0	0	0
T8	0	1	0	0
T12	117818	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T46	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	498	0	0
T3	114244	1	0	0
T4	116754	2	0	0
T5	855872	4	0	0
T7	219399	0	0	0
T8	0	1	0	0
T12	117818	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T46	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	901	0	0
T2	70413	2	0	0
T3	114244	0	0	0
T4	116754	5	0	0
T5	855872	12	0	0
T6	0	2	0	0
T7	219399	0	0	0
T12	117818	1	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T31	0	3	0	0
T67	0	11	0	0
T68	0	10	0	0
T69	0	1	0	0
T71	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	89661	0	0
T2	70413	346	0	0
T3	114244	0	0	0
T4	116754	375	0	0
T5	855872	618	0	0
T6	0	324	0	0
T7	219399	0	0	0
T12	117818	10	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T31	0	394	0	0
T67	0	531	0	0
T68	0	1550	0	0
T69	0	13	0	0
T71	0	506	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	824	0	0
T2	70413	2	0	0
T3	114244	0	0	0
T4	116754	4	0	0
T5	855872	12	0	0
T6	0	2	0	0
T7	219399	0	0	0
T12	117818	0	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T27	0	178	0	0
T31	0	1	0	0
T67	0	10	0	0
T68	0	9	0	0
T80	0	3	0	0
T81	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	54	0	0
T4	116754	1	0	0
T5	855872	0	0	0
T7	219399	0	0	0
T8	146021	0	0	0
T12	117818	0	0	0
T19	80031	0	0	0
T20	42702	0	0	0
T21	84641	0	0	0
T22	25346	0	0	0
T23	68118	0	0	0
T31	0	2	0	0
T33	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T71	0	1	0	0
T86	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	987	0	0
T9	42336	323	0	0
T10	0	162	0	0
T11	0	162	0	0
T34	0	179	0	0
T35	0	161	0	0
T36	36369	0	0	0
T37	148969	0	0	0
T38	12075	0	0	0
T39	81037	0	0	0
T40	75573	0	0	0
T41	50778	0	0	0
T42	28892	0	0	0
T43	4389	0	0	0
T44	16154	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	807	0	0
T9	42336	263	0	0
T10	0	132	0	0
T11	0	132	0	0
T34	0	149	0	0
T35	0	131	0	0
T36	36369	0	0	0
T37	148969	0	0	0
T38	12075	0	0	0
T39	81037	0	0	0
T40	75573	0	0	0
T41	50778	0	0	0
T42	28892	0	0	0
T43	4389	0	0	0
T44	16154	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658166773	658099325	0	0
T1	41929	41878	0	0
T2	70413	70327	0	0
T3	114244	114239	0	0
T4	116754	116694	0	0
T5	855872	855862	0	0
T7	219399	219394	0	0
T12	117818	117731	0	0
T19	80031	79931	0	0
T20	42702	42649	0	0
T21	84641	84565	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658293941	658149647	0	0
T1	41929	41878	0	0
T2	70413	70327	0	0
T3	114244	114239	0	0
T4	116754	116694	0	0
T5	855872	855862	0	0
T7	219399	219394	0	0
T12	117818	117731	0	0
T19	80031	79931	0	0
T20	42702	42649	0	0
T21	84641	84565	0	0