Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66046689	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32234205

1

T1

115815

T2

943

T3

83834

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14815796	1			T1	44827		T2	400		T3	33910
values[0x0]	40525240	1			T1	160634		T2	1279		T3	116547
values[0x1]	42939858	1			T1	160602		T2	1285		T3	115515

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56182822	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

42098072

1

T1

146045

T2

1190

T3

106004

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	324078	1			T1	1430		T2	8		T3	1139
valid_sources[0x01]	315469	1			T1	1434		T3	1020		T12	12
valid_sources[0x02]	304270	1			T1	1342		T3	1072		T12	10
valid_sources[0x03]	317801	1			T1	1559		T2	16		T3	960
valid_sources[0x04]	618305	1			T1	1350		T2	18		T3	1045
valid_sources[0x05]	314410	1			T1	1393		T2	21		T3	1131
valid_sources[0x06]	316057	1			T1	1488		T3	1003		T12	26
valid_sources[0x07]	654890	1			T1	1436		T3	1013		T12	11
valid_sources[0x08]	315712	1			T1	1343		T2	10		T3	1193
valid_sources[0x09]	692503	1			T1	1610		T3	1142		T12	29
valid_sources[0x0a]	305116	1			T1	1619		T2	11		T3	798
valid_sources[0x0b]	666104	1			T1	1506		T2	17		T3	1113
valid_sources[0x0c]	732818	1			T1	1277		T3	975		T12	19
valid_sources[0x0d]	334373	1			T1	1376		T2	37		T3	966
valid_sources[0x0e]	313760	1			T1	1473		T3	961		T12	15
valid_sources[0x0f]	747743	1			T1	1553		T2	18		T3	1138
valid_sources[0x10]	312175	1			T1	1576		T2	18		T3	1088
valid_sources[0x11]	320664	1			T1	1295		T3	907		T12	21
valid_sources[0x12]	323474	1			T1	1591		T2	14		T3	944
valid_sources[0x13]	307865	1			T1	1295		T2	14		T3	1019
valid_sources[0x14]	754763	1			T1	1458		T2	19		T3	1128
valid_sources[0x15]	311062	1			T1	1281		T2	17		T3	1243
valid_sources[0x16]	323047	1			T1	1418		T2	17		T3	1061
valid_sources[0x17]	323944	1			T1	1385		T3	958		T12	20
valid_sources[0x18]	317104	1			T1	1417		T2	44		T3	901
valid_sources[0x19]	311751	1			T1	1389		T2	43		T3	1134
valid_sources[0x1a]	743137	1			T1	1448		T3	1003		T12	26
valid_sources[0x1b]	317088	1			T1	1554		T2	37		T3	948
valid_sources[0x1c]	311959	1			T1	1398		T2	11		T3	1055
valid_sources[0x1d]	313530	1			T1	1415		T2	28		T3	984
valid_sources[0x1e]	309648	1			T1	1462		T2	5		T3	1032
valid_sources[0x1f]	306036	1			T1	1594		T2	12		T3	948
valid_sources[0x20]	309347	1			T1	1478		T2	20		T3	1128
valid_sources[0x21]	324981	1			T1	1273		T2	4		T3	1075
valid_sources[0x22]	313854	1			T1	1407		T2	3		T3	1183
valid_sources[0x23]	318259	1			T1	1206		T2	42		T3	979
valid_sources[0x24]	343851	1			T1	1436		T3	1091		T12	19
valid_sources[0x25]	321576	1			T1	1557		T2	5		T3	1156
valid_sources[0x26]	316580	1			T1	1643		T2	35		T3	857
valid_sources[0x27]	326785	1			T1	1323		T3	1262		T12	17
valid_sources[0x28]	825129	1			T1	1345		T2	16		T3	1049
valid_sources[0x29]	327251	1			T1	1479		T2	20		T3	989
valid_sources[0x2a]	631351	1			T1	1288		T3	874		T12	15
valid_sources[0x2b]	304417	1			T1	1558		T2	10		T3	1081
valid_sources[0x2c]	313263	1			T1	1430		T3	906		T12	7
valid_sources[0x2d]	330559	1			T1	1417		T2	43		T3	972
valid_sources[0x2e]	315667	1			T1	1491		T3	1010		T12	13
valid_sources[0x2f]	358183	1			T1	1335		T2	3		T3	967
valid_sources[0x30]	324501	1			T1	1472		T3	1049		T12	25
valid_sources[0x31]	316657	1			T1	1470		T3	951		T12	16
valid_sources[0x32]	308824	1			T1	1575		T2	1		T3	1036
valid_sources[0x33]	305855	1			T1	1458		T2	7		T3	1195
valid_sources[0x34]	370407	1			T1	1382		T3	1052		T12	27
valid_sources[0x35]	673801	1			T1	1447		T3	1123		T12	19
valid_sources[0x36]	314420	1			T1	1486		T2	4		T3	915
valid_sources[0x37]	321859	1			T1	1510		T3	1074		T12	24
valid_sources[0x38]	326574	1			T1	1346		T3	1010		T12	19
valid_sources[0x39]	309825	1			T1	1434		T3	1130		T12	37
valid_sources[0x3a]	319582	1			T1	1415		T3	1006		T12	14
valid_sources[0x3b]	312495	1			T1	1459		T3	1059		T12	41
valid_sources[0x3c]	310252	1			T1	1413		T2	10		T3	1090
valid_sources[0x3d]	316524	1			T1	1272		T2	2		T3	1038
valid_sources[0x3e]	313259	1			T1	1439		T3	905		T12	19
valid_sources[0x3f]	329220	1			T1	1498		T2	45		T3	1205
valid_sources[0x40]	732061	1			T1	1406		T3	1078		T12	20
valid_sources[0x41]	310243	1			T1	1520		T2	6		T3	1130
valid_sources[0x42]	537885	1			T1	1529		T3	1103		T12	17
valid_sources[0x43]	315237	1			T1	1485		T2	3		T3	938
valid_sources[0x44]	753840	1			T1	1515		T3	1039		T12	35
valid_sources[0x45]	306543	1			T1	1524		T2	1		T3	968
valid_sources[0x46]	319834	1			T1	1490		T3	1137		T12	37
valid_sources[0x47]	304637	1			T1	1436		T2	2		T3	1119
valid_sources[0x48]	830406	1			T1	1535		T2	56		T3	1135
valid_sources[0x49]	309514	1			T1	1478		T2	13		T3	902
valid_sources[0x4a]	970903	1			T1	1531		T2	5		T3	1108
valid_sources[0x4b]	306880	1			T1	1485		T2	24		T3	970
valid_sources[0x4c]	394910	1			T1	1292		T2	3		T3	977
valid_sources[0x4d]	313082	1			T1	1255		T2	6		T3	1070
valid_sources[0x4e]	310393	1			T1	1457		T3	889		T12	11
valid_sources[0x4f]	324488	1			T1	1547		T2	25		T3	1223
valid_sources[0x50]	311907	1			T1	1698		T3	1054		T12	33
valid_sources[0x51]	310587	1			T1	1427		T2	16		T3	991
valid_sources[0x52]	311992	1			T1	1321		T2	5		T3	1149
valid_sources[0x53]	317826	1			T1	1578		T2	9		T3	1076
valid_sources[0x54]	303239	1			T1	1295		T2	11		T3	1095
valid_sources[0x55]	306422	1			T1	1449		T2	10		T3	818
valid_sources[0x56]	316603	1			T1	1384		T2	17		T3	911
valid_sources[0x57]	309507	1			T1	1421		T2	18		T3	952
valid_sources[0x58]	633132	1			T1	1476		T2	3		T3	1040
valid_sources[0x59]	310259	1			T1	1395		T2	42		T3	1112
valid_sources[0x5a]	310375	1			T1	1574		T2	38		T3	865
valid_sources[0x5b]	320273	1			T1	1306		T3	967		T12	30
valid_sources[0x5c]	313823	1			T1	1373		T3	1008		T12	30
valid_sources[0x5d]	340083	1			T1	1314		T2	8		T3	1018
valid_sources[0x5e]	330061	1			T1	1423		T2	38		T3	970
valid_sources[0x5f]	316121	1			T1	1331		T3	976		T12	20
valid_sources[0x60]	316151	1			T1	1379		T2	58		T3	916
valid_sources[0x61]	585733	1			T1	1524		T3	1048		T12	12
valid_sources[0x62]	313007	1			T1	1260		T3	1024		T12	16
valid_sources[0x63]	327625	1			T1	1419		T2	3		T3	1001
valid_sources[0x64]	304855	1			T1	1647		T3	1035		T12	23
valid_sources[0x65]	324000	1			T1	1488		T2	8		T3	1127
valid_sources[0x66]	313633	1			T1	1436		T2	47		T3	1102
valid_sources[0x67]	727100	1			T1	1445		T3	1052		T12	16
valid_sources[0x68]	387387	1			T1	1499		T2	28		T3	951
valid_sources[0x69]	327264	1			T1	1453		T2	10		T3	1171
valid_sources[0x6a]	312416	1			T1	1469		T2	3		T3	974
valid_sources[0x6b]	329870	1			T1	1245		T2	9		T3	972
valid_sources[0x6c]	694257	1			T1	1397		T2	34		T3	1211
valid_sources[0x6d]	323565	1			T1	1350		T2	10		T3	1057
valid_sources[0x6e]	312861	1			T1	1604		T2	19		T3	996
valid_sources[0x6f]	308407	1			T1	1555		T2	2		T3	1067
valid_sources[0x70]	321160	1			T1	1345		T2	15		T3	1121
valid_sources[0x71]	320410	1			T1	1556		T2	6		T3	981
valid_sources[0x72]	318510	1			T1	1347		T2	21		T3	1021
valid_sources[0x73]	310979	1			T1	1462		T3	1036		T12	28
valid_sources[0x74]	318909	1			T1	1372		T3	974		T12	34
valid_sources[0x75]	316653	1			T1	1366		T2	35		T3	979
valid_sources[0x76]	322669	1			T1	1418		T2	17		T3	1076
valid_sources[0x77]	365524	1			T1	1415		T2	23		T3	1135
valid_sources[0x78]	1191550	1			T1	1265		T2	12		T3	956
valid_sources[0x79]	302979	1			T1	1563		T2	4		T3	1156
valid_sources[0x7a]	324213	1			T1	1297		T2	15		T3	1001
valid_sources[0x7b]	320204	1			T1	1431		T3	1043		T12	25
valid_sources[0x7c]	312945	1			T1	1532		T2	7		T3	1040
valid_sources[0x7d]	315045	1			T1	1445		T2	27		T3	1087
valid_sources[0x7e]	1073600	1			T1	1525		T3	871		T12	16
valid_sources[0x7f]	324984	1			T1	1595		T3	1023		T12	2
valid_sources[0x80]	331123	1			T1	1511		T2	31		T3	1157

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7433984

1

T1

22320

T2

186

T3

16903

values[0x0]

all_enables

biggest_size

15615374

1

T1

59546

T2

466

T3

43174

values[0x1]

all_enables

biggest_size

9184847

1

T1

33949

T2

291

T3

23757