Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T208,T209,T210
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T7

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15301	0	0
DisabledNoTrigBkwd_A	2147483647	743376	0	0
DisabledNoTrigFwd_A	2147483647	1632799694	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15301	0	0
T29	113127	0	0	0
T44	258710	0	0	0
T46	18414	0	0	0
T64	14575	0	0	0
T65	44970	0	0	0
T66	11774	0	0	0
T67	152698	0	0	0
T126	122354	0	0	0
T129	671354	0	0	0
T208	1641	666	0	0
T209	3550	935	0	0
T210	0	182	0	0
T211	0	1455	0	0
T212	0	528	0	0
T213	0	697	0	0
T214	0	570	0	0
T215	3188	777	0	0
T216	0	379	0	0
T217	0	607	0	0
T218	0	1586	0	0
T219	0	1580	0	0
T220	0	610	0	0
T221	0	594	0	0
T222	0	414	0	0
T223	0	782	0	0
T224	0	1106	0	0
T225	0	363	0	0
T226	0	679	0	0
T227	0	791	0	0
T228	369834	0	0	0
T229	26846	0	0	0
T230	12461	0	0	0
T231	6210	0	0	0
T232	400640	0	0	0
T233	117699	0	0	0
T234	90341	0	0	0
T235	232851	0	0	0
T236	219314	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	743376	0	0
T1	957668	1321	0	0
T2	21046	0	0	0
T3	1801310	272	0	0
T4	474356	2408	0	0
T5	394010	1962	0	0
T6	0	480	0	0
T7	1857636	1195	0	0
T11	1171748	244	0	0
T12	250560	2	0	0
T16	831804	3088	0	0
T17	1736368	1195	0	0
T18	734590	1008	0	0
T19	0	3456	0	0
T20	0	17311	0	0
T21	319732	40	0	0
T22	67836	2	0	0
T25	0	333	0	0
T26	0	53	0	0
T41	0	752	0	0
T42	0	24	0	0
T43	0	1	0	0
T44	0	15	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1632799694	0	0
T1	1915336	1000395	0	0
T2	42092	12396	0	0
T3	3602620	2697473	0	0
T4	474356	2192317	0	0
T7	1857636	1008112	0	0
T11	1171748	582460	0	0
T12	250560	211417	0	0
T16	831804	624345	0	0
T21	319732	242654	0	0
T22	67836	59158	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T215,T217,T218
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	705589305	5643	0	0
DisabledNoTrigBkwd_A	705589305	204964	0	0
DisabledNoTrigFwd_A	705589305	353444186	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	5643	0	0
T126	122354	0	0	0
T129	671354	0	0	0
T215	3188	777	0	0
T217	0	607	0	0
T218	0	1586	0	0
T219	0	1580	0	0
T222	0	414	0	0
T226	0	679	0	0
T230	12461	0	0	0
T231	6210	0	0	0
T232	400640	0	0	0
T233	117699	0	0	0
T234	90341	0	0	0
T235	232851	0	0	0
T236	219314	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	204964	0	0
T1	478834	942	0	0
T2	10523	0	0	0
T3	900655	272	0	0
T4	118589	384	0	0
T5	0	573	0	0
T7	464409	0	0	0
T11	292937	111	0	0
T12	62640	2	0	0
T16	207951	3085	0	0
T17	0	1195	0	0
T21	79933	40	0	0
T22	16959	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	353444186	0	0
T1	478834	27248	0	0
T2	10523	1579	0	0
T3	900655	582	0	0
T4	118589	842930	0	0
T7	464409	54148	0	0
T11	292937	5662	0	0
T12	62640	23728	0	0
T16	207951	2040	0	0
T21	79933	3083	0	0
T22	16959	13998	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T208,T211,T220
1	1	Covered	T2,T7,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T11,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	705589305	3522	0	0
DisabledNoTrigBkwd_A	705589305	193392	0	0
DisabledNoTrigFwd_A	705589305	409362187	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	3522	0	0
T29	113127	0	0	0
T44	258710	0	0	0
T46	18414	0	0	0
T64	14575	0	0	0
T65	44970	0	0	0
T66	11774	0	0	0
T67	152698	0	0	0
T208	1641	666	0	0
T211	0	1455	0	0
T220	0	610	0	0
T227	0	791	0	0
T228	369834	0	0	0
T229	26846	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	193392	0	0
T4	118589	1100	0	0
T5	197005	10	0	0
T6	0	263	0	0
T7	464409	1189	0	0
T11	292937	133	0	0
T12	62640	0	0	0
T16	207951	3	0	0
T17	868184	0	0	0
T18	367295	991	0	0
T20	0	11742	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T26	0	44	0	0
T41	0	752	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	409362187	0	0
T1	478834	478075	0	0
T2	10523	1753	0	0
T3	900655	900570	0	0
T4	118589	614944	0	0
T7	464409	28064	0	0
T11	292937	12722	0	0
T12	62640	62563	0	0
T16	207951	206991	0	0
T21	79933	79857	0	0
T22	16959	16903	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T209,T210,T212
1	1	Covered	T1,T2,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	705589305	4087	0	0
DisabledNoTrigBkwd_A	705589305	182119	0	0
DisabledNoTrigFwd_A	705589305	451093985	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	4087	0	0
T23	133980	0	0	0
T53	25105	0	0	0
T209	3550	935	0	0
T210	889	182	0	0
T212	0	528	0	0
T216	0	379	0	0
T221	0	594	0	0
T224	0	1106	0	0
T225	0	363	0	0
T237	238976	0	0	0
T238	118172	0	0	0
T239	507917	0	0	0
T240	40582	0	0	0
T241	428925	0	0	0
T242	14206	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	182119	0	0
T1	478834	379	0	0
T2	10523	0	0	0
T3	900655	0	0	0
T4	118589	14	0	0
T5	0	612	0	0
T7	464409	5	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T18	0	5	0	0
T19	0	1841	0	0
T20	0	1020	0	0
T21	79933	0	0	0
T22	16959	1	0	0
T25	0	333	0	0
T26	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	451093985	0	0
T1	478834	16995	0	0
T2	10523	6341	0	0
T3	900655	900570	0	0
T4	118589	118314	0	0
T7	464409	461976	0	0
T11	292937	282006	0	0
T12	62640	62563	0	0
T16	207951	207369	0	0
T21	79933	79857	0	0
T22	16959	11354	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T213,T214,T223
1	1	Covered	T2,T7,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	705589305	2049	0	0
DisabledNoTrigBkwd_A	705589305	162901	0	0
DisabledNoTrigFwd_A	705589305	418899336	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	2049	0	0
T101	75522	0	0	0
T102	116797	0	0	0
T213	1438	697	0	0
T214	1293	570	0	0
T223	0	782	0	0
T243	131171	0	0	0
T244	14957	0	0	0
T245	32732	0	0	0
T246	24969	0	0	0
T247	127100	0	0	0
T248	52322	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	162901	0	0
T4	118589	910	0	0
T5	197005	767	0	0
T6	0	217	0	0
T7	464409	1	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T17	868184	0	0	0
T18	367295	12	0	0
T19	0	1615	0	0
T20	0	4549	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T42	0	24	0	0
T43	0	1	0	0
T44	0	15	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	418899336	0	0
T1	478834	478077	0	0
T2	10523	2723	0	0
T3	900655	895751	0	0
T4	118589	616129	0	0
T7	464409	463924	0	0
T11	292937	282070	0	0
T12	62640	62563	0	0
T16	207951	207945	0	0
T21	79933	79857	0	0
T22	16959	16903	0	0