Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T23,T24
1	1	1	Covered	T1,T3,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T12,T4
1	0	1	Covered	T1,T7,T11
1	1	0	Covered	T2,T12,T4
1	1	1	Covered	T2,T4,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T16
0	1	Covered	T5,T19,T25
1	0	Covered	T26,T19,T6

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T16
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T26,T19,T6

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T16
1	0	Not Covered
1	1	Covered	T5,T19,T25

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T12,T11,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T12
1	Covered	T3,T12,T11

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T11
1	Covered	T1,T7,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T11,T4,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T7,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T7,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T12,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T7,T12

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T7
Phase1St	198	Covered	T1,T3,T7
Phase2St	215	Covered	T1,T3,T7
Phase3St	233	Covered	T1,T3,T7
TerminalSt	249	Covered	T1,T3,T7
TimeoutSt	159	Covered	T2,T4,T16

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T3,T7
IdleSt->TimeoutSt	159	Covered	T2,T4,T16
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T16,T19,T27
Phase0St->Phase1St	198	Covered	T1,T3,T7
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T4,T6,T28
Phase1St->Phase2St	215	Covered	T1,T3,T7
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T12,T19,T29
Phase2St->Phase3St	233	Covered	T1,T3,T7
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T5,T19,T30
Phase3St->TerminalSt	249	Covered	T1,T3,T7
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T3,T12,T11
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T4,T16
TimeoutSt->Phase0St	172	Covered	T5,T26,T19

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T26,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T16
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T16,T19,T27
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T6,T28
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T12,T19,T29
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T19,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T12,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	854	0	0
CheckAccumTrig0_A	2147483647	2451	0	0
CheckAccumTrig1_A	2147483647	133	0	0
CheckClr_A	2147483647	1157	0	0
CheckEn_A	2147483647	1238308436	0	0
CheckPhase0_A	2147483647	2787	0	0
CheckPhase1_A	2147483647	2730	0	0
CheckPhase2_A	2147483647	2669	0	0
CheckPhase3_A	2147483647	2620	0	0
CheckTimeout0_A	2147483647	4409	0	0
CheckTimeoutSt1_A	2147483647	437169	0	0
CheckTimeoutSt2_A	2147483647	4013	0	0
CheckTimeoutStTrig_A	2147483647	252	0	0
ErrorStAllEscAsserted_A	2147483647	4558	0	0
ErrorStIsTerminal_A	2147483647	3718	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	854	0	0
T8	371604	123	0	0
T9	0	235	0	0
T10	0	127	0	0
T15	2389612	0	0	0
T31	0	235	0	0
T32	0	134	0	0
T33	151272	0	0	0
T34	114808	0	0	0
T35	297136	0	0	0
T36	3359708	0	0	0
T37	35608	0	0	0
T38	57544	0	0	0
T39	38104	0	0	0
T40	2028560	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2451	0	0
T1	957668	2	0	0
T2	21046	0	0	0
T3	1801310	9	0	0
T4	474356	12	0	0
T5	394010	22	0	0
T6	0	12	0	0
T7	1857636	3	0	0
T11	1171748	3	0	0
T12	250560	2	0	0
T16	831804	2	0	0
T17	1736368	1	0	0
T18	734590	4	0	0
T19	0	1	0	0
T20	0	3	0	0
T21	319732	4	0	0
T22	67836	2	0	0
T25	0	1	0	0
T26	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	133	0	0
T6	985119	3	0	0
T19	115119	1	0	0
T20	108024	0	0	0
T25	72643	0	0	0
T26	27842	1	0	0
T29	113127	0	0	0
T30	447012	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T43	0	1	0	0
T44	258710	0	0	0
T45	0	1	0	0
T46	18414	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	12583	0	0	0
T60	10287	0	0	0
T61	8988	0	0	0
T62	11209	0	0	0
T63	238701	0	0	0
T64	14575	0	0	0
T65	44970	0	0	0
T66	11774	0	0	0
T67	152698	0	0	0
T68	24804	0	0	0
T69	33602	0	0	0
T70	308915	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1157	0	0
T3	900655	8	0	0
T4	355767	3	0	0
T5	788020	3	0	0
T6	0	6	0	0
T7	464409	0	0	0
T11	585874	1	0	0
T12	62640	2	0	0
T16	623853	1	0	0
T17	3472736	0	0	0
T18	1101885	1	0	0
T19	115119	6	0	0
T21	239799	3	0	0
T22	50877	1	0	0
T25	72643	2	0	0
T26	55684	1	0	0
T27	0	1	0	0
T29	0	1	0	0
T59	12583	0	0	0
T60	10287	0	0	0
T71	116667	1	0	0
T72	270993	4	0	0
T73	0	9	0	0
T74	0	2	0	0
T75	0	3	0	0
T76	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1238308436	0	0
T1	1915336	992552	0	0
T2	42092	12396	0	0
T3	3602620	2697470	0	0
T4	474356	1356559	0	0
T7	1857636	132854	0	0
T11	1171748	581518	0	0
T12	250560	209549	0	0
T16	831804	624345	0	0
T21	319732	242651	0	0
T22	67836	59155	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2787	0	0
T1	957668	2	0	0
T2	21046	0	0	0
T3	1801310	9	0	0
T4	474356	12	0	0
T5	394010	26	0	0
T6	0	9	0	0
T7	1857636	3	0	0
T11	1171748	3	0	0
T12	250560	2	0	0
T16	831804	1	0	0
T17	1736368	1	0	0
T18	734590	4	0	0
T19	0	2	0	0
T20	0	3	0	0
T21	319732	4	0	0
T22	67836	2	0	0
T25	0	2	0	0
T26	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2730	0	0
T1	957668	2	0	0
T2	21046	0	0	0
T3	1801310	9	0	0
T4	474356	11	0	0
T5	394010	26	0	0
T6	0	9	0	0
T7	1857636	3	0	0
T11	1171748	3	0	0
T12	250560	2	0	0
T16	831804	1	0	0
T17	1736368	1	0	0
T18	734590	4	0	0
T19	0	2	0	0
T20	0	3	0	0
T21	319732	4	0	0
T22	67836	2	0	0
T25	0	2	0	0
T26	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2669	0	0
T1	957668	2	0	0
T2	21046	0	0	0
T3	1801310	9	0	0
T4	474356	11	0	0
T5	394010	25	0	0
T6	0	9	0	0
T7	1857636	3	0	0
T11	1171748	3	0	0
T12	250560	1	0	0
T16	831804	1	0	0
T17	1736368	1	0	0
T18	734590	4	0	0
T19	0	2	0	0
T20	0	3	0	0
T21	319732	4	0	0
T22	67836	2	0	0
T25	0	2	0	0
T26	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2620	0	0
T1	957668	2	0	0
T2	21046	0	0	0
T3	1801310	9	0	0
T4	474356	11	0	0
T5	394010	23	0	0
T6	0	9	0	0
T7	1857636	3	0	0
T11	1171748	3	0	0
T12	250560	1	0	0
T16	831804	1	0	0
T17	1736368	1	0	0
T18	734590	4	0	0
T19	0	2	0	0
T20	0	3	0	0
T21	319732	4	0	0
T22	67836	2	0	0
T25	0	2	0	0
T26	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4409	0	0
T2	42092	9	0	0
T3	3602620	0	0	0
T4	474356	587	0	0
T5	788020	74	0	0
T6	0	8	0	0
T7	1857636	0	0	0
T11	1171748	0	0	0
T12	250560	0	0	0
T16	831804	2	0	0
T19	0	5	0	0
T21	319732	0	0	0
T22	67836	0	0	0
T25	0	3	0	0
T26	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T62	0	4	0	0
T64	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T77	0	3	0	0
T78	0	16	0	0
T79	0	18	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	437169	0	0
T2	42092	1397	0	0
T3	3602620	0	0	0
T4	474356	26942	0	0
T5	788020	8433	0	0
T6	0	1419	0	0
T7	1857636	0	0	0
T11	1171748	0	0	0
T12	250560	0	0	0
T16	831804	292	0	0
T19	0	289	0	0
T21	319732	0	0	0
T22	67836	0	0	0
T25	0	288	0	0
T26	0	231	0	0
T43	0	123	0	0
T44	0	273	0	0
T45	0	8	0	0
T62	0	317	0	0
T64	0	63	0	0
T68	0	403	0	0
T69	0	30	0	0
T77	0	165	0	0
T78	0	3046	0	0
T79	0	3417	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4013	0	0
T2	42092	9	0	0
T3	3602620	0	0	0
T4	474356	587	0	0
T5	788020	70	0	0
T6	0	2	0	0
T7	1857636	0	0	0
T11	1171748	0	0	0
T12	250560	0	0	0
T16	831804	2	0	0
T19	0	3	0	0
T21	319732	0	0	0
T22	67836	0	0	0
T25	0	2	0	0
T26	0	1	0	0
T27	0	4	0	0
T29	0	3	0	0
T43	0	1	0	0
T44	0	2	0	0
T62	0	4	0	0
T64	0	3	0	0
T66	0	1	0	0
T77	0	3	0	0
T78	0	15	0	0
T79	0	25	0	0
T80	0	14	0	0
T81	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	252	0	0
T5	788020	3	0	0
T6	0	2	0	0
T17	3472736	0	0	0
T18	1469180	0	0	0
T19	460476	1	0	0
T25	290572	1	0	0
T26	111368	0	0	0
T27	0	3	0	0
T29	0	2	0	0
T30	0	1	0	0
T59	50332	0	0	0
T60	41148	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T68	0	1	0	0
T71	155556	0	0	0
T72	361324	0	0	0
T78	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4558	0	0
T8	371604	644	0	0
T9	0	1298	0	0
T10	0	610	0	0
T15	2389612	0	0	0
T31	0	1330	0	0
T32	0	676	0	0
T33	151272	0	0	0
T34	114808	0	0	0
T35	297136	0	0	0
T36	3359708	0	0	0
T37	35608	0	0	0
T38	57544	0	0	0
T39	38104	0	0	0
T40	2028560	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3718	0	0
T8	371604	524	0	0
T9	0	1058	0	0
T10	0	490	0	0
T15	2389612	0	0	0
T31	0	1090	0	0
T32	0	556	0	0
T33	151272	0	0	0
T34	114808	0	0	0
T35	297136	0	0	0
T36	3359708	0	0	0
T37	35608	0	0	0
T38	57544	0	0	0
T39	38104	0	0	0
T40	2028560	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1915336	1915316	0	0
T2	42092	41888	0	0
T3	3602620	3602280	0	0
T4	474356	474352	0	0
T7	1857636	1857604	0	0
T11	1171748	1171368	0	0
T12	250560	250252	0	0
T16	831804	831780	0	0
T21	319732	319428	0	0
T22	67836	67612	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1915336	1915316	0	0
T2	42092	41888	0	0
T3	3602620	3602280	0	0
T4	474356	474352	0	0
T7	1857636	1857604	0	0
T11	1171748	1171368	0	0
T12	250560	250252	0	0
T16	831804	831780	0	0
T21	319732	319428	0	0
T22	67836	67612	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T12,T4
1	0	1	Covered	T11,T4,T18
1	1	0	Covered	T2,T12,T4
1	1	1	Covered	T2,T4,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T16
0	1	Covered	T5,T6,T64
1	0	Covered	T26,T19,T6

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T19,T6

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T16
1	0	Not Covered
1	1	Covered	T5,T6,T64

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T12,T11,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T12,T11
1	Covered	T3,T12,T21

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T11
1	Covered	T1,T4,T22

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T16,T5,T71

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T4,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T12,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T12,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T12,T11,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T12
Phase1St	198	Covered	T1,T3,T12
Phase2St	215	Covered	T1,T3,T12
Phase3St	233	Covered	T1,T3,T12
TerminalSt	249	Covered	T1,T3,T12
TimeoutSt	159	Covered	T2,T4,T16

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T3,T12
IdleSt->TimeoutSt	159	Covered	T2,T4,T16
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T19,T37,T84
Phase0St->Phase1St	198	Covered	T1,T3,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T4,T28,T90
Phase1St->Phase2St	215	Covered	T1,T3,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T12,T19,T91
Phase2St->Phase3St	233	Covered	T1,T3,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T5,T19,T82
Phase3St->TerminalSt	249	Covered	T1,T3,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T12,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T4,T16
TimeoutSt->Phase0St	172	Covered	T5,T26,T19

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T26,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T16
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T37,T84
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T28,T52
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T12,T19,T91
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T19,T82
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T12,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	705589305	187	0	0
CheckAccumTrig0_A	705589305	867	0	0
CheckAccumTrig1_A	705589305	53	0	0
CheckClr_A	705589305	429	0	0
CheckEn_A	705349533	256665916	0	0
CheckPhase0_A	705589305	963	0	0
CheckPhase1_A	705589305	942	0	0
CheckPhase2_A	705589305	922	0	0
CheckPhase3_A	705589305	905	0	0
CheckTimeout0_A	705589305	1034	0	0
CheckTimeoutSt1_A	705589305	109828	0	0
CheckTimeoutSt2_A	705589305	915	0	0
CheckTimeoutStTrig_A	705589305	64	0	0
ErrorStAllEscAsserted_A	705589305	1148	0	0
ErrorStIsTerminal_A	705589305	938	0	0
EscStateOut_A	705347966	705278712	0	0
u_state_regs_A	705589305	705430251	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	187	0	0
T8	92901	19	0	0
T9	0	50	0	0
T10	0	26	0	0
T15	597403	0	0	0
T31	0	68	0	0
T32	0	24	0	0
T33	37818	0	0	0
T34	28702	0	0	0
T35	74284	0	0	0
T36	839927	0	0	0
T37	8902	0	0	0
T38	14386	0	0	0
T39	9526	0	0	0
T40	507140	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	867	0	0
T1	478834	1	0	0
T2	10523	0	0	0
T3	900655	9	0	0
T4	118589	5	0	0
T5	0	5	0	0
T7	464409	0	0	0
T11	292937	1	0	0
T12	62640	2	0	0
T16	207951	1	0	0
T17	0	1	0	0
T21	79933	4	0	0
T22	16959	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	53	0	0
T6	985119	3	0	0
T19	115119	1	0	0
T20	108024	0	0	0
T25	72643	0	0	0
T26	27842	1	0	0
T30	0	1	0	0
T37	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T54	0	1	0	0
T59	12583	0	0	0
T60	10287	0	0	0
T61	8988	0	0	0
T62	11209	0	0	0
T63	238701	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	429	0	0
T3	900655	8	0	0
T4	118589	2	0	0
T5	197005	2	0	0
T6	0	4	0	0
T7	464409	0	0	0
T11	292937	0	0	0
T12	62640	2	0	0
T16	207951	0	0	0
T17	868184	0	0	0
T19	0	6	0	0
T21	79933	3	0	0
T22	16959	0	0	0
T25	0	2	0	0
T71	0	1	0	0
T72	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705349533	256665916	0	0
T1	478834	19405	0	0
T2	10523	1579	0	0
T3	900655	582	0	0
T4	118589	486559	0	0
T7	464409	54148	0	0
T11	292937	5662	0	0
T12	62640	21863	0	0
T16	207951	2040	0	0
T21	79933	3083	0	0
T22	16959	13998	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	963	0	0
T1	478834	1	0	0
T2	10523	0	0	0
T3	900655	9	0	0
T4	118589	5	0	0
T5	0	6	0	0
T7	464409	0	0	0
T11	292937	1	0	0
T12	62640	2	0	0
T16	207951	1	0	0
T17	0	1	0	0
T21	79933	4	0	0
T22	16959	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	942	0	0
T1	478834	1	0	0
T2	10523	0	0	0
T3	900655	9	0	0
T4	118589	4	0	0
T5	0	6	0	0
T7	464409	0	0	0
T11	292937	1	0	0
T12	62640	2	0	0
T16	207951	1	0	0
T17	0	1	0	0
T21	79933	4	0	0
T22	16959	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	922	0	0
T1	478834	1	0	0
T2	10523	0	0	0
T3	900655	9	0	0
T4	118589	4	0	0
T5	0	6	0	0
T7	464409	0	0	0
T11	292937	1	0	0
T12	62640	1	0	0
T16	207951	1	0	0
T17	0	1	0	0
T21	79933	4	0	0
T22	16959	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	905	0	0
T1	478834	1	0	0
T2	10523	0	0	0
T3	900655	9	0	0
T4	118589	4	0	0
T5	0	4	0	0
T7	464409	0	0	0
T11	292937	1	0	0
T12	62640	1	0	0
T16	207951	1	0	0
T17	0	1	0	0
T21	79933	4	0	0
T22	16959	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	1034	0	0
T2	10523	3	0	0
T3	900655	0	0	0
T4	118589	217	0	0
T5	197005	38	0	0
T6	0	4	0	0
T7	464409	0	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	1	0	0
T19	0	2	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T25	0	2	0	0
T26	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	109828	0	0
T2	10523	328	0	0
T3	900655	0	0	0
T4	118589	9595	0	0
T5	197005	5726	0	0
T6	0	48	0	0
T7	464409	0	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	153	0	0
T19	0	69	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T25	0	107	0	0
T26	0	2	0	0
T43	0	123	0	0
T45	0	8	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	915	0	0
T2	10523	3	0	0
T3	900655	0	0	0
T4	118589	217	0	0
T5	197005	37	0	0
T7	464409	0	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	1	0	0
T19	0	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T25	0	2	0	0
T29	0	3	0	0
T43	0	1	0	0
T64	0	2	0	0
T66	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	64	0	0
T5	197005	1	0	0
T6	0	1	0	0
T17	868184	0	0	0
T18	367295	0	0	0
T19	115119	0	0	0
T25	72643	0	0	0
T26	27842	0	0	0
T27	0	2	0	0
T29	0	1	0	0
T59	12583	0	0	0
T60	10287	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T71	38889	0	0	0
T72	90331	0	0	0
T80	0	1	0	0
T85	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	1148	0	0
T8	92901	171	0	0
T9	0	331	0	0
T10	0	155	0	0
T15	597403	0	0	0
T31	0	332	0	0
T32	0	159	0	0
T33	37818	0	0	0
T34	28702	0	0	0
T35	74284	0	0	0
T36	839927	0	0	0
T37	8902	0	0	0
T38	14386	0	0	0
T39	9526	0	0	0
T40	507140	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	938	0	0
T8	92901	141	0	0
T9	0	271	0	0
T10	0	125	0	0
T15	597403	0	0	0
T31	0	272	0	0
T32	0	129	0	0
T33	37818	0	0	0
T34	28702	0	0	0
T35	74284	0	0	0
T36	839927	0	0	0
T37	8902	0	0	0
T38	14386	0	0	0
T39	9526	0	0	0
T40	507140	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705347966	705278712	0	0
T1	478834	478829	0	0
T2	10523	10472	0	0
T3	900655	900570	0	0
T4	118589	118588	0	0
T7	464409	464401	0	0
T11	292937	292842	0	0
T12	62640	62563	0	0
T16	207951	207945	0	0
T21	79933	79857	0	0
T22	16959	16903	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	705430251	0	0
T1	478834	478829	0	0
T2	10523	10472	0	0
T3	900655	900570	0	0
T4	118589	118588	0	0
T7	464409	464401	0	0
T11	292937	292842	0	0
T12	62640	62563	0	0
T16	207951	207945	0	0
T21	79933	79857	0	0
T22	16959	16903	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T16
1	0	1	Covered	T1,T11,T18
1	1	0	Covered	T2,T4,T16
1	1	1	Covered	T2,T4,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T16
0	1	Covered	T5,T19,T68
1	0	Covered	T30,T48,T37

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T30,T48,T37

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T16
1	0	Not Covered
1	1	Covered	T5,T19,T68

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T4
1	Covered	T4,T22,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T4
1	Covered	T4,T5,T26

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T22,T5
1	Covered	T1,T7,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T4
1	Covered	T25,T6,T63

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T7,T4,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T7,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T5,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T7,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T7,T4
Phase1St	198	Covered	T1,T7,T4
Phase2St	215	Covered	T1,T7,T4
Phase3St	233	Covered	T1,T7,T4
TerminalSt	249	Covered	T1,T7,T4
TimeoutSt	159	Covered	T2,T4,T16

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T7,T4
IdleSt->TimeoutSt	159	Covered	T2,T4,T16
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T91,T28,T92
Phase0St->Phase1St	198	Covered	T1,T7,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T6,T93,T94
Phase1St->Phase2St	215	Covered	T1,T7,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T95,T37,T96
Phase2St->Phase3St	233	Covered	T1,T7,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T90,T97,T98
Phase3St->TerminalSt	249	Covered	T1,T7,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T22,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T4,T16
TimeoutSt->Phase0St	172	Covered	T5,T19,T68

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T19,T68
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T16
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T91,T28,T99
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T7,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T7,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T93,T94
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T7,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T7,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T95,T37,T96
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T7,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T7,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T90,T97,T98
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T7,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T7,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T22,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T7,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	705589305	242	0	0
CheckAccumTrig0_A	705589305	505	0	0
CheckAccumTrig1_A	705589305	26	0	0
CheckClr_A	705589305	212	0	0
CheckEn_A	705349533	339859225	0	0
CheckPhase0_A	705589305	581	0	0
CheckPhase1_A	705589305	575	0	0
CheckPhase2_A	705589305	562	0	0
CheckPhase3_A	705589305	553	0	0
CheckTimeout0_A	705589305	822	0	0
CheckTimeoutSt1_A	705589305	94504	0	0
CheckTimeoutSt2_A	705589305	738	0	0
CheckTimeoutStTrig_A	705589305	56	0	0
ErrorStAllEscAsserted_A	705589305	1165	0	0
ErrorStIsTerminal_A	705589305	955	0	0
EscStateOut_A	705347966	705278712	0	0
u_state_regs_A	705589305	705430251	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	242	0	0
T8	92901	42	0	0
T9	0	64	0	0
T10	0	34	0	0
T15	597403	0	0	0
T31	0	58	0	0
T32	0	44	0	0
T33	37818	0	0	0
T34	28702	0	0	0
T35	74284	0	0	0
T36	839927	0	0	0
T37	8902	0	0	0
T38	14386	0	0	0
T39	9526	0	0	0
T40	507140	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	505	0	0
T1	478834	1	0	0
T2	10523	0	0	0
T3	900655	0	0	0
T4	118589	3	0	0
T5	0	3	0	0
T6	0	4	0	0
T7	464409	1	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T18	0	1	0	0
T20	0	1	0	0
T21	79933	0	0	0
T22	16959	1	0	0
T25	0	1	0	0
T26	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	26	0	0
T30	447012	1	0	0
T37	0	1	0	0
T48	100854	1	0	0
T80	193551	0	0	0
T91	164464	0	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	89043	0	0	0
T108	48457	0	0	0
T109	225656	0	0	0
T110	85766	0	0	0
T111	487139	0	0	0
T112	314168	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	212	0	0
T4	118589	1	0	0
T5	197005	1	0	0
T6	0	2	0	0
T16	207951	0	0	0
T17	868184	0	0	0
T18	367295	0	0	0
T21	79933	0	0	0
T22	16959	1	0	0
T26	27842	0	0	0
T30	0	1	0	0
T43	0	1	0	0
T61	0	1	0	0
T68	0	1	0	0
T71	38889	0	0	0
T72	90331	0	0	0
T75	0	1	0	0
T95	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705349533	339859225	0	0
T1	478834	16995	0	0
T2	10523	6341	0	0
T3	900655	900569	0	0
T4	118589	346522	0	0
T7	464409	38493	0	0
T11	292937	282005	0	0
T12	62640	62562	0	0
T16	207951	207369	0	0
T21	79933	79856	0	0
T22	16959	11353	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	581	0	0
T1	478834	1	0	0
T2	10523	0	0	0
T3	900655	0	0	0
T4	118589	3	0	0
T5	0	4	0	0
T7	464409	1	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	79933	0	0	0
T22	16959	1	0	0
T25	0	1	0	0
T26	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	575	0	0
T1	478834	1	0	0
T2	10523	0	0	0
T3	900655	0	0	0
T4	118589	3	0	0
T5	0	4	0	0
T7	464409	1	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	79933	0	0	0
T22	16959	1	0	0
T25	0	1	0	0
T26	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	562	0	0
T1	478834	1	0	0
T2	10523	0	0	0
T3	900655	0	0	0
T4	118589	3	0	0
T5	0	4	0	0
T7	464409	1	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	79933	0	0	0
T22	16959	1	0	0
T25	0	1	0	0
T26	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	553	0	0
T1	478834	1	0	0
T2	10523	0	0	0
T3	900655	0	0	0
T4	118589	3	0	0
T5	0	4	0	0
T7	464409	1	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	79933	0	0	0
T22	16959	1	0	0
T25	0	1	0	0
T26	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	822	0	0
T2	10523	1	0	0
T3	900655	0	0	0
T4	118589	2	0	0
T5	197005	3	0	0
T6	0	3	0	0
T7	464409	0	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	1	0	0
T19	0	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T62	0	2	0	0
T77	0	2	0	0
T78	0	12	0	0
T79	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	94504	0	0
T2	10523	176	0	0
T3	900655	0	0	0
T4	118589	98	0	0
T5	197005	320	0	0
T6	0	556	0	0
T7	464409	0	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	139	0	0
T19	0	66	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T62	0	169	0	0
T77	0	120	0	0
T78	0	2423	0	0
T79	0	1387	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	738	0	0
T2	10523	1	0	0
T3	900655	0	0	0
T4	118589	2	0	0
T5	197005	2	0	0
T6	0	2	0	0
T7	464409	0	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T44	0	1	0	0
T62	0	2	0	0
T77	0	2	0	0
T78	0	12	0	0
T79	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	56	0	0
T5	197005	1	0	0
T17	868184	0	0	0
T18	367295	0	0	0
T19	115119	1	0	0
T23	0	1	0	0
T25	72643	0	0	0
T26	27842	0	0	0
T27	0	1	0	0
T59	12583	0	0	0
T60	10287	0	0	0
T68	0	1	0	0
T71	38889	0	0	0
T72	90331	0	0	0
T83	0	1	0	0
T86	0	1	0	0
T89	0	1	0	0
T113	0	1	0	0
T114	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	1165	0	0
T8	92901	168	0	0
T9	0	348	0	0
T10	0	143	0	0
T15	597403	0	0	0
T31	0	329	0	0
T32	0	177	0	0
T33	37818	0	0	0
T34	28702	0	0	0
T35	74284	0	0	0
T36	839927	0	0	0
T37	8902	0	0	0
T38	14386	0	0	0
T39	9526	0	0	0
T40	507140	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	955	0	0
T8	92901	138	0	0
T9	0	288	0	0
T10	0	113	0	0
T15	597403	0	0	0
T31	0	269	0	0
T32	0	147	0	0
T33	37818	0	0	0
T34	28702	0	0	0
T35	74284	0	0	0
T36	839927	0	0	0
T37	8902	0	0	0
T38	14386	0	0	0
T39	9526	0	0	0
T40	507140	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705347966	705278712	0	0
T1	478834	478829	0	0
T2	10523	10472	0	0
T3	900655	900570	0	0
T4	118589	118588	0	0
T7	464409	464401	0	0
T11	292937	292842	0	0
T12	62640	62563	0	0
T16	207951	207945	0	0
T21	79933	79857	0	0
T22	16959	16903	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	705430251	0	0
T1	478834	478829	0	0
T2	10523	10472	0	0
T3	900655	900570	0	0
T4	118589	118588	0	0
T7	464409	464401	0	0
T11	292937	292842	0	0
T12	62640	62563	0	0
T16	207951	207945	0	0
T21	79933	79857	0	0
T22	16959	16903	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T7,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T23
1	1	1	Covered	T7,T11,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T16
1	0	1	Covered	T7,T11,T18
1	1	0	Covered	T4,T16,T5
1	1	1	Covered	T2,T4,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T5,T25,T6
1	0	Covered	T46,T38,T49

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T46,T38,T49

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Not Covered
1	1	Covered	T5,T25,T6

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T11,T4
1	Covered	T5,T25,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T11,T4
1	Covered	T11,T5,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T4,T5
1	Covered	T7,T5,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T7,T11,T5
1	Covered	T11,T4,T18

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T7,T11,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T7,T11,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T4,T26

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T7,T11,T4
Phase1St	198	Covered	T7,T11,T4
Phase2St	215	Covered	T7,T11,T4
Phase3St	233	Covered	T7,T11,T4
TerminalSt	249	Covered	T7,T11,T4
TimeoutSt	159	Covered	T2,T4,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T7,T11,T4
IdleSt->TimeoutSt	159	Covered	T2,T4,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T16,T27,T74
Phase0St->Phase1St	198	Covered	T7,T11,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T52,T115,T116
Phase1St->Phase2St	215	Covered	T7,T11,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T29,T117,T118
Phase2St->Phase3St	233	Covered	T7,T11,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T30,T80,T119
Phase3St->TerminalSt	249	Covered	T7,T11,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T11,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T4,T5
TimeoutSt->Phase0St	172	Covered	T5,T25,T6

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T11,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T25,T6
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T16,T27,T74
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T7,T11,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T7,T11,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T52,T115,T116
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T7,T11,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T7,T11,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T117,T118
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T7,T11,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T7,T11,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T30,T80,T119
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T7,T11,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T7,T11,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T11,T18,T26
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T7,T11,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	705589305	207	0	0
CheckAccumTrig0_A	705589305	570	0	0
CheckAccumTrig1_A	705589305	26	0	0
CheckClr_A	705589305	284	0	0
CheckEn_A	705349533	320159566	0	0
CheckPhase0_A	705589305	646	0	0
CheckPhase1_A	705589305	638	0	0
CheckPhase2_A	705589305	625	0	0
CheckPhase3_A	705589305	616	0	0
CheckTimeout0_A	705589305	1473	0	0
CheckTimeoutSt1_A	705589305	129278	0	0
CheckTimeoutSt2_A	705589305	1377	0	0
CheckTimeoutStTrig_A	705589305	66	0	0
ErrorStAllEscAsserted_A	705589305	1144	0	0
ErrorStIsTerminal_A	705589305	934	0	0
EscStateOut_A	705347966	705278712	0	0
u_state_regs_A	705589305	705430251	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	207	0	0
T8	92901	37	0	0
T9	0	57	0	0
T10	0	34	0	0
T15	597403	0	0	0
T31	0	51	0	0
T32	0	28	0	0
T33	37818	0	0	0
T34	28702	0	0	0
T35	74284	0	0	0
T36	839927	0	0	0
T37	8902	0	0	0
T38	14386	0	0	0
T39	9526	0	0	0
T40	507140	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	570	0	0
T4	118589	2	0	0
T5	197005	3	0	0
T6	0	1	0	0
T7	464409	1	0	0
T11	292937	2	0	0
T12	62640	0	0	0
T16	207951	1	0	0
T17	868184	0	0	0
T18	367295	2	0	0
T20	0	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T26	0	2	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	26	0	0
T29	113127	0	0	0
T38	0	1	0	0
T44	258710	0	0	0
T46	18414	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T64	14575	0	0	0
T65	44970	0	0	0
T66	11774	0	0	0
T67	152698	0	0	0
T68	24804	0	0	0
T69	33602	0	0	0
T70	308915	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	284	0	0
T4	118589	0	0	0
T5	197005	0	0	0
T11	292937	1	0	0
T16	207951	1	0	0
T17	868184	0	0	0
T18	367295	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T29	0	1	0	0
T71	38889	0	0	0
T72	90331	0	0	0
T73	0	9	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705349533	320159566	0	0
T1	478834	478075	0	0
T2	10523	1753	0	0
T3	900655	900569	0	0
T4	118589	261450	0	0
T7	464409	12577	0	0
T11	292937	11782	0	0
T12	62640	62562	0	0
T16	207951	206991	0	0
T21	79933	79856	0	0
T22	16959	16902	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	646	0	0
T4	118589	2	0	0
T5	197005	4	0	0
T6	0	2	0	0
T7	464409	1	0	0
T11	292937	2	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T17	868184	0	0	0
T18	367295	2	0	0
T20	0	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T25	0	1	0	0
T26	0	2	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	638	0	0
T4	118589	2	0	0
T5	197005	4	0	0
T6	0	2	0	0
T7	464409	1	0	0
T11	292937	2	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T17	868184	0	0	0
T18	367295	2	0	0
T20	0	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T25	0	1	0	0
T26	0	2	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	625	0	0
T4	118589	2	0	0
T5	197005	4	0	0
T6	0	2	0	0
T7	464409	1	0	0
T11	292937	2	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T17	868184	0	0	0
T18	367295	2	0	0
T20	0	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T25	0	1	0	0
T26	0	2	0	0
T41	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	616	0	0
T4	118589	2	0	0
T5	197005	4	0	0
T6	0	2	0	0
T7	464409	1	0	0
T11	292937	2	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T17	868184	0	0	0
T18	367295	2	0	0
T20	0	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T25	0	1	0	0
T26	0	2	0	0
T41	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	1473	0	0
T2	10523	2	0	0
T3	900655	0	0	0
T4	118589	223	0	0
T5	197005	2	0	0
T6	0	1	0	0
T7	464409	0	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T19	0	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T62	0	2	0	0
T77	0	1	0	0
T78	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	129278	0	0
T2	10523	424	0	0
T3	900655	0	0	0
T4	118589	11207	0	0
T5	197005	122	0	0
T6	0	815	0	0
T7	464409	0	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T19	0	66	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T25	0	181	0	0
T26	0	229	0	0
T62	0	148	0	0
T77	0	45	0	0
T78	0	347	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	1377	0	0
T2	10523	2	0	0
T3	900655	0	0	0
T4	118589	223	0	0
T5	197005	1	0	0
T7	464409	0	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T19	0	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T26	0	1	0	0
T62	0	2	0	0
T64	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0
T79	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	66	0	0
T5	197005	1	0	0
T6	0	1	0	0
T17	868184	0	0	0
T18	367295	0	0	0
T19	115119	0	0	0
T25	72643	1	0	0
T26	27842	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T59	12583	0	0	0
T60	10287	0	0	0
T71	38889	0	0	0
T72	90331	0	0	0
T78	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	1144	0	0
T8	92901	175	0	0
T9	0	330	0	0
T10	0	151	0	0
T15	597403	0	0	0
T31	0	324	0	0
T32	0	164	0	0
T33	37818	0	0	0
T34	28702	0	0	0
T35	74284	0	0	0
T36	839927	0	0	0
T37	8902	0	0	0
T38	14386	0	0	0
T39	9526	0	0	0
T40	507140	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	934	0	0
T8	92901	145	0	0
T9	0	270	0	0
T10	0	121	0	0
T15	597403	0	0	0
T31	0	264	0	0
T32	0	134	0	0
T33	37818	0	0	0
T34	28702	0	0	0
T35	74284	0	0	0
T36	839927	0	0	0
T37	8902	0	0	0
T38	14386	0	0	0
T39	9526	0	0	0
T40	507140	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705347966	705278712	0	0
T1	478834	478829	0	0
T2	10523	10472	0	0
T3	900655	900570	0	0
T4	118589	118588	0	0
T7	464409	464401	0	0
T11	292937	292842	0	0
T12	62640	62563	0	0
T16	207951	207945	0	0
T21	79933	79857	0	0
T22	16959	16903	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	705430251	0	0
T1	478834	478829	0	0
T2	10523	10472	0	0
T3	900655	900570	0	0
T4	118589	118588	0	0
T7	464409	464401	0	0
T11	292937	292842	0	0
T12	62640	62563	0	0
T16	207951	207945	0	0
T21	79933	79857	0	0
T22	16959	16903	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T7,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T24
1	1	1	Covered	T7,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T59,T6,T41
1	1	0	Covered	T2,T4,T16
1	1	1	Covered	T2,T4,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T5,T64,T68
1	0	Covered	T30,T81,T120

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T30,T81,T120

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Not Covered
1	1	Covered	T5,T64,T68

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T5,T6,T69

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T19,T20,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T6

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T19
1	Covered	T7,T4,T18

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T5,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T5,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T5,T18,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T7,T5,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T7,T4,T5
Phase1St	198	Covered	T7,T4,T5
Phase2St	215	Covered	T7,T4,T5
Phase3St	233	Covered	T7,T4,T5
TerminalSt	249	Covered	T7,T4,T5
TimeoutSt	159	Covered	T2,T4,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T7,T4,T5
IdleSt->TimeoutSt	159	Covered	T2,T4,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T30,T92,T121
Phase0St->Phase1St	198	Covered	T7,T4,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T36,T119,T122
Phase1St->Phase2St	215	Covered	T7,T4,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T5,T123,T124
Phase2St->Phase3St	233	Covered	T7,T4,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T90,T125,T126
Phase3St->TerminalSt	249	Covered	T7,T4,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T5,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T4,T5
TimeoutSt->Phase0St	172	Covered	T5,T64,T68

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T64,T68
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T121,T127
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T7,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T7,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T36,T119,T122
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T7,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T7,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T123,T124
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T7,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T7,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T90,T125,T126
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T7,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T7,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T6,T27
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T7,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	705589305	218	0	0
CheckAccumTrig0_A	705589305	509	0	0
CheckAccumTrig1_A	705589305	28	0	0
CheckClr_A	705589305	232	0	0
CheckEn_A	705349533	321623729	0	0
CheckPhase0_A	705589305	597	0	0
CheckPhase1_A	705589305	575	0	0
CheckPhase2_A	705589305	560	0	0
CheckPhase3_A	705589305	546	0	0
CheckTimeout0_A	705589305	1080	0	0
CheckTimeoutSt1_A	705589305	103559	0	0
CheckTimeoutSt2_A	705589305	983	0	0
CheckTimeoutStTrig_A	705589305	66	0	0
ErrorStAllEscAsserted_A	705589305	1101	0	0
ErrorStIsTerminal_A	705589305	891	0	0
EscStateOut_A	705347966	705278712	0	0
u_state_regs_A	705589305	705430251	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	218	0	0
T8	92901	25	0	0
T9	0	64	0	0
T10	0	33	0	0
T15	597403	0	0	0
T31	0	58	0	0
T32	0	38	0	0
T33	37818	0	0	0
T34	28702	0	0	0
T35	74284	0	0	0
T36	839927	0	0	0
T37	8902	0	0	0
T38	14386	0	0	0
T39	9526	0	0	0
T40	507140	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	509	0	0
T4	118589	2	0	0
T5	197005	11	0	0
T6	0	7	0	0
T7	464409	1	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T17	868184	0	0	0
T18	367295	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	28	0	0
T23	0	1	0	0
T30	447012	1	0	0
T48	100854	0	0	0
T80	193551	0	0	0
T81	0	1	0	0
T90	0	1	0	0
T91	164464	0	0	0
T104	0	1	0	0
T107	89043	0	0	0
T108	48457	0	0	0
T109	225656	0	0	0
T110	85766	0	0	0
T111	487139	0	0	0
T112	314168	0	0	0
T120	0	1	0	0
T124	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	232	0	0
T5	197005	8	0	0
T6	0	1	0	0
T17	868184	0	0	0
T18	367295	0	0	0
T19	115119	0	0	0
T25	72643	0	0	0
T26	27842	0	0	0
T27	0	1	0	0
T30	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T59	12583	0	0	0
T60	10287	0	0	0
T71	38889	0	0	0
T72	90331	0	0	0
T81	0	2	0	0
T107	0	1	0	0
T119	0	1	0	0
T131	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705349533	321623729	0	0
T1	478834	478077	0	0
T2	10523	2723	0	0
T3	900655	895750	0	0
T4	118589	262028	0	0
T7	464409	27636	0	0
T11	292937	282069	0	0
T12	62640	62562	0	0
T16	207951	207945	0	0
T21	79933	79856	0	0
T22	16959	16902	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	597	0	0
T4	118589	2	0	0
T5	197005	12	0	0
T6	0	7	0	0
T7	464409	1	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T17	868184	0	0	0
T18	367295	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	575	0	0
T4	118589	2	0	0
T5	197005	12	0	0
T6	0	7	0	0
T7	464409	1	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T17	868184	0	0	0
T18	367295	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	560	0	0
T4	118589	2	0	0
T5	197005	11	0	0
T6	0	7	0	0
T7	464409	1	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T17	868184	0	0	0
T18	367295	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	546	0	0
T4	118589	2	0	0
T5	197005	11	0	0
T6	0	7	0	0
T7	464409	1	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T17	868184	0	0	0
T18	367295	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	1080	0	0
T2	10523	3	0	0
T3	900655	0	0	0
T4	118589	145	0	0
T5	197005	31	0	0
T7	464409	0	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T19	0	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T44	0	1	0	0
T64	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T78	0	1	0	0
T79	0	11	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	103559	0	0
T2	10523	469	0	0
T3	900655	0	0	0
T4	118589	6042	0	0
T5	197005	2265	0	0
T7	464409	0	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T19	0	88	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T44	0	273	0	0
T64	0	63	0	0
T68	0	403	0	0
T69	0	30	0	0
T78	0	276	0	0
T79	0	2030	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	983	0	0
T2	10523	3	0	0
T3	900655	0	0	0
T4	118589	145	0	0
T5	197005	30	0	0
T7	464409	0	0	0
T11	292937	0	0	0
T12	62640	0	0	0
T16	207951	0	0	0
T19	0	1	0	0
T21	79933	0	0	0
T22	16959	0	0	0
T27	0	4	0	0
T44	0	1	0	0
T78	0	1	0	0
T79	0	11	0	0
T80	0	14	0	0
T81	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	66	0	0
T5	197005	1	0	0
T17	868184	0	0	0
T18	367295	0	0	0
T19	115119	0	0	0
T25	72643	0	0	0
T26	27842	0	0	0
T59	12583	0	0	0
T60	10287	0	0	0
T64	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T71	38889	0	0	0
T72	90331	0	0	0
T85	0	1	0	0
T91	0	1	0	0
T113	0	2	0	0
T114	0	1	0	0
T132	0	1	0	0
T133	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	1101	0	0
T8	92901	130	0	0
T9	0	289	0	0
T10	0	161	0	0
T15	597403	0	0	0
T31	0	345	0	0
T32	0	176	0	0
T33	37818	0	0	0
T34	28702	0	0	0
T35	74284	0	0	0
T36	839927	0	0	0
T37	8902	0	0	0
T38	14386	0	0	0
T39	9526	0	0	0
T40	507140	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	891	0	0
T8	92901	100	0	0
T9	0	229	0	0
T10	0	131	0	0
T15	597403	0	0	0
T31	0	285	0	0
T32	0	146	0	0
T33	37818	0	0	0
T34	28702	0	0	0
T35	74284	0	0	0
T36	839927	0	0	0
T37	8902	0	0	0
T38	14386	0	0	0
T39	9526	0	0	0
T40	507140	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705347966	705278712	0	0
T1	478834	478829	0	0
T2	10523	10472	0	0
T3	900655	900570	0	0
T4	118589	118588	0	0
T7	464409	464401	0	0
T11	292937	292842	0	0
T12	62640	62563	0	0
T16	207951	207945	0	0
T21	79933	79857	0	0
T22	16959	16903	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	705589305	705430251	0	0
T1	478834	478829	0	0
T2	10523	10472	0	0
T3	900655	900570	0	0
T4	118589	118588	0	0
T7	464409	464401	0	0
T11	292937	292842	0	0
T12	62640	62563	0	0
T16	207951	207945	0	0
T21	79933	79857	0	0
T22	16959	16903	0	0