Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T13,T43
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13640	0	0
DisabledNoTrigBkwd_A	2147483647	636978	0	0
DisabledNoTrigFwd_A	2147483647	1172417960	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13640	0	0
T2	3880	553	0	0
T3	131100	0	0	0
T4	975220	0	0	0
T5	394954	0	0	0
T7	220502	0	0	0
T8	140884	0	0	0
T12	40524	0	0	0
T13	10224	1637	0	0
T14	308434	0	0	0
T15	169154	0	0	0
T17	105568	0	0	0
T19	168114	0	0	0
T35	0	667	0	0
T40	31117	0	0	0
T43	2776	501	0	0
T60	0	414	0	0
T77	186222	0	0	0
T80	358274	0	0	0
T204	0	777	0	0
T205	1772	725	0	0
T206	4817	1240	0	0
T207	0	646	0	0
T208	0	1168	0	0
T209	0	186	0	0
T210	0	147	0	0
T211	0	593	0	0
T212	0	732	0	0
T213	0	433	0	0
T214	0	1174	0	0
T215	0	147	0	0
T216	0	501	0	0
T217	0	594	0	0
T218	0	805	0	0
T219	1941	0	0	0
T220	15366	0	0	0
T221	160898	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	636978	0	0
T1	79331	13	0	0
T2	3880	6	0	0
T3	393300	9	0	0
T4	1950440	1327	0	0
T5	789908	9714	0	0
T7	441004	5995	0	0
T8	422652	1	0	0
T12	121572	0	0	0
T13	15336	36	0	0
T14	616868	7520	0	0
T15	507462	6018	0	0
T16	394293	0	0	0
T17	105568	7142	0	0
T19	252171	132	0	0
T27	0	1875	0	0
T40	31117	35	0	0
T41	0	288	0	0
T42	0	1	0	0
T43	2776	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1172417960	0	0
T1	317324	233292	0	0
T2	15520	12506	0	0
T3	524400	562783	0	0
T4	1950440	1181020	0	0
T5	789908	1162826	0	0
T7	441004	233382	0	0
T8	563536	282353	0	0
T12	162096	90785	0	0
T13	20448	12693	0	0
T14	616868	167811	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T12
1	1	Covered	T1,T3,T8

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T43,T60
1	1	Covered	T1,T3,T8

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T13,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	538519207	5083	0	0
DisabledNoTrigBkwd_A	538519207	141765	0	0
DisabledNoTrigFwd_A	538519207	290651222	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	5083	0	0
T4	487610	0	0	0
T5	197477	0	0	0
T7	110251	0	0	0
T13	5112	1637	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T17	105568	0	0	0
T19	84057	0	0	0
T40	31117	0	0	0
T43	2776	501	0	0
T60	0	414	0	0
T204	0	777	0	0
T210	0	147	0	0
T213	0	433	0	0
T214	0	1174	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	141765	0	0
T3	131100	5	0	0
T4	487610	404	0	0
T5	197477	4119	0	0
T7	110251	4449	0	0
T8	140884	0	0	0
T12	40524	0	0	0
T13	5112	36	0	0
T14	154217	1747	0	0
T15	169154	1473	0	0
T17	0	1815	0	0
T19	84057	32	0	0
T40	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	290651222	0	0
T1	79331	77184	0	0
T2	3880	3085	0	0
T3	131100	142903	0	0
T4	487610	244330	0	0
T5	197477	23557	0	0
T7	110251	3761	0	0
T8	140884	41006	0	0
T12	40524	13472	0	0
T13	5112	3160	0	0
T14	154217	3817	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T12
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T206,T207
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	538519207	4452	0	0
DisabledNoTrigBkwd_A	538519207	136699	0	0
DisabledNoTrigFwd_A	538519207	267173628	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	4452	0	0
T2	3880	553	0	0
T3	131100	0	0	0
T4	487610	0	0	0
T5	197477	0	0	0
T7	110251	0	0	0
T8	140884	0	0	0
T12	40524	0	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T19	84057	0	0	0
T206	0	1240	0	0
T207	0	646	0	0
T209	0	186	0	0
T212	0	732	0	0
T216	0	501	0	0
T217	0	594	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	136699	0	0
T1	79331	13	0	0
T2	3880	6	0	0
T3	131100	1	0	0
T4	487610	96	0	0
T5	197477	2803	0	0
T7	110251	0	0	0
T8	140884	1	0	0
T12	40524	0	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	0	2225	0	0
T17	0	2112	0	0
T19	0	29	0	0
T40	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	267173628	0	0
T1	79331	599	0	0
T2	3880	3110	0	0
T3	131100	129453	0	0
T4	487610	420690	0	0
T5	197477	337330	0	0
T7	110251	110246	0	0
T8	140884	9641	0	0
T12	40524	28472	0	0
T13	5112	3166	0	0
T14	154217	153907	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T4
1	0	Covered	T1,T3,T8
1	1	Covered	T4,T5,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T205,T35,T218
1	1	Covered	T4,T5,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T14

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	538519207	2197	0	0
DisabledNoTrigBkwd_A	538519207	199034	0	0
DisabledNoTrigFwd_A	538519207	291479663	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	2197	0	0
T26	869176	0	0	0
T35	0	667	0	0
T77	186222	0	0	0
T80	358274	0	0	0
T81	21545	0	0	0
T205	1772	725	0	0
T206	4817	0	0	0
T218	0	805	0	0
T219	1941	0	0	0
T220	15366	0	0	0
T221	160898	0	0	0
T222	447996	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	199034	0	0
T4	487610	512	0	0
T5	197477	10	0	0
T7	110251	0	0	0
T14	154217	2451	0	0
T15	169154	2319	0	0
T16	394293	0	0	0
T17	105568	1456	0	0
T19	84057	33	0	0
T27	0	1861	0	0
T40	31117	16	0	0
T41	0	288	0	0
T42	0	1	0	0
T43	2776	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	291479663	0	0
T1	79331	79275	0	0
T2	3880	3143	0	0
T3	131100	131094	0	0
T4	487610	252673	0	0
T5	197477	196035	0	0
T7	110251	110047	0	0
T8	140884	140809	0	0
T12	40524	40441	0	0
T13	5112	3181	0	0
T14	154217	3825	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T208,T211,T215
1	1	Covered	T1,T3,T8

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	538519207	1908	0	0
DisabledNoTrigBkwd_A	538519207	159480	0	0
DisabledNoTrigFwd_A	538519207	323113447	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	1908	0	0
T48	131567	0	0	0
T49	484122	0	0	0
T107	56012	0	0	0
T208	4638	1168	0	0
T209	921	0	0	0
T210	818	0	0	0
T211	0	593	0	0
T215	0	147	0	0
T223	76528	0	0	0
T224	84098	0	0	0
T225	149985	0	0	0
T226	111087	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	159480	0	0
T3	131100	3	0	0
T4	487610	315	0	0
T5	197477	2782	0	0
T7	110251	1546	0	0
T8	140884	0	0	0
T12	40524	0	0	0
T13	5112	0	0	0
T14	154217	3322	0	0
T15	169154	1	0	0
T17	0	1759	0	0
T19	84057	38	0	0
T27	0	14	0	0
T40	0	12	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	323113447	0	0
T1	79331	76234	0	0
T2	3880	3168	0	0
T3	131100	159333	0	0
T4	487610	263327	0	0
T5	197477	605904	0	0
T7	110251	9328	0	0
T8	140884	90897	0	0
T12	40524	8400	0	0
T13	5112	3186	0	0
T14	154217	6262	0	0