Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T4,T5
1	0	1	Covered	T1,T2,T8
1	1	0	Covered	T12,T4,T5
1	1	1	Covered	T12,T4,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T4,T5
0	1	Covered	T12,T4,T5
1	0	Covered	T4,T5,T19

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T4,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T19

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T4,T5
1	0	Covered	T7,T20
1	1	Covered	T12,T4,T5

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T2,T8,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T3,T12

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T12,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T12

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T12,T4,T5

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T12,T4,T5
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T4,T21,T22
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T4,T23,T24
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T3,T25,T26
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T12,T17,T27
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T3,T4,T5
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T12,T4,T5
TimeoutSt->Phase0St	172	Covered	T12,T4,T5

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T4,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T4,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T4,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T12,T4,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T22,T28
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T8
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T23,T26
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T8
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T25,T26
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T12,T17,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	849	0	0
CheckAccumTrig0_A	2147483647	1998	0	0
CheckAccumTrig1_A	2147483647	78	0	0
CheckClr_A	2147483647	880	0	0
CheckEn_A	2147483647	920603258	0	0
CheckPhase0_A	2147483647	2218	0	0
CheckPhase1_A	2147483647	2160	0	0
CheckPhase2_A	2147483647	2118	0	0
CheckPhase3_A	2147483647	2077	0	0
CheckTimeout0_A	2147483647	2150	0	0
CheckTimeoutSt1_A	2147483647	270492	0	0
CheckTimeoutSt2_A	2147483647	1865	0	0
CheckTimeoutStTrig_A	2147483647	196	0	0
ErrorStAllEscAsserted_A	2147483647	4660	0	0
ErrorStIsTerminal_A	2147483647	3820	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	849	0	0
T9	166536	231	0	0
T10	0	265	0	0
T11	0	121	0	0
T29	0	116	0	0
T30	0	116	0	0
T31	1011336	0	0	0
T32	3872072	0	0	0
T33	233176	0	0	0
T34	1823512	0	0	0
T35	6712	0	0	0
T36	2500624	0	0	0
T37	152516	0	0	0
T38	387640	0	0	0
T39	507928	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1998	0	0
T1	79331	1	0	0
T2	3880	1	0	0
T3	393300	4	0	0
T4	1950440	40	0	0
T5	789908	12	0	0
T7	441004	2	0	0
T8	422652	1	0	0
T12	121572	0	0	0
T13	15336	1	0	0
T14	616868	6	0	0
T15	507462	4	0	0
T16	394293	0	0	0
T17	105568	5	0	0
T19	252171	10	0	0
T27	0	4	0	0
T40	31117	9	0	0
T41	0	3	0	0
T42	0	1	0	0
T43	2776	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	78	0	0
T4	487610	1	0	0
T5	197477	1	0	0
T6	22390	0	0	0
T7	110251	0	0	0
T14	154217	0	0	0
T15	338308	0	0	0
T16	788586	0	0	0
T17	211136	0	0	0
T18	254227	0	0	0
T19	168114	3	0	0
T22	0	1	0	0
T25	0	1	0	0
T40	62234	0	0	0
T43	5552	0	0	0
T44	412603	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	3925	0	0	0
T61	67376	0	0	0
T62	48191	0	0	0
T63	11921	0	0	0
T64	277639	0	0	0
T65	11235	0	0	0
T66	225673	0	0	0
T67	880926	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	880	0	0
T3	262200	2	0	0
T4	1950440	29	0	0
T5	789908	3	0	0
T7	441004	0	0	0
T8	281768	0	0	0
T12	81048	1	0	0
T13	10224	0	0	0
T14	616868	3	0	0
T15	676616	0	0	0
T16	788586	0	0	0
T17	211136	1	0	0
T19	336228	9	0	0
T22	0	1	0	0
T25	0	2	0	0
T40	62234	3	0	0
T41	0	2	0	0
T43	5552	0	0	0
T44	0	9	0	0
T62	0	4	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	3	0	0
T68	0	5	0	0
T69	0	3	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	920603258	0	0
T1	317324	233289	0	0
T2	15520	12506	0	0
T3	524400	562783	0	0
T4	1950440	750057	0	0
T5	789908	802403	0	0
T7	441004	233381	0	0
T8	563536	282351	0	0
T12	162096	77319	0	0
T13	20448	12693	0	0
T14	616868	167811	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2218	0	0
T1	79331	1	0	0
T2	3880	1	0	0
T3	393300	4	0	0
T4	1950440	43	0	0
T5	789908	15	0	0
T7	441004	2	0	0
T8	422652	1	0	0
T12	121572	2	0	0
T13	15336	1	0	0
T14	616868	6	0	0
T15	507462	4	0	0
T16	394293	0	0	0
T17	105568	5	0	0
T19	252171	13	0	0
T27	0	4	0	0
T40	31117	7	0	0
T41	0	3	0	0
T42	0	1	0	0
T43	2776	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2160	0	0
T1	79331	1	0	0
T2	3880	1	0	0
T3	393300	4	0	0
T4	1950440	40	0	0
T5	789908	15	0	0
T7	441004	2	0	0
T8	422652	1	0	0
T12	121572	2	0	0
T13	15336	1	0	0
T14	616868	6	0	0
T15	507462	4	0	0
T16	394293	0	0	0
T17	105568	5	0	0
T19	252171	13	0	0
T27	0	4	0	0
T40	31117	7	0	0
T41	0	3	0	0
T42	0	1	0	0
T43	2776	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2118	0	0
T1	79331	1	0	0
T2	3880	1	0	0
T3	393300	3	0	0
T4	1950440	40	0	0
T5	789908	15	0	0
T7	441004	2	0	0
T8	422652	1	0	0
T12	121572	2	0	0
T13	15336	1	0	0
T14	616868	6	0	0
T15	507462	4	0	0
T16	394293	0	0	0
T17	105568	5	0	0
T19	252171	13	0	0
T27	0	4	0	0
T40	31117	8	0	0
T41	0	3	0	0
T42	0	1	0	0
T43	2776	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2077	0	0
T1	79331	1	0	0
T2	3880	1	0	0
T3	393300	3	0	0
T4	1950440	40	0	0
T5	789908	15	0	0
T7	441004	2	0	0
T8	422652	1	0	0
T12	121572	1	0	0
T13	15336	1	0	0
T14	616868	6	0	0
T15	507462	4	0	0
T16	394293	0	0	0
T17	105568	4	0	0
T19	252171	13	0	0
T27	0	3	0	0
T40	31117	9	0	0
T41	0	3	0	0
T42	0	1	0	0
T43	2776	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2150	0	0
T4	1950440	14	0	0
T5	789908	6	0	0
T7	441004	4	0	0
T12	121572	4	0	0
T13	15336	0	0	0
T14	616868	0	0	0
T15	676616	0	0	0
T16	394293	0	0	0
T17	422272	2	0	0
T19	336228	3	0	0
T22	0	14	0	0
T25	0	1	0	0
T40	124468	0	0	0
T41	0	8	0	0
T43	2776	0	0	0
T44	0	12	0	0
T45	0	1	0	0
T63	0	1	0	0
T66	0	2	0	0
T67	0	4	0	0
T68	0	5	0	0
T71	0	3	0	0
T72	0	1	0	0
T73	0	7	0	0
T74	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	270492	0	0
T4	1950440	1214	0	0
T5	789908	572	0	0
T7	441004	152	0	0
T12	121572	619	0	0
T13	15336	0	0	0
T14	616868	0	0	0
T15	676616	0	0	0
T16	394293	0	0	0
T17	422272	98	0	0
T19	336228	76	0	0
T22	0	1450	0	0
T25	0	2	0	0
T40	124468	0	0	0
T41	0	1275	0	0
T43	2776	0	0	0
T44	0	1487	0	0
T45	0	5	0	0
T63	0	122	0	0
T66	0	179	0	0
T67	0	88	0	0
T68	0	665	0	0
T71	0	344	0	0
T72	0	43	0	0
T73	0	470	0	0
T74	0	46	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1865	0	0
T4	1950440	10	0	0
T5	789908	3	0	0
T7	441004	4	0	0
T12	81048	2	0	0
T13	10224	0	0	0
T14	616868	0	0	0
T15	676616	0	0	0
T16	788586	0	0	0
T17	422272	2	0	0
T19	336228	0	0	0
T22	0	31	0	0
T25	0	1	0	0
T40	124468	0	0	0
T41	0	7	0	0
T43	5552	0	0	0
T44	0	10	0	0
T63	0	1	0	0
T66	0	2	0	0
T67	0	3	0	0
T68	0	3	0	0
T71	0	3	0	0
T72	0	1	0	0
T73	0	6	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	4	0	0
T77	0	7	0	0
T78	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	196	0	0
T4	1950440	2	0	0
T5	789908	1	0	0
T7	441004	0	0	0
T12	81048	2	0	0
T13	10224	0	0	0
T14	616868	0	0	0
T15	676616	0	0	0
T16	788586	0	0	0
T17	422272	0	0	0
T19	336228	0	0	0
T24	0	2	0	0
T25	0	1	0	0
T33	0	1	0	0
T37	0	1	0	0
T40	124468	0	0	0
T41	0	1	0	0
T43	5552	0	0	0
T67	0	1	0	0
T68	0	2	0	0
T71	0	2	0	0
T74	0	1	0	0
T76	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4660	0	0
T9	166536	1339	0	0
T10	0	1330	0	0
T11	0	665	0	0
T29	0	665	0	0
T30	0	661	0	0
T31	1011336	0	0	0
T32	3872072	0	0	0
T33	233176	0	0	0
T34	1823512	0	0	0
T35	6712	0	0	0
T36	2500624	0	0	0
T37	152516	0	0	0
T38	387640	0	0	0
T39	507928	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3820	0	0
T9	166536	1099	0	0
T10	0	1090	0	0
T11	0	545	0	0
T29	0	545	0	0
T30	0	541	0	0
T31	1011336	0	0	0
T32	3872072	0	0	0
T33	233176	0	0	0
T34	1823512	0	0	0
T35	6712	0	0	0
T36	2500624	0	0	0
T37	152516	0	0	0
T38	387640	0	0	0
T39	507928	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	317324	317100	0	0
T2	15520	15196	0	0
T3	524400	524376	0	0
T4	1950440	1948136	0	0
T5	789908	789728	0	0
T7	441004	440984	0	0
T8	563536	563236	0	0
T12	162096	161764	0	0
T13	20448	20176	0	0
T14	616868	616844	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	317324	317100	0	0
T2	15520	15196	0	0
T3	524400	524376	0	0
T4	1950440	1948136	0	0
T5	789908	789728	0	0
T7	441004	440984	0	0
T8	563536	563236	0	0
T12	162096	161764	0	0
T13	20448	20176	0	0
T14	616868	616844	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T4,T5
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T12,T4,T5
1	1	1	Covered	T12,T4,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T4,T19
0	1	Covered	T12,T71,T74
1	0	Covered	T19,T49,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T4,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T19,T49,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T4,T19
1	0	Not Covered
1	1	Covered	T12,T71,T74

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T2,T8,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T8,T4
1	Covered	T1,T3,T12

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19,T17,T44

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T40

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T8
TerminalSt	249	Covered	T1,T2,T8
TimeoutSt	159	Covered	T12,T4,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T12,T4,T19
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T86,T87,T88
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T4,T24,T49
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T3,T26,T89
Phase2St->Phase3St	233	Covered	T1,T2,T8
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T25,T90,T91
Phase3St->TerminalSt	249	Covered	T1,T2,T8
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T5,T19
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T41,T44
TimeoutSt->Phase0St	172	Covered	T12,T19,T71

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T4,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T19,T71
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T4,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T41,T44
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T87,T56,T92
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T8
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T49,T93
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T8
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T26,T89
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T8
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T90,T91
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T8,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T19,T40
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T8
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	538519207	213	0	0
CheckAccumTrig0_A	538519207	415	0	0
CheckAccumTrig1_A	538519207	10	0	0
CheckClr_A	538519207	173	0	0
CheckEn_A	538302192	212680772	0	0
CheckPhase0_A	538519207	482	0	0
CheckPhase1_A	538519207	468	0	0
CheckPhase2_A	538519207	461	0	0
CheckPhase3_A	538519207	457	0	0
CheckTimeout0_A	538519207	354	0	0
CheckTimeoutSt1_A	538519207	50911	0	0
CheckTimeoutSt2_A	538519207	279	0	0
CheckTimeoutStTrig_A	538519207	64	0	0
ErrorStAllEscAsserted_A	538519207	1135	0	0
ErrorStIsTerminal_A	538519207	925	0	0
EscStateOut_A	538300810	538236448	0	0
u_state_regs_A	538519207	538365906	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	213	0	0
T9	41634	68	0	0
T10	0	57	0	0
T11	0	32	0	0
T29	0	33	0	0
T30	0	23	0	0
T31	252834	0	0	0
T32	968018	0	0	0
T33	58294	0	0	0
T34	455878	0	0	0
T35	1678	0	0	0
T36	625156	0	0	0
T37	38129	0	0	0
T38	96910	0	0	0
T39	126982	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	415	0	0
T1	79331	1	0	0
T2	3880	1	0	0
T3	131100	1	0	0
T4	487610	12	0	0
T5	197477	3	0	0
T7	110251	0	0	0
T8	140884	1	0	0
T12	40524	0	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	0	1	0	0
T17	0	1	0	0
T19	0	7	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	10	0	0
T6	22390	0	0	0
T15	169154	0	0	0
T16	394293	0	0	0
T17	105568	0	0	0
T18	254227	0	0	0
T19	84057	3	0	0
T40	31117	0	0	0
T43	2776	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	3925	0	0	0
T61	67376	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	173	0	0
T3	131100	1	0	0
T4	487610	9	0	0
T5	197477	0	0	0
T7	110251	0	0	0
T8	140884	0	0	0
T12	40524	0	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T19	84057	9	0	0
T25	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T67	0	2	0	0
T69	0	3	0	0
T70	0	1	0	0
T72	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538302192	212680772	0	0
T1	79331	599	0	0
T2	3880	3110	0	0
T3	131100	129453	0	0
T4	487610	415285	0	0
T5	197477	336563	0	0
T7	110251	110246	0	0
T8	140884	9641	0	0
T12	40524	15007	0	0
T13	5112	3166	0	0
T14	154217	153907	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	482	0	0
T1	79331	1	0	0
T2	3880	1	0	0
T3	131100	1	0	0
T4	487610	12	0	0
T5	197477	3	0	0
T7	110251	0	0	0
T8	140884	1	0	0
T12	40524	1	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	0	1	0	0
T17	0	1	0	0
T19	0	10	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	468	0	0
T1	79331	1	0	0
T2	3880	1	0	0
T3	131100	1	0	0
T4	487610	11	0	0
T5	197477	3	0	0
T7	110251	0	0	0
T8	140884	1	0	0
T12	40524	1	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	0	1	0	0
T17	0	1	0	0
T19	0	10	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	461	0	0
T1	79331	1	0	0
T2	3880	1	0	0
T3	131100	0	0	0
T4	487610	11	0	0
T5	197477	3	0	0
T7	110251	0	0	0
T8	140884	1	0	0
T12	40524	1	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	0	1	0	0
T17	0	1	0	0
T19	0	10	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	457	0	0
T1	79331	1	0	0
T2	3880	1	0	0
T3	131100	0	0	0
T4	487610	11	0	0
T5	197477	3	0	0
T7	110251	0	0	0
T8	140884	1	0	0
T12	40524	1	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	0	1	0	0
T17	0	1	0	0
T19	0	10	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	354	0	0
T4	487610	4	0	0
T5	197477	0	0	0
T7	110251	0	0	0
T12	40524	1	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T17	105568	0	0	0
T19	84057	3	0	0
T22	0	9	0	0
T40	31117	0	0	0
T41	0	2	0	0
T44	0	1	0	0
T68	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T74	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	50911	0	0
T4	487610	252	0	0
T5	197477	0	0	0
T7	110251	0	0	0
T12	40524	124	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T17	105568	0	0	0
T19	84057	76	0	0
T22	0	842	0	0
T40	31117	0	0	0
T41	0	334	0	0
T44	0	187	0	0
T68	0	188	0	0
T71	0	305	0	0
T72	0	43	0	0
T74	0	46	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	279	0	0
T4	487610	4	0	0
T5	197477	0	0	0
T7	110251	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T16	394293	0	0	0
T17	105568	0	0	0
T19	84057	0	0	0
T22	0	9	0	0
T40	31117	0	0	0
T41	0	2	0	0
T43	2776	0	0	0
T44	0	1	0	0
T68	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T78	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	64	0	0
T4	487610	0	0	0
T5	197477	0	0	0
T7	110251	0	0	0
T12	40524	1	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T17	105568	0	0	0
T19	84057	0	0	0
T24	0	1	0	0
T33	0	1	0	0
T40	31117	0	0	0
T71	0	1	0	0
T74	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	1135	0	0
T9	41634	336	0	0
T10	0	318	0	0
T11	0	164	0	0
T29	0	167	0	0
T30	0	150	0	0
T31	252834	0	0	0
T32	968018	0	0	0
T33	58294	0	0	0
T34	455878	0	0	0
T35	1678	0	0	0
T36	625156	0	0	0
T37	38129	0	0	0
T38	96910	0	0	0
T39	126982	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	925	0	0
T9	41634	276	0	0
T10	0	258	0	0
T11	0	134	0	0
T29	0	137	0	0
T30	0	120	0	0
T31	252834	0	0	0
T32	968018	0	0	0
T33	58294	0	0	0
T34	455878	0	0	0
T35	1678	0	0	0
T36	625156	0	0	0
T37	38129	0	0	0
T38	96910	0	0	0
T39	126982	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538300810	538236448	0	0
T1	79331	79275	0	0
T2	3880	3799	0	0
T3	131100	131094	0	0
T4	487610	487034	0	0
T5	197477	197432	0	0
T7	110251	110246	0	0
T8	140884	140809	0	0
T12	40524	40441	0	0
T13	5112	5044	0	0
T14	154217	154211	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	538365906	0	0
T1	79331	79275	0	0
T2	3880	3799	0	0
T3	131100	131094	0	0
T4	487610	487034	0	0
T5	197477	197432	0	0
T7	110251	110246	0	0
T8	140884	140809	0	0
T12	40524	40441	0	0
T13	5112	5044	0	0
T14	154217	154211	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T5,T14
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T14

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T13,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T14

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T7
1	0	1	Covered	T4,T5,T14
1	1	0	Covered	T12,T4,T5
1	1	1	Covered	T4,T41,T44

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T41,T44
0	1	Covered	T4,T67,T78
1	0	Covered	T44,T45,T25

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T41,T44
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T44,T45,T25

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T41,T44
1	0	Not Covered
1	1	Covered	T4,T67,T78

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T14
1	Covered	T4,T5,T44

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T19
1	Covered	T14,T27,T41

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T14
1	Covered	T4,T5,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T14
1	Covered	T4,T15,T41

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T5,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T5,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T14,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T5,T14

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T5,T14
Phase1St	198	Covered	T4,T5,T14
Phase2St	215	Covered	T4,T5,T14
Phase3St	233	Covered	T4,T5,T14
TerminalSt	249	Covered	T4,T5,T14
TimeoutSt	159	Covered	T4,T41,T44

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T4,T5,T14
IdleSt->TimeoutSt	159	Covered	T4,T41,T44
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T21,T94,T28
Phase0St->Phase1St	198	Covered	T4,T5,T14
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T4,T23,T26
Phase1St->Phase2St	215	Covered	T4,T5,T14
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T25,T48,T90
Phase2St->Phase3St	233	Covered	T4,T5,T14
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T95,T96,T97
Phase3St->TerminalSt	249	Covered	T4,T5,T14
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T5,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T41,T44
TimeoutSt->Phase0St	172	Covered	T4,T44,T67

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T14
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T41,T44
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T44,T67
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T41,T44
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T41,T44
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T98,T99
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T5,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T5,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T23,T26
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T5,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T5,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T25,T48,T90
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T5,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T5,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T95,T96,T97
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T5,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T5,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T14,T40
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	538519207	221	0	0
CheckAccumTrig0_A	538519207	395	0	0
CheckAccumTrig1_A	538519207	12	0	0
CheckClr_A	538519207	145	0	0
CheckEn_A	538302192	242358238	0	0
CheckPhase0_A	538519207	427	0	0
CheckPhase1_A	538519207	419	0	0
CheckPhase2_A	538519207	414	0	0
CheckPhase3_A	538519207	407	0	0
CheckTimeout0_A	538519207	721	0	0
CheckTimeoutSt1_A	538519207	90700	0	0
CheckTimeoutSt2_A	538519207	668	0	0
CheckTimeoutStTrig_A	538519207	36	0	0
ErrorStAllEscAsserted_A	538519207	1159	0	0
ErrorStIsTerminal_A	538519207	949	0	0
EscStateOut_A	538300810	538236448	0	0
u_state_regs_A	538519207	538365906	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	221	0	0
T9	41634	39	0	0
T10	0	80	0	0
T11	0	30	0	0
T29	0	31	0	0
T30	0	41	0	0
T31	252834	0	0	0
T32	968018	0	0	0
T33	58294	0	0	0
T34	455878	0	0	0
T35	1678	0	0	0
T36	625156	0	0	0
T37	38129	0	0	0
T38	96910	0	0	0
T39	126982	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	395	0	0
T4	487610	9	0	0
T5	197477	2	0	0
T7	110251	0	0	0
T14	154217	4	0	0
T15	169154	1	0	0
T16	394293	0	0	0
T17	105568	1	0	0
T19	84057	1	0	0
T27	0	1	0	0
T40	31117	3	0	0
T41	0	3	0	0
T42	0	1	0	0
T43	2776	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	12	0	0
T25	0	1	0	0
T44	412603	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T56	0	1	0	0
T62	48191	0	0	0
T63	11921	0	0	0
T64	277639	0	0	0
T65	11235	0	0	0
T66	225673	0	0	0
T67	880926	0	0	0
T68	88229	0	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	19880	0	0	0
T106	93231	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	145	0	0
T4	487610	6	0	0
T5	197477	0	0	0
T7	110251	0	0	0
T14	154217	3	0	0
T15	169154	0	0	0
T16	394293	0	0	0
T17	105568	0	0	0
T19	84057	0	0	0
T22	0	1	0	0
T25	0	1	0	0
T40	31117	2	0	0
T43	2776	0	0	0
T44	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	2	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538302192	242358238	0	0
T1	79331	79274	0	0
T2	3880	3143	0	0
T3	131100	131094	0	0
T4	487610	49117	0	0
T5	197477	163559	0	0
T7	110251	110046	0	0
T8	140884	140808	0	0
T12	40524	40440	0	0
T13	5112	3181	0	0
T14	154217	3825	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	427	0	0
T4	487610	10	0	0
T5	197477	2	0	0
T7	110251	0	0	0
T14	154217	4	0	0
T15	169154	1	0	0
T16	394293	0	0	0
T17	105568	1	0	0
T19	84057	1	0	0
T27	0	1	0	0
T40	31117	3	0	0
T41	0	3	0	0
T42	0	1	0	0
T43	2776	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	419	0	0
T4	487610	9	0	0
T5	197477	2	0	0
T7	110251	0	0	0
T14	154217	4	0	0
T15	169154	1	0	0
T16	394293	0	0	0
T17	105568	1	0	0
T19	84057	1	0	0
T27	0	1	0	0
T40	31117	3	0	0
T41	0	3	0	0
T42	0	1	0	0
T43	2776	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	414	0	0
T4	487610	9	0	0
T5	197477	2	0	0
T7	110251	0	0	0
T14	154217	4	0	0
T15	169154	1	0	0
T16	394293	0	0	0
T17	105568	1	0	0
T19	84057	1	0	0
T27	0	1	0	0
T40	31117	3	0	0
T41	0	3	0	0
T42	0	1	0	0
T43	2776	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	407	0	0
T4	487610	9	0	0
T5	197477	2	0	0
T7	110251	0	0	0
T14	154217	4	0	0
T15	169154	1	0	0
T16	394293	0	0	0
T17	105568	1	0	0
T19	84057	1	0	0
T27	0	1	0	0
T40	31117	3	0	0
T41	0	3	0	0
T42	0	1	0	0
T43	2776	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	721	0	0
T4	487610	3	0	0
T5	197477	0	0	0
T7	110251	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T16	394293	0	0	0
T17	105568	0	0	0
T19	84057	0	0	0
T22	0	5	0	0
T25	0	1	0	0
T40	31117	0	0	0
T41	0	1	0	0
T43	2776	0	0	0
T44	0	6	0	0
T45	0	1	0	0
T63	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T71	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	90700	0	0
T4	487610	292	0	0
T5	197477	0	0	0
T7	110251	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T16	394293	0	0	0
T17	105568	0	0	0
T19	84057	0	0	0
T22	0	608	0	0
T25	0	2	0	0
T40	31117	0	0	0
T41	0	71	0	0
T43	2776	0	0	0
T44	0	774	0	0
T45	0	5	0	0
T63	0	122	0	0
T66	0	114	0	0
T67	0	24	0	0
T71	0	39	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	668	0	0
T4	487610	2	0	0
T5	197477	0	0	0
T7	110251	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T16	394293	0	0	0
T17	105568	0	0	0
T19	84057	0	0	0
T22	0	5	0	0
T40	31117	0	0	0
T41	0	1	0	0
T43	2776	0	0	0
T44	0	5	0	0
T63	0	1	0	0
T66	0	1	0	0
T71	0	1	0	0
T74	0	2	0	0
T76	0	3	0	0
T77	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	36	0	0
T4	487610	1	0	0
T5	197477	0	0	0
T7	110251	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T16	394293	0	0	0
T17	105568	0	0	0
T19	84057	0	0	0
T24	0	1	0	0
T28	0	1	0	0
T37	0	1	0	0
T40	31117	0	0	0
T43	2776	0	0	0
T49	0	1	0	0
T67	0	1	0	0
T78	0	1	0	0
T83	0	1	0	0
T85	0	1	0	0
T107	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	1159	0	0
T9	41634	299	0	0
T10	0	331	0	0
T11	0	164	0	0
T29	0	202	0	0
T30	0	163	0	0
T31	252834	0	0	0
T32	968018	0	0	0
T33	58294	0	0	0
T34	455878	0	0	0
T35	1678	0	0	0
T36	625156	0	0	0
T37	38129	0	0	0
T38	96910	0	0	0
T39	126982	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	949	0	0
T9	41634	239	0	0
T10	0	271	0	0
T11	0	134	0	0
T29	0	172	0	0
T30	0	133	0	0
T31	252834	0	0	0
T32	968018	0	0	0
T33	58294	0	0	0
T34	455878	0	0	0
T35	1678	0	0	0
T36	625156	0	0	0
T37	38129	0	0	0
T38	96910	0	0	0
T39	126982	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538300810	538236448	0	0
T1	79331	79275	0	0
T2	3880	3799	0	0
T3	131100	131094	0	0
T4	487610	487034	0	0
T5	197477	197432	0	0
T7	110251	110246	0	0
T8	140884	140809	0	0
T12	40524	40441	0	0
T13	5112	5044	0	0
T14	154217	154211	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	538365906	0	0
T1	79331	79275	0	0
T2	3880	3799	0	0
T3	131100	131094	0	0
T4	487610	487034	0	0
T5	197477	197432	0	0
T7	110251	110246	0	0
T8	140884	140809	0	0
T12	40524	40441	0	0
T13	5112	5044	0	0
T14	154217	154211	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T12,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T12,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T13,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T4,T5
1	0	1	Covered	T1,T8,T13
1	1	0	Covered	T12,T4,T5
1	1	1	Covered	T12,T4,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T4,T5
0	1	Covered	T12,T4,T5
1	0	Covered	T4,T5,T44

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T44

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T4,T5
1	0	Covered	T7
1	1	Covered	T12,T4,T5

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T4
1	Covered	T13,T4,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T13
1	Covered	T4,T5,T15

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T13
1	Covered	T19,T40,T41

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T13,T4,T5
1	Covered	T3,T12,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T13,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T12,T13,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T12,T13
Phase1St	198	Covered	T3,T12,T13
Phase2St	215	Covered	T3,T12,T13
Phase3St	233	Covered	T3,T12,T13
TerminalSt	249	Covered	T3,T13,T4
TimeoutSt	159	Covered	T12,T4,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T3,T13,T4
IdleSt->TimeoutSt	159	Covered	T12,T4,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T4,T21,T22
Phase0St->Phase1St	198	Covered	T3,T12,T13
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T108,T94,T109
Phase1St->Phase2St	215	Covered	T3,T12,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T110,T52,T111
Phase2St->Phase3St	233	Covered	T3,T12,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T12,T17,T41
Phase3St->TerminalSt	249	Covered	T3,T13,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T12,T4,T7
TimeoutSt->Phase0St	172	Covered	T12,T4,T5

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T4,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T4,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T4,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T12,T4,T7
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T22,T112
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T12,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T12,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T108,T109,T90
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T12,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T12,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T110,T52,T111
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T12,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T12,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T12,T17,T41
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T13,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T12,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T13,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	538519207	187	0	0
CheckAccumTrig0_A	538519207	744	0	0
CheckAccumTrig1_A	538519207	37	0	0
CheckClr_A	538519207	366	0	0
CheckEn_A	538302192	218852325	0	0
CheckPhase0_A	538519207	815	0	0
CheckPhase1_A	538519207	797	0	0
CheckPhase2_A	538519207	773	0	0
CheckPhase3_A	538519207	753	0	0
CheckTimeout0_A	538519207	641	0	0
CheckTimeoutSt1_A	538519207	76827	0	0
CheckTimeoutSt2_A	538519207	548	0	0
CheckTimeoutStTrig_A	538519207	53	0	0
ErrorStAllEscAsserted_A	538519207	1174	0	0
ErrorStIsTerminal_A	538519207	964	0	0
EscStateOut_A	538300810	538236448	0	0
u_state_regs_A	538519207	538365906	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	187	0	0
T9	41634	46	0	0
T10	0	72	0	0
T11	0	16	0	0
T29	0	25	0	0
T30	0	28	0	0
T31	252834	0	0	0
T32	968018	0	0	0
T33	58294	0	0	0
T34	455878	0	0	0
T35	1678	0	0	0
T36	625156	0	0	0
T37	38129	0	0	0
T38	96910	0	0	0
T39	126982	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	744	0	0
T3	131100	2	0	0
T4	487610	16	0	0
T5	197477	4	0	0
T7	110251	1	0	0
T8	140884	0	0	0
T12	40524	0	0	0
T13	5112	1	0	0
T14	154217	1	0	0
T15	169154	1	0	0
T17	0	2	0	0
T19	84057	1	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	37	0	0
T4	487610	1	0	0
T5	197477	1	0	0
T7	110251	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T16	394293	0	0	0
T17	105568	0	0	0
T19	84057	0	0	0
T22	0	1	0	0
T40	31117	0	0	0
T43	2776	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	366	0	0
T3	131100	1	0	0
T4	487610	14	0	0
T5	197477	3	0	0
T7	110251	0	0	0
T8	140884	0	0	0
T12	40524	1	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T17	0	1	0	0
T19	84057	0	0	0
T41	0	2	0	0
T44	0	6	0	0
T62	0	4	0	0
T65	0	1	0	0
T68	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538302192	218852325	0	0
T1	79331	77183	0	0
T2	3880	3085	0	0
T3	131100	142903	0	0
T4	487610	26444	0	0
T5	197477	15872	0	0
T7	110251	3761	0	0
T8	140884	41005	0	0
T12	40524	13472	0	0
T13	5112	3160	0	0
T14	154217	3817	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	815	0	0
T3	131100	2	0	0
T4	487610	17	0	0
T5	197477	6	0	0
T7	110251	1	0	0
T8	140884	0	0	0
T12	40524	1	0	0
T13	5112	1	0	0
T14	154217	1	0	0
T15	169154	1	0	0
T17	0	2	0	0
T19	84057	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	797	0	0
T3	131100	2	0	0
T4	487610	17	0	0
T5	197477	6	0	0
T7	110251	1	0	0
T8	140884	0	0	0
T12	40524	1	0	0
T13	5112	1	0	0
T14	154217	1	0	0
T15	169154	1	0	0
T17	0	2	0	0
T19	84057	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	773	0	0
T3	131100	2	0	0
T4	487610	17	0	0
T5	197477	6	0	0
T7	110251	1	0	0
T8	140884	0	0	0
T12	40524	1	0	0
T13	5112	1	0	0
T14	154217	1	0	0
T15	169154	1	0	0
T17	0	2	0	0
T19	84057	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	753	0	0
T3	131100	2	0	0
T4	487610	17	0	0
T5	197477	6	0	0
T7	110251	1	0	0
T8	140884	0	0	0
T12	40524	0	0	0
T13	5112	1	0	0
T14	154217	1	0	0
T15	169154	1	0	0
T17	0	1	0	0
T19	84057	1	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	641	0	0
T4	487610	5	0	0
T5	197477	2	0	0
T7	110251	1	0	0
T12	40524	2	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T17	105568	1	0	0
T19	84057	0	0	0
T40	31117	0	0	0
T41	0	1	0	0
T44	0	4	0	0
T66	0	1	0	0
T67	0	2	0	0
T68	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	76827	0	0
T4	487610	239	0	0
T5	197477	373	0	0
T7	110251	35	0	0
T12	40524	327	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T17	105568	46	0	0
T19	84057	0	0	0
T40	31117	0	0	0
T41	0	137	0	0
T44	0	371	0	0
T66	0	65	0	0
T67	0	51	0	0
T68	0	228	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	548	0	0
T4	487610	3	0	0
T5	197477	0	0	0
T7	110251	1	0	0
T12	40524	1	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T17	105568	1	0	0
T19	84057	0	0	0
T22	0	17	0	0
T25	0	1	0	0
T40	31117	0	0	0
T44	0	3	0	0
T66	0	1	0	0
T67	0	2	0	0
T71	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	53	0	0
T4	487610	1	0	0
T5	197477	1	0	0
T7	110251	0	0	0
T12	40524	1	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T17	105568	0	0	0
T19	84057	0	0	0
T25	0	1	0	0
T40	31117	0	0	0
T41	0	1	0	0
T68	0	2	0	0
T71	0	1	0	0
T76	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	1174	0	0
T9	41634	339	0	0
T10	0	349	0	0
T11	0	173	0	0
T29	0	145	0	0
T30	0	168	0	0
T31	252834	0	0	0
T32	968018	0	0	0
T33	58294	0	0	0
T34	455878	0	0	0
T35	1678	0	0	0
T36	625156	0	0	0
T37	38129	0	0	0
T38	96910	0	0	0
T39	126982	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	964	0	0
T9	41634	279	0	0
T10	0	289	0	0
T11	0	143	0	0
T29	0	115	0	0
T30	0	138	0	0
T31	252834	0	0	0
T32	968018	0	0	0
T33	58294	0	0	0
T34	455878	0	0	0
T35	1678	0	0	0
T36	625156	0	0	0
T37	38129	0	0	0
T38	96910	0	0	0
T39	126982	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538300810	538236448	0	0
T1	79331	79275	0	0
T2	3880	3799	0	0
T3	131100	131094	0	0
T4	487610	487034	0	0
T5	197477	197432	0	0
T7	110251	110246	0	0
T8	140884	140809	0	0
T12	40524	40441	0	0
T13	5112	5044	0	0
T14	154217	154211	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	538365906	0	0
T1	79331	79275	0	0
T2	3880	3799	0	0
T3	131100	131094	0	0
T4	487610	487034	0	0
T5	197477	197432	0	0
T7	110251	110246	0	0
T8	140884	140809	0	0
T12	40524	40441	0	0
T13	5112	5044	0	0
T14	154217	154211	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T12,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T12,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T4,T5
1	0	1	Covered	T1,T14,T42
1	1	0	Covered	T12,T4,T5
1	1	1	Covered	T12,T4,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T4,T5
0	1	Covered	T4,T73,T71
1	0	Covered	T5,T80,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T80,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T4,T5
1	0	Covered	T20
1	1	Covered	T4,T73,T71

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T5,T40,T113

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T14
1	Covered	T3,T5,T7

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T4,T5,T14

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T4,T5,T15

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T5,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T4,T5
Phase1St	198	Covered	T3,T4,T5
Phase2St	215	Covered	T3,T4,T5
Phase3St	233	Covered	T3,T4,T5
TerminalSt	249	Covered	T3,T4,T5
TimeoutSt	159	Covered	T12,T4,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T3,T4,T5
IdleSt->TimeoutSt	159	Covered	T12,T4,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T21,T114,T115
Phase0St->Phase1St	198	Covered	T3,T4,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T4,T49,T116
Phase1St->Phase2St	215	Covered	T3,T4,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T26,T90,T117
Phase2St->Phase3St	233	Covered	T3,T4,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T27,T118,T33
Phase3St->TerminalSt	249	Covered	T3,T4,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T5,T40
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T12,T4,T5
TimeoutSt->Phase0St	172	Covered	T4,T5,T73

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T4,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T73
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T4,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T12,T4,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T91,T119,T120
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T49,T116
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T90,T117
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T118,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T40
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	538519207	228	0	0
CheckAccumTrig0_A	538519207	444	0	0
CheckAccumTrig1_A	538519207	19	0	0
CheckClr_A	538519207	196	0	0
CheckEn_A	538302192	246711923	0	0
CheckPhase0_A	538519207	494	0	0
CheckPhase1_A	538519207	476	0	0
CheckPhase2_A	538519207	470	0	0
CheckPhase3_A	538519207	460	0	0
CheckTimeout0_A	538519207	434	0	0
CheckTimeoutSt1_A	538519207	52054	0	0
CheckTimeoutSt2_A	538519207	370	0	0
CheckTimeoutStTrig_A	538519207	43	0	0
ErrorStAllEscAsserted_A	538519207	1192	0	0
ErrorStIsTerminal_A	538519207	982	0	0
EscStateOut_A	538300810	538236448	0	0
u_state_regs_A	538519207	538365906	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	228	0	0
T9	41634	78	0	0
T10	0	56	0	0
T11	0	43	0	0
T29	0	27	0	0
T30	0	24	0	0
T31	252834	0	0	0
T32	968018	0	0	0
T33	58294	0	0	0
T34	455878	0	0	0
T35	1678	0	0	0
T36	625156	0	0	0
T37	38129	0	0	0
T38	96910	0	0	0
T39	126982	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	444	0	0
T3	131100	1	0	0
T4	487610	3	0	0
T5	197477	3	0	0
T7	110251	1	0	0
T8	140884	0	0	0
T12	40524	0	0	0
T13	5112	0	0	0
T14	154217	1	0	0
T15	169154	1	0	0
T17	0	1	0	0
T19	84057	1	0	0
T27	0	3	0	0
T40	0	4	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	19	0	0
T5	197477	1	0	0
T7	110251	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T16	394293	0	0	0
T17	105568	0	0	0
T18	254227	0	0	0
T19	84057	0	0	0
T40	31117	0	0	0
T43	2776	0	0	0
T50	0	1	0	0
T52	0	1	0	0
T80	0	1	0	0
T121	0	1	0	0
T122	0	2	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	196	0	0
T4	487610	2	0	0
T5	197477	1	0	0
T7	110251	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T16	394293	0	0	0
T17	105568	0	0	0
T19	84057	0	0	0
T27	0	2	0	0
T40	31117	3	0	0
T43	2776	0	0	0
T70	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0
T118	0	1	0	0
T127	0	3	0	0
T128	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538302192	246711923	0	0
T1	79331	76233	0	0
T2	3880	3168	0	0
T3	131100	159333	0	0
T4	487610	259211	0	0
T5	197477	286409	0	0
T7	110251	9328	0	0
T8	140884	90897	0	0
T12	40524	8400	0	0
T13	5112	3186	0	0
T14	154217	6262	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	494	0	0
T3	131100	1	0	0
T4	487610	4	0	0
T5	197477	4	0	0
T7	110251	1	0	0
T8	140884	0	0	0
T12	40524	0	0	0
T13	5112	0	0	0
T14	154217	1	0	0
T15	169154	1	0	0
T17	0	1	0	0
T19	84057	1	0	0
T27	0	3	0	0
T40	0	4	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	476	0	0
T3	131100	1	0	0
T4	487610	3	0	0
T5	197477	4	0	0
T7	110251	1	0	0
T8	140884	0	0	0
T12	40524	0	0	0
T13	5112	0	0	0
T14	154217	1	0	0
T15	169154	1	0	0
T17	0	1	0	0
T19	84057	1	0	0
T27	0	3	0	0
T40	0	4	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	470	0	0
T3	131100	1	0	0
T4	487610	3	0	0
T5	197477	4	0	0
T7	110251	1	0	0
T8	140884	0	0	0
T12	40524	0	0	0
T13	5112	0	0	0
T14	154217	1	0	0
T15	169154	1	0	0
T17	0	1	0	0
T19	84057	1	0	0
T27	0	3	0	0
T40	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	460	0	0
T3	131100	1	0	0
T4	487610	3	0	0
T5	197477	4	0	0
T7	110251	1	0	0
T8	140884	0	0	0
T12	40524	0	0	0
T13	5112	0	0	0
T14	154217	1	0	0
T15	169154	1	0	0
T17	0	1	0	0
T19	84057	1	0	0
T27	0	2	0	0
T40	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	434	0	0
T4	487610	2	0	0
T5	197477	4	0	0
T7	110251	3	0	0
T12	40524	1	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T17	105568	1	0	0
T19	84057	0	0	0
T40	31117	0	0	0
T41	0	4	0	0
T44	0	1	0	0
T67	0	1	0	0
T68	0	2	0	0
T73	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	52054	0	0
T4	487610	431	0	0
T5	197477	199	0	0
T7	110251	117	0	0
T12	40524	168	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T17	105568	52	0	0
T19	84057	0	0	0
T40	31117	0	0	0
T41	0	733	0	0
T44	0	155	0	0
T67	0	13	0	0
T68	0	249	0	0
T73	0	470	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	370	0	0
T4	487610	1	0	0
T5	197477	3	0	0
T7	110251	3	0	0
T12	40524	1	0	0
T13	5112	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T17	105568	1	0	0
T19	84057	0	0	0
T40	31117	0	0	0
T41	0	4	0	0
T44	0	1	0	0
T67	0	1	0	0
T68	0	2	0	0
T73	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	43	0	0
T4	487610	1	0	0
T5	197477	0	0	0
T7	110251	0	0	0
T14	154217	0	0	0
T15	169154	0	0	0
T16	394293	0	0	0
T17	105568	0	0	0
T19	84057	0	0	0
T22	0	1	0	0
T40	31117	0	0	0
T43	2776	0	0	0
T49	0	4	0	0
T71	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T90	0	2	0	0
T108	0	1	0	0
T109	0	1	0	0
T129	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	1192	0	0
T9	41634	365	0	0
T10	0	332	0	0
T11	0	164	0	0
T29	0	151	0	0
T30	0	180	0	0
T31	252834	0	0	0
T32	968018	0	0	0
T33	58294	0	0	0
T34	455878	0	0	0
T35	1678	0	0	0
T36	625156	0	0	0
T37	38129	0	0	0
T38	96910	0	0	0
T39	126982	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	982	0	0
T9	41634	305	0	0
T10	0	272	0	0
T11	0	134	0	0
T29	0	121	0	0
T30	0	150	0	0
T31	252834	0	0	0
T32	968018	0	0	0
T33	58294	0	0	0
T34	455878	0	0	0
T35	1678	0	0	0
T36	625156	0	0	0
T37	38129	0	0	0
T38	96910	0	0	0
T39	126982	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538300810	538236448	0	0
T1	79331	79275	0	0
T2	3880	3799	0	0
T3	131100	131094	0	0
T4	487610	487034	0	0
T5	197477	197432	0	0
T7	110251	110246	0	0
T8	140884	140809	0	0
T12	40524	40441	0	0
T13	5112	5044	0	0
T14	154217	154211	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538519207	538365906	0	0
T1	79331	79275	0	0
T2	3880	3799	0	0
T3	131100	131094	0	0
T4	487610	487034	0	0
T5	197477	197432	0	0
T7	110251	110246	0	0
T8	140884	140809	0	0
T12	40524	40441	0	0
T13	5112	5044	0	0
T14	154217	154211	0	0