Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T73,T206,T207
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2123556948	13797	0	0
DisabledNoTrigBkwd_A	2123556948	665401	0	0
DisabledNoTrigFwd_A	2123556948	1137016625	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	13797	0	0
T26	22534	0	0	0
T52	472757	0	0	0
T73	0	262	0	0
T91	116044	0	0	0
T92	288177	0	0	0
T122	343480	0	0	0
T206	928	215	0	0
T207	0	647	0	0
T208	3165	708	0	0
T209	2666	433	0	0
T210	4939	1401	0	0
T211	0	769	0	0
T212	0	1748	0	0
T213	0	536	0	0
T214	0	223	0	0
T215	0	603	0	0
T216	0	823	0	0
T217	0	824	0	0
T218	0	716	0	0
T219	0	656	0	0
T220	0	378	0	0
T221	0	870	0	0
T222	0	637	0	0
T223	0	705	0	0
T224	0	643	0	0
T225	42734	0	0	0
T226	145008	0	0	0
T227	947676	0	0	0
T228	43135	0	0	0
T229	12604	0	0	0
T230	280324	0	0	0
T231	31401	0	0	0
T232	7655	0	0	0
T233	589745	0	0	0
T234	360068	0	0	0
T235	9023	0	0	0
T236	102042	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	665401	0	0
T1	102568	51	0	0
T2	170864	12	0	0
T3	831620	480	0	0
T4	88600	0	0	0
T5	650684	12433	0	0
T6	1806768	159	0	0
T10	338380	150	0	0
T11	1552784	1218	0	0
T16	1454748	3520	0	0
T17	0	2348	0	0
T18	0	13	0	0
T21	250740	53	0	0
T22	0	79	0	0
T33	0	7	0	0
T48	0	118	0	0
T49	0	588	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	1137016625	0	0
T1	102568	28099	0	0
T2	170864	124440	0	0
T3	831620	419685	0	0
T4	88600	8679	0	0
T5	650684	1322328	0	0
T6	1806768	1293702	0	0
T10	338380	181134	0	0
T11	1552784	780645	0	0
T16	1454748	803565	0	0
T21	250740	192048	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T5
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T207,T215
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	530889237	2170	0	0
DisabledNoTrigBkwd_A	530889237	161341	0	0
DisabledNoTrigFwd_A	530889237	269214049	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	2170	0	0
T26	22534	0	0	0
T52	472757	0	0	0
T91	116044	0	0	0
T92	288177	0	0	0
T206	928	215	0	0
T207	0	647	0	0
T215	0	603	0	0
T223	0	705	0	0
T225	42734	0	0	0
T226	145008	0	0	0
T227	947676	0	0	0
T228	43135	0	0	0
T229	12604	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	161341	0	0
T1	25642	22	0	0
T2	42716	12	0	0
T3	207905	479	0	0
T4	22150	0	0	0
T5	162671	1948	0	0
T6	451692	79	0	0
T10	84595	0	0	0
T11	388196	0	0	0
T16	363687	2	0	0
T17	0	1162	0	0
T18	0	1	0	0
T21	62685	53	0	0
T33	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	269214049	0	0
T1	25642	2064	0	0
T2	42716	876	0	0
T3	207905	3611	0	0
T4	22150	2145	0	0
T5	162671	447222	0	0
T6	451692	251907	0	0
T10	84595	84520	0	0
T11	388196	386907	0	0
T16	363687	361184	0	0
T21	62685	4218	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T10,T5
1	1	Covered	T1,T3,T10

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T208,T209,T214
1	1	Covered	T1,T3,T10

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T10

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	530889237	2565	0	0
DisabledNoTrigBkwd_A	530889237	130862	0	0
DisabledNoTrigFwd_A	530889237	300863845	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	2565	0	0
T122	343480	0	0	0
T208	3165	708	0	0
T209	2666	433	0	0
T214	0	223	0	0
T216	0	823	0	0
T220	0	378	0	0
T230	280324	0	0	0
T231	31401	0	0	0
T232	7655	0	0	0
T233	589745	0	0	0
T234	360068	0	0	0
T235	9023	0	0	0
T236	102042	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	130862	0	0
T1	25642	3	0	0
T2	42716	0	0	0
T3	207905	1	0	0
T4	22150	0	0	0
T5	162671	34	0	0
T6	451692	51	0	0
T10	84595	70	0	0
T11	388196	0	0	0
T16	363687	15	0	0
T17	0	1167	0	0
T21	62685	0	0	0
T22	0	9	0	0
T48	0	117	0	0
T49	0	7	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	300863845	0	0
T1	25642	13921	0	0
T2	42716	42635	0	0
T3	207905	587	0	0
T4	22150	2161	0	0
T5	162671	153547	0	0
T6	451692	345630	0	0
T10	84595	10513	0	0
T11	388196	387544	0	0
T16	363687	360437	0	0
T21	62685	62610	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T3,T10,T5
1	1	Covered	T1,T3,T10

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T210,T211,T212
1	1	Covered	T1,T3,T10

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	530889237	6911	0	0
DisabledNoTrigBkwd_A	530889237	217983	0	0
DisabledNoTrigFwd_A	530889237	271793995	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	6911	0	0
T55	15974	0	0	0
T210	4939	1401	0	0
T211	0	769	0	0
T212	0	1748	0	0
T217	0	824	0	0
T219	0	656	0	0
T221	0	870	0	0
T224	0	643	0	0
T237	42749	0	0	0
T238	451914	0	0	0
T239	19035	0	0	0
T240	260506	0	0	0
T241	21723	0	0	0
T242	428433	0	0	0
T243	33339	0	0	0
T244	25917	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	217983	0	0
T1	25642	17	0	0
T2	42716	0	0	0
T3	207905	0	0	0
T4	22150	0	0	0
T5	162671	8709	0	0
T6	451692	2	0	0
T10	84595	80	0	0
T11	388196	621	0	0
T16	363687	1887	0	0
T17	0	19	0	0
T18	0	4	0	0
T21	62685	0	0	0
T22	0	41	0	0
T49	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	271793995	0	0
T1	25642	2098	0	0
T2	42716	42635	0	0
T3	207905	207592	0	0
T4	22150	2178	0	0
T5	162671	381807	0	0
T6	451692	389533	0	0
T10	84595	2596	0	0
T11	388196	3087	0	0
T16	363687	30296	0	0
T21	62685	62610	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T10,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T73,T213,T218
1	1	Covered	T1,T10,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	530889237	2151	0	0
DisabledNoTrigBkwd_A	530889237	155215	0	0
DisabledNoTrigFwd_A	530889237	295144736	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	2151	0	0
T12	278041	0	0	0
T19	22797	0	0	0
T20	386661	0	0	0
T23	45157	0	0	0
T31	262733	0	0	0
T34	4483	0	0	0
T35	106626	0	0	0
T64	47469	0	0	0
T73	951	262	0	0
T213	0	536	0	0
T218	0	716	0	0
T222	0	637	0	0
T245	94080	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	155215	0	0
T1	25642	9	0	0
T2	42716	0	0	0
T3	207905	0	0	0
T4	22150	0	0	0
T5	162671	1742	0	0
T6	451692	27	0	0
T10	84595	0	0	0
T11	388196	597	0	0
T16	363687	1616	0	0
T18	0	8	0	0
T21	62685	0	0	0
T22	0	29	0	0
T33	0	2	0	0
T48	0	1	0	0
T49	0	579	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	295144736	0	0
T1	25642	10016	0	0
T2	42716	38294	0	0
T3	207905	207895	0	0
T4	22150	2195	0	0
T5	162671	339752	0	0
T6	451692	306632	0	0
T10	84595	83505	0	0
T11	388196	3107	0	0
T16	363687	51648	0	0
T21	62685	62610	0	0