Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T1,T5,T6
1	1	1	Covered	T5,T6,T22

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T22
0	1	Covered	T6,T23,T24
1	0	Covered	T5,T23,T25

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T22
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T23,T25

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T22
1	0	Covered	T26,T27,T28
1	1	Covered	T6,T23,T24

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T2,T10

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T10,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T5,T6,T22

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T5,T6,T22
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T6,T25,T29
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T5,T18,T30
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T18,T31,T32
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T1,T33,T34
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T5,T6
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T5,T22,T35
TimeoutSt->Phase0St	172	Covered	T5,T6,T20

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T22,T35
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T36,T37
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T18,T30
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T18,T31,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T33,T34
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T5,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2123556948	970	0	0
CheckAccumTrig0_A	2123556948	2295	0	0
CheckAccumTrig1_A	2123556948	104	0	0
CheckClr_A	2123556948	1082	0	0
CheckEn_A	2122042864	885882227	0	0
CheckPhase0_A	2123556948	2530	0	0
CheckPhase1_A	2123556948	2460	0	0
CheckPhase2_A	2123556948	2400	0	0
CheckPhase3_A	2123556948	2357	0	0
CheckTimeout0_A	2123556948	4089	0	0
CheckTimeoutSt1_A	2123556948	493920	0	0
CheckTimeoutSt2_A	2123556948	3763	0	0
CheckTimeoutStTrig_A	2123556948	211	0	0
ErrorStAllEscAsserted_A	2123556948	5150	0	0
ErrorStIsTerminal_A	2123556948	4190	0	0
EscStateOut_A	2122034828	2121751408	0	0
u_state_regs_A	2123556948	2122866688	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	970	0	0
T7	184384	235	0	0
T8	0	233	0	0
T9	0	119	0	0
T37	670692	0	0	0
T38	0	250	0	0
T39	0	133	0	0
T40	2011904	0	0	0
T41	1940536	0	0	0
T42	445080	0	0	0
T43	543628	0	0	0
T44	829692	0	0	0
T45	649244	0	0	0
T46	903848	0	0	0
T47	146884	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	2295	0	0
T1	102568	11	0	0
T2	170864	1	0	0
T3	831620	2	0	0
T4	88600	0	0	0
T5	650684	12	0	0
T6	1806768	8	0	0
T10	338380	2	0	0
T11	1552784	3	0	0
T16	1454748	4	0	0
T17	0	3	0	0
T18	0	3	0	0
T21	250740	1	0	0
T22	0	4	0	0
T33	0	3	0	0
T48	0	2	0	0
T49	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	104	0	0
T5	488013	3	0	0
T6	1355076	0	0	0
T11	1164588	0	0	0
T16	1091061	0	0	0
T17	950526	0	0	0
T18	323007	0	0	0
T20	386661	0	0	0
T21	188055	0	0	0
T22	341811	0	0	0
T23	45157	1	0	0
T24	0	1	0	0
T25	0	4	0	0
T30	157056	0	0	0
T31	262733	0	0	0
T32	407174	0	0	0
T34	4483	0	0	0
T35	106626	0	0	0
T37	0	3	0	0
T41	0	1	0	0
T44	0	1	0	0
T48	431727	0	0	0
T49	141141	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	0	1	0	0
T54	0	4	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	47469	0	0	0
T65	149976	0	0	0
T66	30828	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	1082	0	0
T1	76926	5	0	0
T2	128148	0	0	0
T3	623715	0	0	0
T4	66450	0	0	0
T5	650684	4	0	0
T6	1806768	1	0	0
T10	253785	0	0	0
T11	1552784	1	0	0
T16	1454748	0	0	0
T17	316842	0	0	0
T18	107669	3	0	0
T21	250740	0	0	0
T22	113937	0	0	0
T24	0	3	0	0
T25	0	6	0	0
T29	0	2	0	0
T30	0	2	0	0
T31	0	3	0	0
T32	0	8	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T50	0	8	0	0
T67	0	5	0	0
T68	0	4	0	0
T69	0	1	0	0
T70	0	4	0	0
T71	0	2	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2122042864	885882227	0	0
T1	102568	28098	0	0
T2	170864	124437	0	0
T3	831620	419685	0	0
T4	88600	8675	0	0
T5	650684	1306490	0	0
T6	1806768	1235419	0	0
T10	338380	181132	0	0
T11	1552784	780644	0	0
T16	1454748	94455	0	0
T21	250740	192045	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	2530	0	0
T1	102568	10	0	0
T2	170864	1	0	0
T3	831620	2	0	0
T4	88600	0	0	0
T5	650684	15	0	0
T6	1806768	6	0	0
T10	338380	2	0	0
T11	1552784	3	0	0
T16	1454748	4	0	0
T17	0	3	0	0
T18	0	3	0	0
T21	250740	1	0	0
T22	0	4	0	0
T33	0	3	0	0
T48	0	2	0	0
T49	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	2460	0	0
T1	102568	10	0	0
T2	170864	1	0	0
T3	831620	2	0	0
T4	88600	0	0	0
T5	650684	14	0	0
T6	1806768	6	0	0
T10	338380	2	0	0
T11	1552784	3	0	0
T12	0	1	0	0
T16	1454748	4	0	0
T17	0	3	0	0
T18	0	2	0	0
T21	250740	1	0	0
T22	0	4	0	0
T33	0	3	0	0
T48	0	2	0	0
T49	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	2400	0	0
T1	102568	10	0	0
T2	170864	1	0	0
T3	831620	2	0	0
T4	88600	0	0	0
T5	650684	14	0	0
T6	1806768	6	0	0
T10	338380	2	0	0
T11	1552784	3	0	0
T12	0	1	0	0
T16	1454748	4	0	0
T17	0	3	0	0
T18	0	1	0	0
T21	250740	1	0	0
T22	0	4	0	0
T33	0	4	0	0
T48	0	2	0	0
T49	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	2357	0	0
T1	102568	9	0	0
T2	170864	1	0	0
T3	831620	2	0	0
T4	88600	0	0	0
T5	650684	14	0	0
T6	1806768	6	0	0
T10	338380	2	0	0
T11	1552784	3	0	0
T12	0	1	0	0
T16	1454748	4	0	0
T17	0	3	0	0
T21	250740	1	0	0
T22	0	4	0	0
T33	0	3	0	0
T48	0	2	0	0
T49	0	3	0	0
T73	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	4089	0	0
T5	488013	5	0	0
T6	1806768	2	0	0
T11	1552784	0	0	0
T16	1454748	0	0	0
T17	1267368	0	0	0
T18	430676	0	0	0
T20	0	1	0	0
T21	250740	0	0	0
T22	455748	2	0	0
T23	0	4	0	0
T24	0	24	0	0
T25	0	4	0	0
T29	0	37	0	0
T33	14992	0	0	0
T34	0	3	0	0
T35	0	1	0	0
T48	575636	0	0	0
T49	188188	0	0	0
T50	0	1	0	0
T69	0	1	0	0
T71	0	24	0	0
T72	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	9	0	0
T77	0	10	0	0
T78	0	8	0	0
T79	0	12	0	0
T80	0	20	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	493920	0	0
T5	488013	235	0	0
T6	1806768	270	0	0
T11	1552784	0	0	0
T16	1454748	0	0	0
T17	1267368	0	0	0
T18	430676	0	0	0
T21	250740	0	0	0
T22	455748	118	0	0
T23	0	692	0	0
T24	0	4093	0	0
T25	0	19	0	0
T29	0	3200	0	0
T32	0	160	0	0
T33	14992	0	0	0
T34	0	222	0	0
T35	0	48	0	0
T48	575636	0	0	0
T49	188188	0	0	0
T69	0	214	0	0
T71	0	5731	0	0
T72	0	776	0	0
T74	0	460	0	0
T75	0	164	0	0
T76	0	691	0	0
T77	0	1772	0	0
T78	0	745	0	0
T79	0	1550	0	0
T80	0	9274	0	0
T81	0	121	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	3763	0	0
T5	325342	2	0	0
T6	1355076	0	0	0
T11	1164588	0	0	0
T13	100975	0	0	0
T16	1091061	0	0	0
T17	950526	0	0	0
T18	323007	0	0	0
T21	188055	0	0	0
T22	341811	1	0	0
T23	45157	0	0	0
T24	0	15	0	0
T29	0	35	0	0
T30	157056	0	0	0
T32	407174	0	0	0
T33	14992	0	0	0
T34	4483	2	0	0
T35	106626	1	0	0
T36	0	15	0	0
T41	0	307	0	0
T48	431727	0	0	0
T49	141141	0	0	0
T64	47469	0	0	0
T65	149976	0	0	0
T66	30828	0	0	0
T69	0	1	0	0
T71	0	8	0	0
T72	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	3	0	0
T77	0	4	0	0
T78	0	7	0	0
T79	0	11	0	0
T80	0	26	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	79596	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	211	0	0
T6	451692	1	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T17	316842	0	0	0
T18	107669	0	0	0
T21	62685	0	0	0
T22	113937	0	0	0
T23	0	1	0	0
T24	404651	1	0	0
T29	0	2	0	0
T33	14992	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T41	0	7	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T50	237991	0	0	0
T52	0	3	0	0
T71	0	2	0	0
T72	303248	1	0	0
T78	133895	1	0	0
T79	0	3	0	0
T80	0	3	0	0
T82	23351	0	0	0
T83	17488	0	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	1014438	0	0	0
T95	248410	0	0	0
T96	81732	0	0	0
T97	51462	0	0	0
T98	514296	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	5150	0	0
T7	184384	1329	0	0
T8	0	1221	0	0
T9	0	593	0	0
T37	670692	0	0	0
T38	0	1353	0	0
T39	0	654	0	0
T40	2011904	0	0	0
T41	1940536	0	0	0
T42	445080	0	0	0
T43	543628	0	0	0
T44	829692	0	0	0
T45	649244	0	0	0
T46	903848	0	0	0
T47	146884	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	4190	0	0
T7	184384	1089	0	0
T8	0	981	0	0
T9	0	473	0	0
T37	670692	0	0	0
T38	0	1113	0	0
T39	0	534	0	0
T40	2011904	0	0	0
T41	1940536	0	0	0
T42	445080	0	0	0
T43	543628	0	0	0
T44	829692	0	0	0
T45	649244	0	0	0
T46	903848	0	0	0
T47	146884	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2122034828	2121751408	0	0
T1	102568	102276	0	0
T2	170864	170540	0	0
T3	831620	831580	0	0
T4	88600	87964	0	0
T5	650684	650460	0	0
T6	1806768	1806272	0	0
T10	338380	338080	0	0
T11	1552784	1552748	0	0
T16	1454748	1454728	0	0
T21	250740	250440	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2123556948	2122866688	0	0
T1	102568	102276	0	0
T2	170864	170540	0	0
T3	831620	831580	0	0
T4	88600	87964	0	0
T5	650684	650460	0	0
T6	1806768	1806272	0	0
T10	338380	338080	0	0
T11	1552784	1552748	0	0
T16	1454748	1454728	0	0
T21	250740	250440	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T21
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T5,T6,T22
1	1	1	Covered	T5,T6,T22

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T22
0	1	Covered	T6,T23,T79
1	0	Covered	T5,T25,T36

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T6,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T25,T36

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T22
1	0	Not Covered
1	1	Covered	T6,T23,T79

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T21,T23

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T3,T5,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T32,T74

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T5,T6,T22

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T5,T6,T22
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T25,T29
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T5,T18,T32
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T29,T79,T41
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T1,T33,T83
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T5,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T5,T22,T34
TimeoutSt->Phase0St	172	Covered	T5,T6,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T22,T34
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T99,T100
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T18,T32
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T79,T41
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T33,T83
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T5,T35
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	530889237	249	0	0
CheckAccumTrig0_A	530889237	797	0	0
CheckAccumTrig1_A	530889237	47	0	0
CheckClr_A	530889237	412	0	0
CheckEn_A	530510716	212884941	0	0
CheckPhase0_A	530889237	879	0	0
CheckPhase1_A	530889237	849	0	0
CheckPhase2_A	530889237	825	0	0
CheckPhase3_A	530889237	806	0	0
CheckTimeout0_A	530889237	1035	0	0
CheckTimeoutSt1_A	530889237	127035	0	0
CheckTimeoutSt2_A	530889237	925	0	0
CheckTimeoutStTrig_A	530889237	62	0	0
ErrorStAllEscAsserted_A	530889237	1260	0	0
ErrorStIsTerminal_A	530889237	1020	0	0
EscStateOut_A	530508707	530437852	0	0
u_state_regs_A	530889237	530716672	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	249	0	0
T7	46096	56	0	0
T8	0	67	0	0
T9	0	27	0	0
T37	167673	0	0	0
T38	0	72	0	0
T39	0	27	0	0
T40	502976	0	0	0
T41	485134	0	0	0
T42	111270	0	0	0
T43	135907	0	0	0
T44	207423	0	0	0
T45	162311	0	0	0
T46	225962	0	0	0
T47	36721	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	797	0	0
T1	25642	5	0	0
T2	42716	1	0	0
T3	207905	1	0	0
T4	22150	0	0	0
T5	162671	4	0	0
T6	451692	2	0	0
T10	84595	0	0	0
T11	388196	0	0	0
T16	363687	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T21	62685	1	0	0
T33	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	47	0	0
T5	162671	1	0	0
T6	451692	0	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T17	316842	0	0	0
T18	107669	0	0	0
T21	62685	0	0	0
T22	113937	0	0	0
T25	0	4	0	0
T37	0	1	0	0
T41	0	1	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	0	1	0	0
T56	0	1	0	0
T59	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	412	0	0
T1	25642	4	0	0
T2	42716	0	0	0
T3	207905	0	0	0
T4	22150	0	0	0
T5	162671	2	0	0
T6	451692	0	0	0
T10	84595	0	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T18	0	1	0	0
T21	62685	0	0	0
T24	0	1	0	0
T25	0	6	0	0
T32	0	4	0	0
T33	0	1	0	0
T35	0	1	0	0
T67	0	4	0	0
T70	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530510716	212884941	0	0
T1	25642	2064	0	0
T2	42716	876	0	0
T3	207905	3611	0	0
T4	22150	2144	0	0
T5	162671	442273	0	0
T6	451692	251901	0	0
T10	84595	84519	0	0
T11	388196	386907	0	0
T16	363687	21477	0	0
T21	62685	4218	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	879	0	0
T1	25642	5	0	0
T2	42716	1	0	0
T3	207905	1	0	0
T4	22150	0	0	0
T5	162671	5	0	0
T6	451692	2	0	0
T10	84595	0	0	0
T11	388196	0	0	0
T16	363687	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T21	62685	1	0	0
T33	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	849	0	0
T1	25642	5	0	0
T2	42716	1	0	0
T3	207905	1	0	0
T4	22150	0	0	0
T5	162671	4	0	0
T6	451692	2	0	0
T10	84595	0	0	0
T11	388196	0	0	0
T12	0	1	0	0
T16	363687	1	0	0
T17	0	1	0	0
T21	62685	1	0	0
T33	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	825	0	0
T1	25642	5	0	0
T2	42716	1	0	0
T3	207905	1	0	0
T4	22150	0	0	0
T5	162671	4	0	0
T6	451692	2	0	0
T10	84595	0	0	0
T11	388196	0	0	0
T12	0	1	0	0
T16	363687	1	0	0
T17	0	1	0	0
T21	62685	1	0	0
T33	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	806	0	0
T1	25642	4	0	0
T2	42716	1	0	0
T3	207905	1	0	0
T4	22150	0	0	0
T5	162671	4	0	0
T6	451692	2	0	0
T10	84595	0	0	0
T11	388196	0	0	0
T12	0	1	0	0
T16	363687	1	0	0
T17	0	1	0	0
T21	62685	1	0	0
T33	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	1035	0	0
T5	162671	2	0	0
T6	451692	1	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T17	316842	0	0	0
T18	107669	0	0	0
T21	62685	0	0	0
T22	113937	1	0	0
T23	0	1	0	0
T24	0	8	0	0
T25	0	4	0	0
T34	0	1	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T69	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	127035	0	0
T5	162671	66	0	0
T6	451692	65	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T17	316842	0	0	0
T18	107669	0	0	0
T21	62685	0	0	0
T22	113937	85	0	0
T23	0	674	0	0
T24	0	1292	0	0
T25	0	19	0	0
T34	0	74	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T69	0	214	0	0
T75	0	164	0	0
T76	0	149	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	925	0	0
T5	162671	1	0	0
T6	451692	0	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T17	316842	0	0	0
T18	107669	0	0	0
T21	62685	0	0	0
T22	113937	1	0	0
T24	0	8	0	0
T34	0	1	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T69	0	1	0	0
T72	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T82	0	2	0	0
T83	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	62	0	0
T6	451692	1	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T17	316842	0	0	0
T18	107669	0	0	0
T21	62685	0	0	0
T22	113937	0	0	0
T23	0	1	0	0
T33	14992	0	0	0
T36	0	1	0	0
T41	0	3	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T52	0	1	0	0
T79	0	2	0	0
T80	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T93	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	1260	0	0
T7	46096	308	0	0
T8	0	316	0	0
T9	0	141	0	0
T37	167673	0	0	0
T38	0	339	0	0
T39	0	156	0	0
T40	502976	0	0	0
T41	485134	0	0	0
T42	111270	0	0	0
T43	135907	0	0	0
T44	207423	0	0	0
T45	162311	0	0	0
T46	225962	0	0	0
T47	36721	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	1020	0	0
T7	46096	248	0	0
T8	0	256	0	0
T9	0	111	0	0
T37	167673	0	0	0
T38	0	279	0	0
T39	0	126	0	0
T40	502976	0	0	0
T41	485134	0	0	0
T42	111270	0	0	0
T43	135907	0	0	0
T44	207423	0	0	0
T45	162311	0	0	0
T46	225962	0	0	0
T47	36721	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530508707	530437852	0	0
T1	25642	25569	0	0
T2	42716	42635	0	0
T3	207905	207895	0	0
T4	22150	21991	0	0
T5	162671	162615	0	0
T6	451692	451568	0	0
T10	84595	84520	0	0
T11	388196	388187	0	0
T16	363687	363682	0	0
T21	62685	62610	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	530716672	0	0
T1	25642	25569	0	0
T2	42716	42635	0	0
T3	207905	207895	0	0
T4	22150	21991	0	0
T5	162671	162615	0	0
T6	451692	451568	0	0
T10	84595	84520	0	0
T11	388196	388187	0	0
T16	363687	363682	0	0
T21	62685	62610	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T10

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T10

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T6
1	0	1	Covered	T3,T10,T5
1	1	0	Covered	T1,T5,T6
1	1	1	Covered	T5,T35,T23

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T35,T23
0	1	Covered	T72,T29,T79
1	0	Covered	T5,T23,T51

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T35,T23
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T23,T51

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T35,T23
1	0	Covered	T26
1	1	Covered	T72,T29,T79

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T5,T6,T22

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T5
1	Covered	T1,T5,T48

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T10,T5
1	Covered	T3,T16,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T10,T17,T49

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T10,T18,T33

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T10,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T10,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T10
Phase1St	198	Covered	T1,T3,T10
Phase2St	215	Covered	T1,T3,T10
Phase3St	233	Covered	T1,T3,T10
TerminalSt	249	Covered	T1,T3,T10
TimeoutSt	159	Covered	T5,T35,T23

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T3,T10
IdleSt->TimeoutSt	159	Covered	T5,T35,T23
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T29,T36
Phase0St->Phase1St	198	Covered	T1,T3,T10
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T101,T52,T102
Phase1St->Phase2St	215	Covered	T1,T3,T10
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T18,T31,T32
Phase2St->Phase3St	233	Covered	T1,T3,T10
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T34,T32,T103
Phase3St->TerminalSt	249	Covered	T1,T3,T10
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T5,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T35,T76,T71
TimeoutSt->Phase0St	172	Covered	T5,T23,T72

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T10
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T35,T23
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T23,T72
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T35,T23
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T35,T76,T71
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T36,T37,T100
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T10
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T10
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T101,T52,T102
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T10
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T10
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T18,T31,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T10
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T34,T32,T104
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T31,T30
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T10
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	530889237	250	0	0
CheckAccumTrig0_A	530889237	470	0	0
CheckAccumTrig1_A	530889237	16	0	0
CheckClr_A	530889237	195	0	0
CheckEn_A	530510716	237898104	0	0
CheckPhase0_A	530889237	516	0	0
CheckPhase1_A	530889237	502	0	0
CheckPhase2_A	530889237	493	0	0
CheckPhase3_A	530889237	483	0	0
CheckTimeout0_A	530889237	1377	0	0
CheckTimeoutSt1_A	530889237	171616	0	0
CheckTimeoutSt2_A	530889237	1313	0	0
CheckTimeoutStTrig_A	530889237	45	0	0
ErrorStAllEscAsserted_A	530889237	1314	0	0
ErrorStIsTerminal_A	530889237	1074	0	0
EscStateOut_A	530508707	530437852	0	0
u_state_regs_A	530889237	530716672	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	250	0	0
T7	46096	62	0	0
T8	0	46	0	0
T9	0	37	0	0
T37	167673	0	0	0
T38	0	61	0	0
T39	0	44	0	0
T40	502976	0	0	0
T41	485134	0	0	0
T42	111270	0	0	0
T43	135907	0	0	0
T44	207423	0	0	0
T45	162311	0	0	0
T46	225962	0	0	0
T47	36721	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	470	0	0
T1	25642	1	0	0
T2	42716	0	0	0
T3	207905	1	0	0
T4	22150	0	0	0
T5	162671	1	0	0
T6	451692	3	0	0
T10	84595	1	0	0
T11	388196	0	0	0
T16	363687	1	0	0
T17	0	1	0	0
T21	62685	0	0	0
T22	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	16	0	0
T5	162671	1	0	0
T6	451692	0	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T17	316842	0	0	0
T18	107669	0	0	0
T21	62685	0	0	0
T22	113937	0	0	0
T23	0	1	0	0
T37	0	1	0	0
T44	0	1	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T58	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	195	0	0
T1	25642	1	0	0
T2	42716	0	0	0
T3	207905	0	0	0
T4	22150	0	0	0
T5	162671	0	0	0
T6	451692	0	0	0
T10	84595	0	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T18	0	1	0	0
T21	62685	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T31	0	3	0	0
T32	0	4	0	0
T34	0	1	0	0
T50	0	7	0	0
T69	0	1	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530510716	237898104	0	0
T1	25642	13920	0	0
T2	42716	42634	0	0
T3	207905	587	0	0
T4	22150	2160	0	0
T5	162671	148521	0	0
T6	451692	345623	0	0
T10	84595	10513	0	0
T11	388196	387543	0	0
T16	363687	2667	0	0
T21	62685	62609	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	516	0	0
T1	25642	1	0	0
T2	42716	0	0	0
T3	207905	1	0	0
T4	22150	0	0	0
T5	162671	2	0	0
T6	451692	1	0	0
T10	84595	1	0	0
T11	388196	0	0	0
T16	363687	1	0	0
T17	0	1	0	0
T21	62685	0	0	0
T22	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	502	0	0
T1	25642	1	0	0
T2	42716	0	0	0
T3	207905	1	0	0
T4	22150	0	0	0
T5	162671	2	0	0
T6	451692	1	0	0
T10	84595	1	0	0
T11	388196	0	0	0
T16	363687	1	0	0
T17	0	1	0	0
T21	62685	0	0	0
T22	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	493	0	0
T1	25642	1	0	0
T2	42716	0	0	0
T3	207905	1	0	0
T4	22150	0	0	0
T5	162671	2	0	0
T6	451692	1	0	0
T10	84595	1	0	0
T11	388196	0	0	0
T16	363687	1	0	0
T17	0	1	0	0
T21	62685	0	0	0
T22	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	483	0	0
T1	25642	1	0	0
T2	42716	0	0	0
T3	207905	1	0	0
T4	22150	0	0	0
T5	162671	2	0	0
T6	451692	1	0	0
T10	84595	1	0	0
T11	388196	0	0	0
T16	363687	1	0	0
T17	0	1	0	0
T21	62685	0	0	0
T22	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	1377	0	0
T5	162671	1	0	0
T6	451692	0	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T17	316842	0	0	0
T18	107669	0	0	0
T21	62685	0	0	0
T22	113937	0	0	0
T23	0	1	0	0
T29	0	9	0	0
T35	0	1	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T71	0	4	0	0
T72	0	1	0	0
T76	0	1	0	0
T78	0	7	0	0
T79	0	8	0	0
T80	0	20	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	171616	0	0
T5	162671	17	0	0
T6	451692	0	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T17	316842	0	0	0
T18	107669	0	0	0
T21	62685	0	0	0
T22	113937	0	0	0
T29	0	1050	0	0
T35	0	48	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T71	0	1914	0	0
T72	0	144	0	0
T76	0	127	0	0
T78	0	742	0	0
T79	0	1366	0	0
T80	0	7486	0	0
T81	0	121	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	1313	0	0
T13	100975	0	0	0
T23	45157	0	0	0
T29	0	7	0	0
T30	157056	0	0	0
T32	407174	0	0	0
T34	4483	0	0	0
T35	106626	1	0	0
T36	0	3	0	0
T41	0	307	0	0
T64	47469	0	0	0
T65	149976	0	0	0
T66	30828	0	0	0
T71	0	4	0	0
T76	0	1	0	0
T78	0	7	0	0
T79	0	7	0	0
T80	0	19	0	0
T84	0	1	0	0
T85	79596	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	45	0	0
T29	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T41	0	2	0	0
T50	237991	0	0	0
T72	151624	1	0	0
T78	133895	0	0	0
T79	0	1	0	0
T80	0	1	0	0
T82	23351	0	0	0
T83	17488	0	0	0
T86	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T94	507219	0	0	0
T95	248410	0	0	0
T96	81732	0	0	0
T97	51462	0	0	0
T98	514296	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	1314	0	0
T7	46096	339	0	0
T8	0	292	0	0
T9	0	153	0	0
T37	167673	0	0	0
T38	0	364	0	0
T39	0	166	0	0
T40	502976	0	0	0
T41	485134	0	0	0
T42	111270	0	0	0
T43	135907	0	0	0
T44	207423	0	0	0
T45	162311	0	0	0
T46	225962	0	0	0
T47	36721	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	1074	0	0
T7	46096	279	0	0
T8	0	232	0	0
T9	0	123	0	0
T37	167673	0	0	0
T38	0	304	0	0
T39	0	136	0	0
T40	502976	0	0	0
T41	485134	0	0	0
T42	111270	0	0	0
T43	135907	0	0	0
T44	207423	0	0	0
T45	162311	0	0	0
T46	225962	0	0	0
T47	36721	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530508707	530437852	0	0
T1	25642	25569	0	0
T2	42716	42635	0	0
T3	207905	207895	0	0
T4	22150	21991	0	0
T5	162671	162615	0	0
T6	451692	451568	0	0
T10	84595	84520	0	0
T11	388196	388187	0	0
T16	363687	363682	0	0
T21	62685	62610	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	530716672	0	0
T1	25642	25569	0	0
T2	42716	42635	0	0
T3	207905	207895	0	0
T4	22150	21991	0	0
T5	162671	162615	0	0
T6	451692	451568	0	0
T10	84595	84520	0	0
T11	388196	388187	0	0
T16	363687	363682	0	0
T21	62685	62610	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T10,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T22
1	0	1	Covered	T3,T10,T5
1	1	0	Covered	T5,T6,T17
1	1	1	Covered	T5,T34,T74

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T34,T74
0	1	Covered	T24,T71,T78
1	0	Covered	T5,T24,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T34,T74
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T24,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T34,T74
1	0	Covered	T28
1	1	Covered	T24,T71,T78

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T5,T11
1	Covered	T1,T5,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T10,T5
1	Covered	T5,T17,T33

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T10,T5,T16

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T10,T5
1	Covered	T11,T49,T35

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T10,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T11,T16,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T5,T6,T11

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T10,T5
Phase1St	198	Covered	T1,T10,T5
Phase2St	215	Covered	T1,T10,T5
Phase3St	233	Covered	T1,T10,T5
TerminalSt	249	Covered	T1,T10,T5
TimeoutSt	159	Covered	T5,T34,T74

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T10,T5
IdleSt->TimeoutSt	159	Covered	T5,T34,T74
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T37,T52,T105
Phase0St->Phase1St	198	Covered	T1,T10,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T30,T50,T37
Phase1St->Phase2St	215	Covered	T1,T10,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T18,T67,T105
Phase2St->Phase3St	233	Covered	T1,T10,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T105,T106,T107
Phase3St->TerminalSt	249	Covered	T1,T10,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T5,T6,T11
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T5,T34,T74
TimeoutSt->Phase0St	172	Covered	T5,T24,T71

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T34,T74
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T24,T71
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T34,T74
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T34,T74
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T37,T52,T105
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T10,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T10,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T30,T50,T37
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T10,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T10,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T18,T67,T105
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T10,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T10,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T105,T106,T107
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T10,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T5,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T6,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T10,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	530889237	229	0	0
CheckAccumTrig0_A	530889237	511	0	0
CheckAccumTrig1_A	530889237	21	0	0
CheckClr_A	530889237	240	0	0
CheckEn_A	530510716	219162738	0	0
CheckPhase0_A	530889237	573	0	0
CheckPhase1_A	530889237	556	0	0
CheckPhase2_A	530889237	542	0	0
CheckPhase3_A	530889237	537	0	0
CheckTimeout0_A	530889237	1245	0	0
CheckTimeoutSt1_A	530889237	140407	0	0
CheckTimeoutSt2_A	530889237	1162	0	0
CheckTimeoutStTrig_A	530889237	59	0	0
ErrorStAllEscAsserted_A	530889237	1268	0	0
ErrorStIsTerminal_A	530889237	1028	0	0
EscStateOut_A	530508707	530437852	0	0
u_state_regs_A	530889237	530716672	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	229	0	0
T7	46096	53	0	0
T8	0	74	0	0
T9	0	24	0	0
T37	167673	0	0	0
T38	0	48	0	0
T39	0	30	0	0
T40	502976	0	0	0
T41	485134	0	0	0
T42	111270	0	0	0
T43	135907	0	0	0
T44	207423	0	0	0
T45	162311	0	0	0
T46	225962	0	0	0
T47	36721	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	511	0	0
T1	25642	1	0	0
T2	42716	0	0	0
T3	207905	0	0	0
T4	22150	0	0	0
T5	162671	4	0	0
T6	451692	1	0	0
T10	84595	1	0	0
T11	388196	2	0	0
T16	363687	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T21	62685	0	0	0
T22	0	1	0	0
T49	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	21	0	0
T5	162671	1	0	0
T6	451692	0	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T17	316842	0	0	0
T18	107669	0	0	0
T21	62685	0	0	0
T22	113937	0	0	0
T24	0	1	0	0
T37	0	1	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T50	0	1	0	0
T52	0	1	0	0
T57	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	240	0	0
T5	162671	2	0	0
T6	451692	1	0	0
T11	388196	1	0	0
T16	363687	0	0	0
T17	316842	0	0	0
T18	107669	1	0	0
T21	62685	0	0	0
T22	113937	0	0	0
T24	0	2	0	0
T30	0	1	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T50	0	1	0	0
T67	0	1	0	0
T68	0	4	0	0
T71	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530510716	219162738	0	0
T1	25642	2098	0	0
T2	42716	42634	0	0
T3	207905	207592	0	0
T4	22150	2177	0	0
T5	162671	375949	0	0
T6	451692	389527	0	0
T10	84595	2596	0	0
T11	388196	3087	0	0
T16	363687	30296	0	0
T21	62685	62609	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	573	0	0
T1	25642	1	0	0
T2	42716	0	0	0
T3	207905	0	0	0
T4	22150	0	0	0
T5	162671	5	0	0
T6	451692	1	0	0
T10	84595	1	0	0
T11	388196	2	0	0
T16	363687	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T21	62685	0	0	0
T22	0	1	0	0
T49	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	556	0	0
T1	25642	1	0	0
T2	42716	0	0	0
T3	207905	0	0	0
T4	22150	0	0	0
T5	162671	5	0	0
T6	451692	1	0	0
T10	84595	1	0	0
T11	388196	2	0	0
T16	363687	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T21	62685	0	0	0
T22	0	1	0	0
T49	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	542	0	0
T1	25642	1	0	0
T2	42716	0	0	0
T3	207905	0	0	0
T4	22150	0	0	0
T5	162671	5	0	0
T6	451692	1	0	0
T10	84595	1	0	0
T11	388196	2	0	0
T16	363687	1	0	0
T17	0	1	0	0
T21	62685	0	0	0
T22	0	1	0	0
T33	0	1	0	0
T49	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	537	0	0
T1	25642	1	0	0
T2	42716	0	0	0
T3	207905	0	0	0
T4	22150	0	0	0
T5	162671	5	0	0
T6	451692	1	0	0
T10	84595	1	0	0
T11	388196	2	0	0
T16	363687	1	0	0
T17	0	1	0	0
T21	62685	0	0	0
T22	0	1	0	0
T33	0	1	0	0
T49	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	1245	0	0
T5	162671	2	0	0
T6	451692	0	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T17	316842	0	0	0
T18	107669	0	0	0
T21	62685	0	0	0
T22	113937	0	0	0
T24	0	9	0	0
T29	0	28	0	0
T34	0	1	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T50	0	1	0	0
T71	0	6	0	0
T74	0	1	0	0
T77	0	4	0	0
T78	0	1	0	0
T79	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	140407	0	0
T5	162671	152	0	0
T6	451692	0	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T17	316842	0	0	0
T18	107669	0	0	0
T21	62685	0	0	0
T22	113937	0	0	0
T24	0	1649	0	0
T29	0	2150	0	0
T34	0	74	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T71	0	1851	0	0
T74	0	460	0	0
T77	0	729	0	0
T78	0	3	0	0
T79	0	184	0	0
T80	0	1788	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	1162	0	0
T5	162671	1	0	0
T6	451692	0	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T17	316842	0	0	0
T18	107669	0	0	0
T21	62685	0	0	0
T22	113937	0	0	0
T24	0	7	0	0
T29	0	28	0	0
T34	0	1	0	0
T36	0	12	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T71	0	4	0	0
T74	0	1	0	0
T77	0	4	0	0
T79	0	4	0	0
T80	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	59	0	0
T14	359627	0	0	0
T24	404651	1	0	0
T36	0	1	0	0
T41	0	2	0	0
T52	0	2	0	0
T70	101168	0	0	0
T71	483921	2	0	0
T72	151624	0	0	0
T76	27051	0	0	0
T77	78858	0	0	0
T78	0	1	0	0
T80	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T94	507219	0	0	0
T110	0	1	0	0
T111	20540	0	0	0
T112	26170	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	1268	0	0
T7	46096	342	0	0
T8	0	319	0	0
T9	0	137	0	0
T37	167673	0	0	0
T38	0	312	0	0
T39	0	158	0	0
T40	502976	0	0	0
T41	485134	0	0	0
T42	111270	0	0	0
T43	135907	0	0	0
T44	207423	0	0	0
T45	162311	0	0	0
T46	225962	0	0	0
T47	36721	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	1028	0	0
T7	46096	282	0	0
T8	0	259	0	0
T9	0	107	0	0
T37	167673	0	0	0
T38	0	252	0	0
T39	0	128	0	0
T40	502976	0	0	0
T41	485134	0	0	0
T42	111270	0	0	0
T43	135907	0	0	0
T44	207423	0	0	0
T45	162311	0	0	0
T46	225962	0	0	0
T47	36721	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530508707	530437852	0	0
T1	25642	25569	0	0
T2	42716	42635	0	0
T3	207905	207895	0	0
T4	22150	21991	0	0
T5	162671	162615	0	0
T6	451692	451568	0	0
T10	84595	84520	0	0
T11	388196	388187	0	0
T16	363687	363682	0	0
T21	62685	62610	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	530716672	0	0
T1	25642	25569	0	0
T2	42716	42635	0	0
T3	207905	207895	0	0
T4	22150	21991	0	0
T5	162671	162615	0	0
T6	451692	451568	0	0
T10	84595	84520	0	0
T11	388196	388187	0	0
T16	363687	363682	0	0
T21	62685	62610	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T10,T5,T6
1	1	0	Covered	T1,T5,T6
1	1	1	Covered	T6,T22,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T22,T23
0	1	Covered	T98,T36,T41
1	0	Covered	T22,T20,T23

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T22,T23
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T20,T23

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T22,T20
1	0	Covered	T27
1	1	Covered	T98,T36,T41

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T73,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T16

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T11,T22,T48

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T11
1	Covered	T5,T6,T22

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T5,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T6,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T5,T6,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T5,T6
Phase1St	198	Covered	T1,T5,T6
Phase2St	215	Covered	T1,T5,T6
Phase3St	233	Covered	T1,T5,T6
TerminalSt	249	Covered	T1,T5,T6
TimeoutSt	159	Covered	T6,T22,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T5,T6
IdleSt->TimeoutSt	159	Covered	T6,T22,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T1,T72,T29
Phase0St->Phase1St	198	Covered	T1,T5,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T44,T53,T113
Phase1St->Phase2St	215	Covered	T1,T5,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T40,T53,T114
Phase2St->Phase3St	233	Covered	T1,T5,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T18,T71,T53
Phase3St->TerminalSt	249	Covered	T1,T5,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T5,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T22,T23
TimeoutSt->Phase0St	172	Covered	T20,T23,T98

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T22,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T22,T20,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T22,T23
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T22,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T115,T116
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T5,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T5,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T44,T53,T113
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T5,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T5,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T40,T53,T114
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T5,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T18,T71,T53
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T5,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T22,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T5,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	530889237	242	0	0
CheckAccumTrig0_A	530889237	517	0	0
CheckAccumTrig1_A	530889237	20	0	0
CheckClr_A	530889237	235	0	0
CheckEn_A	530510716	215936444	0	0
CheckPhase0_A	530889237	562	0	0
CheckPhase1_A	530889237	553	0	0
CheckPhase2_A	530889237	540	0	0
CheckPhase3_A	530889237	531	0	0
CheckTimeout0_A	530889237	432	0	0
CheckTimeoutSt1_A	530889237	54862	0	0
CheckTimeoutSt2_A	530889237	363	0	0
CheckTimeoutStTrig_A	530889237	45	0	0
ErrorStAllEscAsserted_A	530889237	1308	0	0
ErrorStIsTerminal_A	530889237	1068	0	0
EscStateOut_A	530508707	530437852	0	0
u_state_regs_A	530889237	530716672	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	242	0	0
T7	46096	64	0	0
T8	0	46	0	0
T9	0	31	0	0
T37	167673	0	0	0
T38	0	69	0	0
T39	0	32	0	0
T40	502976	0	0	0
T41	485134	0	0	0
T42	111270	0	0	0
T43	135907	0	0	0
T44	207423	0	0	0
T45	162311	0	0	0
T46	225962	0	0	0
T47	36721	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	517	0	0
T1	25642	4	0	0
T2	42716	0	0	0
T3	207905	0	0	0
T4	22150	0	0	0
T5	162671	3	0	0
T6	451692	2	0	0
T10	84595	0	0	0
T11	388196	1	0	0
T16	363687	1	0	0
T18	0	1	0	0
T21	62685	0	0	0
T22	0	2	0	0
T33	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	20	0	0
T20	386661	1	0	0
T23	45157	1	0	0
T26	0	1	0	0
T30	157056	0	0	0
T31	262733	0	0	0
T32	407174	0	0	0
T34	4483	0	0	0
T35	106626	0	0	0
T37	0	1	0	0
T62	0	1	0	0
T64	47469	0	0	0
T65	149976	0	0	0
T66	30828	0	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	235	0	0
T1	25642	3	0	0
T2	42716	0	0	0
T3	207905	0	0	0
T4	22150	0	0	0
T5	162671	0	0	0
T6	451692	0	0	0
T10	84595	0	0	0
T11	388196	0	0	0
T14	0	2	0	0
T16	363687	0	0	0
T18	0	1	0	0
T20	0	1	0	0
T21	62685	0	0	0
T22	0	1	0	0
T23	0	2	0	0
T24	0	10	0	0
T67	0	1	0	0
T71	0	1	0	0
T75	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530510716	215936444	0	0
T1	25642	10016	0	0
T2	42716	38293	0	0
T3	207905	207895	0	0
T4	22150	2194	0	0
T5	162671	339747	0	0
T6	451692	248368	0	0
T10	84595	83504	0	0
T11	388196	3107	0	0
T16	363687	40015	0	0
T21	62685	62609	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	562	0	0
T1	25642	3	0	0
T2	42716	0	0	0
T3	207905	0	0	0
T4	22150	0	0	0
T5	162671	3	0	0
T6	451692	2	0	0
T10	84595	0	0	0
T11	388196	1	0	0
T16	363687	1	0	0
T18	0	1	0	0
T21	62685	0	0	0
T22	0	2	0	0
T33	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	553	0	0
T1	25642	3	0	0
T2	42716	0	0	0
T3	207905	0	0	0
T4	22150	0	0	0
T5	162671	3	0	0
T6	451692	2	0	0
T10	84595	0	0	0
T11	388196	1	0	0
T16	363687	1	0	0
T18	0	1	0	0
T21	62685	0	0	0
T22	0	2	0	0
T33	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	540	0	0
T1	25642	3	0	0
T2	42716	0	0	0
T3	207905	0	0	0
T4	22150	0	0	0
T5	162671	3	0	0
T6	451692	2	0	0
T10	84595	0	0	0
T11	388196	1	0	0
T16	363687	1	0	0
T18	0	1	0	0
T21	62685	0	0	0
T22	0	2	0	0
T33	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	531	0	0
T1	25642	3	0	0
T2	42716	0	0	0
T3	207905	0	0	0
T4	22150	0	0	0
T5	162671	3	0	0
T6	451692	2	0	0
T10	84595	0	0	0
T11	388196	1	0	0
T16	363687	1	0	0
T21	62685	0	0	0
T22	0	2	0	0
T33	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T73	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	432	0	0
T6	451692	1	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T17	316842	0	0	0
T18	107669	0	0	0
T20	0	1	0	0
T21	62685	0	0	0
T22	113937	1	0	0
T23	0	2	0	0
T24	0	7	0	0
T32	0	1	0	0
T33	14992	0	0	0
T34	0	1	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T71	0	14	0	0
T76	0	6	0	0
T77	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	54862	0	0
T6	451692	205	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T17	316842	0	0	0
T18	107669	0	0	0
T21	62685	0	0	0
T22	113937	33	0	0
T23	0	18	0	0
T24	0	1152	0	0
T32	0	160	0	0
T33	14992	0	0	0
T34	0	74	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T71	0	1966	0	0
T72	0	632	0	0
T76	0	415	0	0
T77	0	1043	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	363	0	0
T6	451692	1	0	0
T11	388196	0	0	0
T16	363687	0	0	0
T17	316842	0	0	0
T18	107669	0	0	0
T21	62685	0	0	0
T22	113937	1	0	0
T23	0	1	0	0
T24	0	7	0	0
T32	0	1	0	0
T33	14992	0	0	0
T34	0	1	0	0
T48	143909	0	0	0
T49	47047	0	0	0
T71	0	14	0	0
T72	0	3	0	0
T76	0	6	0	0
T77	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	45	0	0
T15	505255	0	0	0
T29	526720	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T41	0	3	0	0
T60	0	1	0	0
T79	161448	0	0	0
T80	255130	0	0	0
T98	514296	1	0	0
T110	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	19897	0	0	0
T127	113303	0	0	0
T128	52894	0	0	0
T129	23168	0	0	0
T130	55104	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	1308	0	0
T7	46096	340	0	0
T8	0	294	0	0
T9	0	162	0	0
T37	167673	0	0	0
T38	0	338	0	0
T39	0	174	0	0
T40	502976	0	0	0
T41	485134	0	0	0
T42	111270	0	0	0
T43	135907	0	0	0
T44	207423	0	0	0
T45	162311	0	0	0
T46	225962	0	0	0
T47	36721	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	1068	0	0
T7	46096	280	0	0
T8	0	234	0	0
T9	0	132	0	0
T37	167673	0	0	0
T38	0	278	0	0
T39	0	144	0	0
T40	502976	0	0	0
T41	485134	0	0	0
T42	111270	0	0	0
T43	135907	0	0	0
T44	207423	0	0	0
T45	162311	0	0	0
T46	225962	0	0	0
T47	36721	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530508707	530437852	0	0
T1	25642	25569	0	0
T2	42716	42635	0	0
T3	207905	207895	0	0
T4	22150	21991	0	0
T5	162671	162615	0	0
T6	451692	451568	0	0
T10	84595	84520	0	0
T11	388196	388187	0	0
T16	363687	363682	0	0
T21	62685	62610	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530889237	530716672	0	0
T1	25642	25569	0	0
T2	42716	42635	0	0
T3	207905	207895	0	0
T4	22150	21991	0	0
T5	162671	162615	0	0
T6	451692	451568	0	0
T10	84595	84520	0	0
T11	388196	388187	0	0
T16	363687	363682	0	0
T21	62685	62610	0	0