Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T12
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T199,T72,T200
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T12

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12744	0	0
DisabledNoTrigBkwd_A	2147483647	605601	0	0
DisabledNoTrigFwd_A	2147483647	1219909749	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12744	0	0
T9	22202	0	0	0
T55	192289	0	0	0
T72	0	863	0	0
T80	58298	0	0	0
T81	130599	0	0	0
T90	63802	0	0	0
T107	171273	0	0	0
T110	255512	0	0	0
T111	270674	0	0	0
T199	4301	935	0	0
T200	1118	409	0	0
T201	1775	865	0	0
T202	0	1484	0	0
T203	0	366	0	0
T204	0	428	0	0
T205	0	452	0	0
T206	0	575	0	0
T207	0	589	0	0
T208	0	975	0	0
T209	0	421	0	0
T210	0	1092	0	0
T211	0	256	0	0
T212	0	218	0	0
T213	0	824	0	0
T214	0	833	0	0
T215	0	269	0	0
T216	0	289	0	0
T217	0	601	0	0
T218	4009	0	0	0
T219	24441	0	0	0
T220	111025	0	0	0
T221	21167	0	0	0
T222	246126	0	0	0
T223	115588	0	0	0
T224	116198	0	0	0
T225	432739	0	0	0
T226	86785	0	0	0
T227	989760	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	605601	0	0
T2	320985	60	0	0
T3	423654	27	0	0
T4	1961084	105	0	0
T5	0	2148	0	0
T6	2185444	0	0	0
T7	1114700	3	0	0
T8	100406	599	0	0
T12	87536	65	0	0
T13	153864	27	0	0
T14	180028	1	0	0
T15	84944	38	0	0
T16	0	430	0	0
T19	162782	1335	0	0
T20	0	2373	0	0
T21	0	2207	0	0
T22	0	286	0	0
T23	51336	3	0	0
T24	0	151	0	0
T27	0	1440	0	0
T51	0	7	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1219909749	0	0
T1	99348	74956	0	0
T2	427980	209496	0	0
T3	564872	335773	0	0
T4	1961084	1382773	0	0
T6	2185444	1114542	0	0
T12	87536	23912	0	0
T13	153864	105849	0	0
T14	180028	136841	0	0
T15	84944	61473	0	0
T23	51336	41718	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T15
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T199,T207,T215
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	547691932	2394	0	0
DisabledNoTrigBkwd_A	547691932	132116	0	0
DisabledNoTrigFwd_A	547691932	309786203	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	2394	0	0
T80	58298	0	0	0
T81	130599	0	0	0
T107	171273	0	0	0
T110	255512	0	0	0
T199	4301	935	0	0
T207	0	589	0	0
T215	0	269	0	0
T217	0	601	0	0
T218	4009	0	0	0
T219	24441	0	0	0
T220	111025	0	0	0
T221	21167	0	0	0
T222	246126	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	132116	0	0
T2	106995	27	0	0
T3	141218	2	0	0
T4	490271	34	0	0
T6	546361	0	0	0
T7	278675	1	0	0
T8	0	300	0	0
T12	21884	26	0	0
T13	38466	0	0	0
T14	45007	1	0	0
T15	21236	32	0	0
T23	12834	3	0	0
T24	0	103	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	309786203	0	0
T1	24837	709	0	0
T2	106995	14603	0	0
T3	141218	104810	0	0
T4	490271	138633	0	0
T6	546361	18127	0	0
T12	21884	836	0	0
T13	38466	32282	0	0
T14	45007	36905	0	0
T15	21236	11964	0	0
T23	12834	3447	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T3,T12,T15
1	1	Covered	T2,T3,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T200,T203,T204
1	1	Covered	T2,T3,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T12,T15

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	547691932	1421	0	0
DisabledNoTrigBkwd_A	547691932	138724	0	0
DisabledNoTrigFwd_A	547691932	310639548	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	1421	0	0
T9	22202	0	0	0
T55	192289	0	0	0
T90	63802	0	0	0
T111	270674	0	0	0
T200	1118	409	0	0
T203	0	366	0	0
T204	0	428	0	0
T212	0	218	0	0
T223	115588	0	0	0
T224	116198	0	0	0
T225	432739	0	0	0
T226	86785	0	0	0
T227	989760	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	138724	0	0
T2	106995	32	0	0
T3	141218	0	0	0
T4	490271	23	0	0
T5	0	303	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	0	1	0	0
T12	21884	19	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	5	0	0
T19	0	1332	0	0
T20	0	2373	0	0
T21	0	4	0	0
T23	12834	0	0	0
T27	0	1298	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	310639548	0	0
T1	24837	24749	0	0
T2	106995	3003	0	0
T3	141218	122680	0	0
T4	490271	420262	0	0
T6	546361	546268	0	0
T12	21884	5798	0	0
T13	38466	37405	0	0
T14	45007	44918	0	0
T15	21236	12782	0	0
T23	12834	12757	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T2,T12,T15
1	1	Covered	T2,T3,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T202,T205
1	1	Covered	T2,T3,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	547691932	7242	0	0
DisabledNoTrigBkwd_A	547691932	164660	0	0
DisabledNoTrigFwd_A	547691932	296562726	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	7242	0	0
T98	151042	0	0	0
T113	471913	0	0	0
T201	1775	865	0	0
T202	0	1484	0	0
T205	0	452	0	0
T206	0	575	0	0
T208	0	975	0	0
T209	0	421	0	0
T210	0	1092	0	0
T211	0	256	0	0
T214	0	833	0	0
T216	0	289	0	0
T228	847877	0	0	0
T229	157982	0	0	0
T230	155395	0	0	0
T231	83711	0	0	0
T232	199540	0	0	0
T233	29393	0	0	0
T234	1323	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	164660	0	0
T2	106995	1	0	0
T3	141218	25	0	0
T4	490271	16	0	0
T5	0	1681	0	0
T6	546361	0	0	0
T7	278675	2	0	0
T8	0	298	0	0
T12	21884	7	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	1	0	0
T19	0	3	0	0
T23	12834	0	0	0
T27	0	34	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	296562726	0	0
T1	24837	24749	0	0
T2	106995	90515	0	0
T3	141218	4321	0	0
T4	490271	426853	0	0
T6	546361	546268	0	0
T12	21884	6119	0	0
T13	38466	34574	0	0
T14	45007	10100	0	0
T15	21236	19038	0	0
T23	12834	12757	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T2,T3,T12
1	1	Covered	T3,T12,T15

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T72,T213
1	1	Covered	T3,T12,T15

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T13,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	547691932	1687	0	0
DisabledNoTrigBkwd_A	547691932	170101	0	0
DisabledNoTrigFwd_A	547691932	302921272	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	1687	0	0
T36	366646	0	0	0
T72	1636	863	0	0
T73	317567	0	0	0
T74	43920	0	0	0
T75	24952	0	0	0
T76	361295	0	0	0
T213	0	824	0	0
T235	25034	0	0	0
T236	724844	0	0	0
T237	40353	0	0	0
T238	77651	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	170101	0	0
T4	490271	32	0	0
T5	0	164	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	13	0	0
T13	38466	27	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T16	0	430	0	0
T19	162782	0	0	0
T21	0	2203	0	0
T22	0	286	0	0
T23	12834	0	0	0
T24	0	48	0	0
T27	0	108	0	0
T51	0	7	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	302921272	0	0
T1	24837	24749	0	0
T2	106995	101375	0	0
T3	141218	103962	0	0
T4	490271	397025	0	0
T6	546361	3879	0	0
T12	21884	11159	0	0
T13	38466	1588	0	0
T14	45007	44918	0	0
T15	21236	17689	0	0
T23	12834	12757	0	0