Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T26
1	1	1	Covered	T2,T3,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T13,T4
1	1	0	Covered	T2,T3,T12
1	1	1	Covered	T2,T3,T12

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T12
0	1	Covered	T2,T3,T27
1	0	Covered	T12,T21,T28

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T12
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T12,T21,T28

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T29,T30
1	1	Covered	T2,T3,T27

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T3,T12,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T15,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T15,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T12

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T12
Phase1St	198	Covered	T2,T3,T12
Phase2St	215	Covered	T2,T3,T12
Phase3St	233	Covered	T2,T3,T12
TerminalSt	249	Covered	T2,T3,T12
TimeoutSt	159	Covered	T2,T3,T12

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T2,T3,T12
IdleSt->TimeoutSt	159	Covered	T2,T3,T12
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T5,T31,T32
Phase0St->Phase1St	198	Covered	T2,T3,T12
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T22,T33,T34
Phase1St->Phase2St	215	Covered	T2,T3,T12
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T4,T5,T31
Phase2St->Phase3St	233	Covered	T2,T3,T12
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T25,T20,T22
Phase3St->TerminalSt	249	Covered	T2,T3,T12
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T3,T12,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T3,T5,T27
TimeoutSt->Phase0St	172	Covered	T2,T3,T12

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T27
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T35,T36
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T33,T34,T37
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T31,T38
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T20,T39
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T12,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	841	0	0
CheckAccumTrig0_A	2147483647	2321	0	0
CheckAccumTrig1_A	2147483647	95	0	0
CheckClr_A	2147483647	1062	0	0
CheckEn_A	2147483647	913377390	0	0
CheckPhase0_A	2147483647	2543	0	0
CheckPhase1_A	2147483647	2483	0	0
CheckPhase2_A	2147483647	2422	0	0
CheckPhase3_A	2147483647	2351	0	0
CheckTimeout0_A	2147483647	3335	0	0
CheckTimeoutSt1_A	2147483647	368292	0	0
CheckTimeoutSt2_A	2147483647	3009	0	0
CheckTimeoutStTrig_A	2147483647	216	0	0
ErrorStAllEscAsserted_A	2147483647	4626	0	0
ErrorStIsTerminal_A	2147483647	3786	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	841	0	0
T9	88808	153	0	0
T10	0	101	0	0
T11	0	98	0	0
T40	0	250	0	0
T41	0	239	0	0
T42	329132	0	0	0
T43	2725804	0	0	0
T44	35904	0	0	0
T45	374036	0	0	0
T46	1784908	0	0	0
T47	288576	0	0	0
T48	265796	0	0	0
T49	75132	0	0	0
T50	721216	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2321	0	0
T2	213990	2	0	0
T3	423654	2	0	0
T4	1961084	14	0	0
T5	0	17	0	0
T6	2185444	0	0	0
T7	1114700	2	0	0
T8	200812	3	0	0
T12	87536	7	0	0
T13	153864	1	0	0
T14	180028	1	0	0
T15	84944	3	0	0
T16	0	1	0	0
T19	162782	2	0	0
T20	0	5	0	0
T21	0	2	0	0
T22	0	3	0	0
T23	51336	1	0	0
T24	0	2	0	0
T27	0	4	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	95	0	0
T4	490271	0	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	1	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T19	162782	0	0	0
T21	0	1	0	0
T23	12834	0	0	0
T27	62484	0	0	0
T28	337800	2	0	0
T29	0	1	0	0
T36	0	1	0	0
T53	217516	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	2	0	0
T69	219792	0	0	0
T70	763280	0	0	0
T71	51134	0	0	0
T72	3272	0	0	0
T73	635134	0	0	0
T74	87840	0	0	0
T75	49904	0	0	0
T76	722590	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1062	0	0
T3	423654	2	0	0
T4	1470813	2	0	0
T5	929091	4	0	0
T6	1639083	0	0	0
T7	836025	1	0	0
T8	301218	0	0	0
T12	65652	4	0	0
T13	115398	0	0	0
T14	135021	0	0	0
T15	63708	0	0	0
T16	557123	0	0	0
T20	978224	3	0	0
T21	343881	0	0	0
T22	394396	1	0	0
T23	38502	1	0	0
T25	0	2	0	0
T27	62484	3	0	0
T33	0	14	0	0
T34	0	1	0	0
T35	0	4	0	0
T36	0	3	0	0
T51	21747	1	0	0
T52	15627	2	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	3	0	0
T82	35111	0	0	0
T83	332221	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	913377390	0	0
T1	99348	74953	0	0
T2	427980	122003	0	0
T3	564872	335770	0	0
T4	1961084	1347506	0	0
T6	2185444	1114540	0	0
T12	87536	13601	0	0
T13	153864	105846	0	0
T14	180028	101992	0	0
T15	84944	25007	0	0
T23	51336	41715	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2543	0	0
T2	320985	3	0	0
T3	564872	4	0	0
T4	1961084	14	0	0
T5	0	18	0	0
T6	2185444	0	0	0
T7	1114700	2	0	0
T8	100406	3	0	0
T12	87536	8	0	0
T13	153864	1	0	0
T14	180028	1	0	0
T15	84944	3	0	0
T16	0	1	0	0
T19	0	2	0	0
T20	0	4	0	0
T21	0	2	0	0
T23	51336	1	0	0
T24	0	2	0	0
T27	0	5	0	0
T82	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2483	0	0
T2	320985	3	0	0
T3	564872	4	0	0
T4	1961084	13	0	0
T5	0	18	0	0
T6	2185444	0	0	0
T7	1114700	2	0	0
T8	100406	3	0	0
T12	87536	8	0	0
T13	153864	1	0	0
T14	180028	1	0	0
T15	84944	3	0	0
T16	0	1	0	0
T19	0	2	0	0
T20	0	4	0	0
T21	0	2	0	0
T23	51336	1	0	0
T24	0	2	0	0
T27	0	5	0	0
T82	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2422	0	0
T2	320985	3	0	0
T3	564872	4	0	0
T4	1961084	12	0	0
T5	0	17	0	0
T6	2185444	0	0	0
T7	1114700	2	0	0
T8	100406	3	0	0
T12	87536	8	0	0
T13	153864	1	0	0
T14	180028	1	0	0
T15	84944	3	0	0
T16	0	1	0	0
T19	0	2	0	0
T20	0	4	0	0
T21	0	2	0	0
T23	51336	1	0	0
T24	0	2	0	0
T27	0	5	0	0
T82	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2351	0	0
T2	320985	3	0	0
T3	564872	4	0	0
T4	1961084	12	0	0
T5	0	17	0	0
T6	2185444	0	0	0
T7	1114700	2	0	0
T8	100406	3	0	0
T12	87536	8	0	0
T13	153864	1	0	0
T14	180028	1	0	0
T15	84944	3	0	0
T16	0	1	0	0
T19	0	2	0	0
T20	0	3	0	0
T21	0	2	0	0
T23	51336	1	0	0
T24	0	2	0	0
T27	0	5	0	0
T82	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3335	0	0
T2	106995	1	0	0
T3	564872	19	0	0
T4	1961084	0	0	0
T5	0	6	0	0
T6	2185444	0	0	0
T7	1114700	0	0	0
T8	301218	0	0	0
T12	87536	1	0	0
T13	153864	0	0	0
T14	180028	0	0	0
T15	84944	0	0	0
T21	0	1	0	0
T22	0	5	0	0
T23	51336	0	0	0
T27	0	3	0	0
T31	0	13	0	0
T32	0	13	0	0
T33	0	20	0	0
T34	0	12	0	0
T35	0	2	0	0
T52	0	2	0	0
T77	0	4	0	0
T80	0	1	0	0
T81	0	13	0	0
T82	0	3	0	0
T84	0	3	0	0
T85	0	5	0	0
T86	0	1	0	0
T87	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	368292	0	0
T2	106995	744	0	0
T3	564872	4352	0	0
T4	1961084	0	0	0
T5	0	500	0	0
T6	2185444	0	0	0
T7	1114700	0	0	0
T8	301218	0	0	0
T12	87536	1	0	0
T13	153864	0	0	0
T14	180028	0	0	0
T15	84944	0	0	0
T22	0	397	0	0
T23	51336	0	0	0
T27	0	122	0	0
T31	0	3448	0	0
T32	0	2912	0	0
T33	0	1336	0	0
T34	0	1177	0	0
T35	0	216	0	0
T52	0	242	0	0
T77	0	793	0	0
T80	0	225	0	0
T81	0	579	0	0
T82	0	12	0	0
T84	0	230	0	0
T85	0	677	0	0
T86	0	437	0	0
T87	0	16	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3009	0	0
T3	564872	17	0	0
T4	1961084	0	0	0
T5	0	4	0	0
T6	2185444	0	0	0
T7	1114700	0	0	0
T8	401624	0	0	0
T12	87536	0	0	0
T13	153864	0	0	0
T14	180028	0	0	0
T15	84944	0	0	0
T22	0	4	0	0
T23	51336	0	0	0
T27	0	1	0	0
T31	0	10	0	0
T32	0	16	0	0
T33	0	19	0	0
T34	0	19	0	0
T35	0	1	0	0
T52	0	1	0	0
T77	0	3	0	0
T80	0	1	0	0
T81	0	12	0	0
T84	0	3	0	0
T85	0	6	0	0
T86	0	1	0	0
T87	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	216	0	0
T2	106995	1	0	0
T3	0	1	0	0
T20	978224	0	0	0
T21	343881	0	0	0
T22	394396	0	0	0
T27	62484	1	0	0
T29	0	1	0	0
T31	298470	3	0	0
T32	226431	2	0	0
T33	150507	0	0	0
T35	0	3	0	0
T36	0	5	0	0
T38	38454	0	0	0
T39	424967	0	0	0
T45	0	1	0	0
T51	21747	0	0	0
T52	15627	1	0	0
T54	0	1	0	0
T56	0	4	0	0
T75	0	1	0	0
T77	10992	1	0	0
T81	0	3	0	0
T83	332221	0	0	0
T85	29907	0	0	0
T86	1894	0	0	0
T87	902205	0	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	0	2	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	5315	0	0	0
T95	59001	0	0	0
T96	23968	0	0	0
T97	46697	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4626	0	0
T9	88808	663	0	0
T10	0	640	0	0
T11	0	665	0	0
T40	0	1344	0	0
T41	0	1314	0	0
T42	329132	0	0	0
T43	2725804	0	0	0
T44	35904	0	0	0
T45	374036	0	0	0
T46	1784908	0	0	0
T47	288576	0	0	0
T48	265796	0	0	0
T49	75132	0	0	0
T50	721216	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3786	0	0
T9	88808	543	0	0
T10	0	520	0	0
T11	0	545	0	0
T40	0	1104	0	0
T41	0	1074	0	0
T42	329132	0	0	0
T43	2725804	0	0	0
T44	35904	0	0	0
T45	374036	0	0	0
T46	1784908	0	0	0
T47	288576	0	0	0
T48	265796	0	0	0
T49	75132	0	0	0
T50	721216	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	99348	98996	0	0
T2	427980	427620	0	0
T3	564872	564276	0	0
T4	1961084	1960676	0	0
T6	2185444	2185072	0	0
T12	87536	87332	0	0
T13	153864	153644	0	0
T14	180028	179672	0	0
T15	84944	84576	0	0
T23	51336	51028	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	99348	98996	0	0
T2	427980	427620	0	0
T3	564872	564276	0	0
T4	1961084	1960676	0	0
T6	2185444	2185072	0	0
T12	87536	87332	0	0
T13	153864	153644	0	0
T14	180028	179672	0	0
T15	84944	84576	0	0
T23	51336	51028	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T12,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T12
1	0	1	Covered	T13,T24,T5
1	1	0	Covered	T3,T12,T15
1	1	1	Covered	T3,T77,T33

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T77,T33
0	1	Covered	T31,T35,T81
1	0	Covered	T28,T36,T54

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T77,T33
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T28,T36,T54

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T77,T33
1	0	Not Covered
1	1	Covered	T31,T35,T81

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T15,T4
1	Covered	T12,T19,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T12,T15
1	Covered	T4,T5,T21

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T12,T4
1	Covered	T15,T4,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12,T15,T4
1	Covered	T2,T8,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T19,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T8,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T12,T15,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T12,T15
Phase1St	198	Covered	T2,T12,T15
Phase2St	215	Covered	T2,T12,T15
Phase3St	233	Covered	T2,T12,T15
TerminalSt	249	Covered	T2,T12,T15
TimeoutSt	159	Covered	T3,T77,T33

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T2,T12,T15
IdleSt->TimeoutSt	159	Covered	T3,T77,T33
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T98,T99,T100
Phase0St->Phase1St	198	Covered	T2,T12,T15
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T46,T101,T102
Phase1St->Phase2St	215	Covered	T2,T12,T15
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T5,T36,T103
Phase2St->Phase3St	233	Covered	T2,T12,T15
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T20,T80,T81
Phase3St->TerminalSt	249	Covered	T2,T12,T15
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T5,T27
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T77,T33
TimeoutSt->Phase0St	172	Covered	T31,T35,T81

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T77,T33
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T31,T35,T81
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T77,T33
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T77,T33
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T104,T105,T106
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T12,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T12,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T46,T101,T102
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T12,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T12,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T36,T103
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T12,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T12,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T80,T81
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T12,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T12,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T27,T20,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T12,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	547691932	202	0	0
CheckAccumTrig0_A	547691932	506	0	0
CheckAccumTrig1_A	547691932	23	0	0
CheckClr_A	547691932	233	0	0
CheckEn_A	547549190	244105181	0	0
CheckPhase0_A	547691932	567	0	0
CheckPhase1_A	547691932	558	0	0
CheckPhase2_A	547691932	545	0	0
CheckPhase3_A	547691932	530	0	0
CheckTimeout0_A	547691932	803	0	0
CheckTimeoutSt1_A	547691932	101004	0	0
CheckTimeoutSt2_A	547691932	728	0	0
CheckTimeoutStTrig_A	547691932	50	0	0
ErrorStAllEscAsserted_A	547691932	1155	0	0
ErrorStIsTerminal_A	547691932	945	0	0
EscStateOut_A	547547802	547479105	0	0
u_state_regs_A	547691932	547533520	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	202	0	0
T9	22202	39	0	0
T10	0	28	0	0
T11	0	19	0	0
T40	0	64	0	0
T41	0	52	0	0
T42	82283	0	0	0
T43	681451	0	0	0
T44	8976	0	0	0
T45	93509	0	0	0
T46	446227	0	0	0
T47	72144	0	0	0
T48	66449	0	0	0
T49	18783	0	0	0
T50	180304	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	506	0	0
T2	106995	1	0	0
T3	141218	0	0	0
T4	490271	3	0	0
T5	0	6	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	0	1	0	0
T12	21884	1	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	1	0	0
T19	0	1	0	0
T20	0	4	0	0
T21	0	1	0	0
T23	12834	0	0	0
T27	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	23	0	0
T28	168900	1	0	0
T36	0	1	0	0
T53	108758	0	0	0
T54	0	1	0	0
T58	0	1	0	0
T61	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	2	0	0
T69	109896	0	0	0
T70	381640	0	0	0
T71	25567	0	0	0
T72	1636	0	0	0
T73	317567	0	0	0
T74	43920	0	0	0
T75	24952	0	0	0
T76	361295	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	233	0	0
T5	929091	1	0	0
T16	557123	0	0	0
T20	978224	3	0	0
T21	343881	0	0	0
T22	394396	1	0	0
T27	62484	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	3	0	0
T51	21747	0	0	0
T52	15627	0	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	3	0	0
T82	35111	0	0	0
T83	332221	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547549190	244105181	0	0
T1	24837	24748	0	0
T2	106995	3003	0	0
T3	141218	122679	0	0
T4	490271	385014	0	0
T6	546361	546267	0	0
T12	21884	5798	0	0
T13	38466	37404	0	0
T14	45007	44917	0	0
T15	21236	2692	0	0
T23	12834	12756	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	567	0	0
T2	106995	1	0	0
T3	141218	0	0	0
T4	490271	3	0	0
T5	0	6	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	0	1	0	0
T12	21884	1	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	1	0	0
T19	0	1	0	0
T20	0	4	0	0
T21	0	1	0	0
T23	12834	0	0	0
T27	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	558	0	0
T2	106995	1	0	0
T3	141218	0	0	0
T4	490271	3	0	0
T5	0	6	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	0	1	0	0
T12	21884	1	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	1	0	0
T19	0	1	0	0
T20	0	4	0	0
T21	0	1	0	0
T23	12834	0	0	0
T27	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	545	0	0
T2	106995	1	0	0
T3	141218	0	0	0
T4	490271	3	0	0
T5	0	5	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	0	1	0	0
T12	21884	1	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	1	0	0
T19	0	1	0	0
T20	0	4	0	0
T21	0	1	0	0
T23	12834	0	0	0
T27	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	530	0	0
T2	106995	1	0	0
T3	141218	0	0	0
T4	490271	3	0	0
T5	0	5	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	0	1	0	0
T12	21884	1	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	1	0	0
T19	0	1	0	0
T20	0	3	0	0
T21	0	1	0	0
T23	12834	0	0	0
T27	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	803	0	0
T3	141218	2	0	0
T4	490271	0	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	0	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T23	12834	0	0	0
T31	0	4	0	0
T32	0	8	0	0
T33	0	2	0	0
T34	0	12	0	0
T35	0	2	0	0
T77	0	1	0	0
T80	0	1	0	0
T81	0	13	0	0
T85	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	101004	0	0
T3	141218	240	0	0
T4	490271	0	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	0	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T23	12834	0	0	0
T31	0	1359	0	0
T32	0	1868	0	0
T33	0	533	0	0
T34	0	1177	0	0
T35	0	216	0	0
T77	0	567	0	0
T80	0	225	0	0
T81	0	579	0	0
T85	0	243	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	728	0	0
T3	141218	2	0	0
T4	490271	0	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	0	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T23	12834	0	0	0
T31	0	2	0	0
T32	0	8	0	0
T33	0	2	0	0
T34	0	12	0	0
T35	0	1	0	0
T77	0	1	0	0
T80	0	1	0	0
T81	0	12	0	0
T85	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	50	0	0
T29	0	1	0	0
T31	298470	2	0	0
T32	226431	0	0	0
T35	0	1	0	0
T38	38454	0	0	0
T39	424967	0	0	0
T45	0	1	0	0
T56	0	1	0	0
T75	0	1	0	0
T81	0	1	0	0
T85	29907	0	0	0
T86	1894	0	0	0
T87	902205	0	0	0
T89	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T95	59001	0	0	0
T96	23968	0	0	0
T97	46697	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	1155	0	0
T9	22202	169	0	0
T10	0	165	0	0
T11	0	171	0	0
T40	0	324	0	0
T41	0	326	0	0
T42	82283	0	0	0
T43	681451	0	0	0
T44	8976	0	0	0
T45	93509	0	0	0
T46	446227	0	0	0
T47	72144	0	0	0
T48	66449	0	0	0
T49	18783	0	0	0
T50	180304	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	945	0	0
T9	22202	139	0	0
T10	0	135	0	0
T11	0	141	0	0
T40	0	264	0	0
T41	0	266	0	0
T42	82283	0	0	0
T43	681451	0	0	0
T44	8976	0	0	0
T45	93509	0	0	0
T46	446227	0	0	0
T47	72144	0	0	0
T48	66449	0	0	0
T49	18783	0	0	0
T50	180304	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547547802	547479105	0	0
T1	24837	24749	0	0
T2	106995	106905	0	0
T3	141218	141069	0	0
T4	490271	490169	0	0
T6	546361	546268	0	0
T12	21884	21833	0	0
T13	38466	38411	0	0
T14	45007	44918	0	0
T15	21236	21144	0	0
T23	12834	12757	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	547533520	0	0
T1	24837	24749	0	0
T2	106995	106905	0	0
T3	141218	141069	0	0
T4	490271	490169	0	0
T6	546361	546268	0	0
T12	21884	21833	0	0
T13	38466	38411	0	0
T14	45007	44918	0	0
T15	21236	21144	0	0
T23	12834	12757	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T12,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T12,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T12,T13,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T12
1	0	1	Covered	T6,T13,T4
1	1	0	Covered	T2,T3,T15
1	1	1	Covered	T3,T5,T82

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T82
0	1	Covered	T3,T5,T82
1	0	Covered	T27,T22,T33

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T5,T82
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T27,T22,T33

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T82
1	0	Not Covered
1	1	Covered	T3,T5,T82

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T13
1	Covered	T4,T16,T82

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T12,T4,T24
1	Covered	T3,T13,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T13,T4
1	Covered	T12,T5,T22

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T13
1	Covered	T24,T5,T27

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T12,T13,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T12,T4,T24

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T12,T13
Phase1St	198	Covered	T3,T12,T13
Phase2St	215	Covered	T3,T12,T13
Phase3St	233	Covered	T3,T12,T13
TerminalSt	249	Covered	T3,T12,T13
TimeoutSt	159	Covered	T3,T5,T82

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T12,T13,T4
IdleSt->TimeoutSt	159	Covered	T3,T5,T82
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T107,T46,T93
Phase0St->Phase1St	198	Covered	T3,T12,T13
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T4,T22,T87
Phase1St->Phase2St	215	Covered	T3,T12,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T80,T36,T45
Phase2St->Phase3St	233	Covered	T3,T12,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T107,T108,T109
Phase3St->TerminalSt	249	Covered	T3,T12,T13
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T5,T27
TimeoutSt->Phase0St	172	Covered	T3,T5,T82

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T82
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T82
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T82
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T27
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T107,T46,T93
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T12,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T12,T13
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T87,T110,T81
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T12,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T12,T13
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T80,T36,T45
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T12,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T12,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T107,T108,T109
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T12,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T13,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T5,T82
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T12,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	547691932	242	0	0
CheckAccumTrig0_A	547691932	503	0	0
CheckAccumTrig1_A	547691932	17	0	0
CheckClr_A	547691932	233	0	0
CheckEn_A	547549190	221322475	0	0
CheckPhase0_A	547691932	567	0	0
CheckPhase1_A	547691932	554	0	0
CheckPhase2_A	547691932	540	0	0
CheckPhase3_A	547691932	527	0	0
CheckTimeout0_A	547691932	461	0	0
CheckTimeoutSt1_A	547691932	55928	0	0
CheckTimeoutSt2_A	547691932	376	0	0
CheckTimeoutStTrig_A	547691932	63	0	0
ErrorStAllEscAsserted_A	547691932	1167	0	0
ErrorStIsTerminal_A	547691932	957	0	0
EscStateOut_A	547547802	547479105	0	0
u_state_regs_A	547691932	547533520	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	242	0	0
T9	22202	39	0	0
T10	0	23	0	0
T11	0	19	0	0
T40	0	83	0	0
T41	0	78	0	0
T42	82283	0	0	0
T43	681451	0	0	0
T44	8976	0	0	0
T45	93509	0	0	0
T46	446227	0	0	0
T47	72144	0	0	0
T48	66449	0	0	0
T49	18783	0	0	0
T50	180304	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	503	0	0
T4	490271	3	0	0
T5	0	3	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	1	0	0
T13	38466	1	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T16	0	1	0	0
T19	162782	0	0	0
T21	0	1	0	0
T22	0	3	0	0
T23	12834	0	0	0
T24	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	17	0	0
T20	978224	0	0	0
T21	343881	0	0	0
T22	394396	1	0	0
T27	62484	1	0	0
T33	150507	1	0	0
T44	0	1	0	0
T51	21747	0	0	0
T52	15627	0	0	0
T59	0	1	0	0
T64	0	2	0	0
T66	0	1	0	0
T77	10992	0	0	0
T83	332221	0	0	0
T94	5315	0	0	0
T106	0	2	0	0
T111	0	1	0	0
T112	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	233	0	0
T3	141218	1	0	0
T4	490271	0	0	0
T5	0	1	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	0	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T23	12834	0	0	0
T27	0	1	0	0
T32	0	2	0	0
T34	0	4	0	0
T77	0	1	0	0
T82	0	2	0	0
T87	0	3	0	0
T107	0	5	0	0
T110	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547549190	221322475	0	0
T1	24837	24748	0	0
T2	106995	101374	0	0
T3	141218	103961	0	0
T4	490271	397018	0	0
T6	546361	3879	0	0
T12	21884	848	0	0
T13	38466	1588	0	0
T14	45007	44917	0	0
T15	21236	17688	0	0
T23	12834	12756	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	567	0	0
T3	141218	1	0	0
T4	490271	3	0	0
T5	0	5	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	1	0	0
T13	38466	1	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T16	0	1	0	0
T21	0	1	0	0
T23	12834	0	0	0
T24	0	1	0	0
T27	0	1	0	0
T82	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	554	0	0
T3	141218	1	0	0
T4	490271	2	0	0
T5	0	5	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	1	0	0
T13	38466	1	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T16	0	1	0	0
T21	0	1	0	0
T23	12834	0	0	0
T24	0	1	0	0
T27	0	1	0	0
T82	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	540	0	0
T3	141218	1	0	0
T4	490271	2	0	0
T5	0	5	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	1	0	0
T13	38466	1	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T16	0	1	0	0
T21	0	1	0	0
T23	12834	0	0	0
T24	0	1	0	0
T27	0	1	0	0
T82	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	527	0	0
T3	141218	1	0	0
T4	490271	2	0	0
T5	0	5	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	1	0	0
T13	38466	1	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T16	0	1	0	0
T21	0	1	0	0
T23	12834	0	0	0
T24	0	1	0	0
T27	0	1	0	0
T82	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	461	0	0
T3	141218	7	0	0
T4	490271	0	0	0
T5	0	4	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	0	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T22	0	2	0	0
T23	12834	0	0	0
T27	0	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	0	17	0	0
T82	0	3	0	0
T85	0	1	0	0
T86	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	55928	0	0
T3	141218	2483	0	0
T4	490271	0	0	0
T5	0	411	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	0	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T22	0	58	0	0
T23	12834	0	0	0
T27	0	16	0	0
T31	0	134	0	0
T32	0	377	0	0
T33	0	742	0	0
T82	0	12	0	0
T85	0	116	0	0
T86	0	437	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	376	0	0
T3	141218	6	0	0
T4	490271	0	0	0
T5	0	2	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	0	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T22	0	1	0	0
T23	12834	0	0	0
T27	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	16	0	0
T34	0	5	0	0
T85	0	1	0	0
T86	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	63	0	0
T3	141218	1	0	0
T4	490271	0	0	0
T5	0	2	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	0	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T23	12834	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T56	0	1	0	0
T81	0	2	0	0
T82	0	3	0	0
T113	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	1167	0	0
T9	22202	165	0	0
T10	0	156	0	0
T11	0	165	0	0
T40	0	345	0	0
T41	0	336	0	0
T42	82283	0	0	0
T43	681451	0	0	0
T44	8976	0	0	0
T45	93509	0	0	0
T46	446227	0	0	0
T47	72144	0	0	0
T48	66449	0	0	0
T49	18783	0	0	0
T50	180304	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	957	0	0
T9	22202	135	0	0
T10	0	126	0	0
T11	0	135	0	0
T40	0	285	0	0
T41	0	276	0	0
T42	82283	0	0	0
T43	681451	0	0	0
T44	8976	0	0	0
T45	93509	0	0	0
T46	446227	0	0	0
T47	72144	0	0	0
T48	66449	0	0	0
T49	18783	0	0	0
T50	180304	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547547802	547479105	0	0
T1	24837	24749	0	0
T2	106995	106905	0	0
T3	141218	141069	0	0
T4	490271	490169	0	0
T6	546361	546268	0	0
T12	21884	21833	0	0
T13	38466	38411	0	0
T14	45007	44918	0	0
T15	21236	21144	0	0
T23	12834	12757	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	547533520	0	0
T1	24837	24749	0	0
T2	106995	106905	0	0
T3	141218	141069	0	0
T4	490271	490169	0	0
T6	546361	546268	0	0
T12	21884	21833	0	0
T13	38466	38411	0	0
T14	45007	44918	0	0
T15	21236	21144	0	0
T23	12834	12757	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T26
1	1	1	Covered	T2,T3,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T13,T4,T8
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T3,T12,T27

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T27
0	1	Covered	T27,T52,T77
1	0	Covered	T12,T21,T53

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T12,T27
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T12,T21,T53

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T27
1	0	Not Covered
1	1	Covered	T27,T52,T77

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T12,T4,T24

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T12,T14,T4
1	Covered	T2,T3,T15

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T4,T5,T27

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T14,T8,T25

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T12,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T12,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T12

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T12
Phase1St	198	Covered	T2,T3,T12
Phase2St	215	Covered	T2,T3,T12
Phase3St	233	Covered	T2,T3,T12
TerminalSt	249	Covered	T2,T3,T12
TimeoutSt	159	Covered	T3,T12,T27

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T2,T3,T12
IdleSt->TimeoutSt	159	Covered	T3,T12,T27
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T31,T32,T36
Phase0St->Phase1St	198	Covered	T2,T3,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T22,T33,T34
Phase1St->Phase2St	215	Covered	T2,T3,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T4,T31,T38
Phase2St->Phase3St	233	Covered	T2,T3,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T25,T22,T39
Phase3St->TerminalSt	249	Covered	T2,T3,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T12,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T22,T52
TimeoutSt->Phase0St	172	Covered	T12,T27,T21

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T27
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T27,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T27
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T22,T52
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T114,T46,T56
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T33,T34,T37
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T38,T81
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T12,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T39,T115
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T12,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T12,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	547691932	167	0	0
CheckAccumTrig0_A	547691932	822	0	0
CheckAccumTrig1_A	547691932	37	0	0
CheckClr_A	547691932	393	0	0
CheckEn_A	547549190	217874333	0	0
CheckPhase0_A	547691932	873	0	0
CheckPhase1_A	547691932	845	0	0
CheckPhase2_A	547691932	825	0	0
CheckPhase3_A	547691932	792	0	0
CheckTimeout0_A	547691932	932	0	0
CheckTimeoutSt1_A	547691932	103248	0	0
CheckTimeoutSt2_A	547691932	831	0	0
CheckTimeoutStTrig_A	547691932	59	0	0
ErrorStAllEscAsserted_A	547691932	1099	0	0
ErrorStIsTerminal_A	547691932	889	0	0
EscStateOut_A	547547802	547479105	0	0
u_state_regs_A	547691932	547533520	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	167	0	0
T9	22202	30	0	0
T10	0	28	0	0
T11	0	35	0	0
T40	0	30	0	0
T41	0	44	0	0
T42	82283	0	0	0
T43	681451	0	0	0
T44	8976	0	0	0
T45	93509	0	0	0
T46	446227	0	0	0
T47	72144	0	0	0
T48	66449	0	0	0
T49	18783	0	0	0
T50	180304	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	822	0	0
T2	106995	1	0	0
T3	141218	1	0	0
T4	490271	7	0	0
T6	546361	0	0	0
T7	278675	1	0	0
T8	0	1	0	0
T12	21884	4	0	0
T13	38466	0	0	0
T14	45007	1	0	0
T15	21236	1	0	0
T23	12834	1	0	0
T24	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	37	0	0
T4	490271	0	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	1	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T19	162782	0	0	0
T21	0	1	0	0
T23	12834	0	0	0
T29	0	1	0	0
T53	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T60	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	393	0	0
T3	141218	1	0	0
T4	490271	2	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	4	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T23	12834	1	0	0
T25	0	2	0	0
T27	0	1	0	0
T33	0	11	0	0
T51	0	1	0	0
T52	0	2	0	0
T77	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547549190	217874333	0	0
T1	24837	709	0	0
T2	106995	14603	0	0
T3	141218	104809	0	0
T4	490271	138629	0	0
T6	546361	18127	0	0
T12	21884	836	0	0
T13	38466	32281	0	0
T14	45007	2058	0	0
T15	21236	4037	0	0
T23	12834	3447	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	873	0	0
T2	106995	1	0	0
T3	141218	1	0	0
T4	490271	7	0	0
T6	546361	0	0	0
T7	278675	1	0	0
T8	0	1	0	0
T12	21884	5	0	0
T13	38466	0	0	0
T14	45007	1	0	0
T15	21236	1	0	0
T23	12834	1	0	0
T24	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	845	0	0
T2	106995	1	0	0
T3	141218	1	0	0
T4	490271	7	0	0
T6	546361	0	0	0
T7	278675	1	0	0
T8	0	1	0	0
T12	21884	5	0	0
T13	38466	0	0	0
T14	45007	1	0	0
T15	21236	1	0	0
T23	12834	1	0	0
T24	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	825	0	0
T2	106995	1	0	0
T3	141218	1	0	0
T4	490271	6	0	0
T6	546361	0	0	0
T7	278675	1	0	0
T8	0	1	0	0
T12	21884	5	0	0
T13	38466	0	0	0
T14	45007	1	0	0
T15	21236	1	0	0
T23	12834	1	0	0
T24	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	792	0	0
T2	106995	1	0	0
T3	141218	1	0	0
T4	490271	6	0	0
T6	546361	0	0	0
T7	278675	1	0	0
T8	0	1	0	0
T12	21884	5	0	0
T13	38466	0	0	0
T14	45007	1	0	0
T15	21236	1	0	0
T23	12834	1	0	0
T24	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	932	0	0
T3	141218	5	0	0
T4	490271	0	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	1	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T23	12834	0	0	0
T27	0	1	0	0
T31	0	4	0	0
T33	0	1	0	0
T52	0	2	0	0
T77	0	2	0	0
T84	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	103248	0	0
T3	141218	736	0	0
T4	490271	0	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	1	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T22	0	257	0	0
T23	12834	0	0	0
T27	0	106	0	0
T31	0	525	0	0
T33	0	61	0	0
T52	0	242	0	0
T77	0	219	0	0
T84	0	142	0	0
T85	0	107	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	831	0	0
T3	141218	5	0	0
T4	490271	0	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	0	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T22	0	2	0	0
T23	12834	0	0	0
T31	0	3	0	0
T32	0	5	0	0
T33	0	1	0	0
T52	0	1	0	0
T77	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T87	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	59	0	0
T20	978224	0	0	0
T21	343881	0	0	0
T22	394396	0	0	0
T27	62484	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	150507	0	0	0
T36	0	3	0	0
T51	21747	0	0	0
T52	15627	1	0	0
T56	0	2	0	0
T77	10992	1	0	0
T81	0	2	0	0
T83	332221	0	0	0
T88	0	1	0	0
T91	0	1	0	0
T94	5315	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	1099	0	0
T9	22202	163	0	0
T10	0	150	0	0
T11	0	167	0	0
T40	0	294	0	0
T41	0	325	0	0
T42	82283	0	0	0
T43	681451	0	0	0
T44	8976	0	0	0
T45	93509	0	0	0
T46	446227	0	0	0
T47	72144	0	0	0
T48	66449	0	0	0
T49	18783	0	0	0
T50	180304	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	889	0	0
T9	22202	133	0	0
T10	0	120	0	0
T11	0	137	0	0
T40	0	234	0	0
T41	0	265	0	0
T42	82283	0	0	0
T43	681451	0	0	0
T44	8976	0	0	0
T45	93509	0	0	0
T46	446227	0	0	0
T47	72144	0	0	0
T48	66449	0	0	0
T49	18783	0	0	0
T50	180304	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547547802	547479105	0	0
T1	24837	24749	0	0
T2	106995	106905	0	0
T3	141218	141069	0	0
T4	490271	490169	0	0
T6	546361	546268	0	0
T12	21884	21833	0	0
T13	38466	38411	0	0
T14	45007	44918	0	0
T15	21236	21144	0	0
T23	12834	12757	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	547533520	0	0
T1	24837	24749	0	0
T2	106995	106905	0	0
T3	141218	141069	0	0
T4	490271	490169	0	0
T6	546361	546268	0	0
T12	21884	21833	0	0
T13	38466	38411	0	0
T14	45007	44918	0	0
T15	21236	21144	0	0
T23	12834	12757	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T12,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T12
1	0	1	Covered	T4,T5,T20
1	1	0	Covered	T12,T4,T5
1	1	1	Covered	T2,T3,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T32
1	0	Covered	T28,T59,T99

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T28,T59,T99

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T29,T30
1	1	Covered	T2,T3,T32

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T3,T7,T8

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T3,T12,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T15
1	Covered	T2,T4,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T15,T19,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T15,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T7,T8,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T12,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T15

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T12
Phase1St	198	Covered	T2,T3,T12
Phase2St	215	Covered	T2,T3,T12
Phase3St	233	Covered	T2,T3,T12
TerminalSt	249	Covered	T2,T3,T12
TimeoutSt	159	Covered	T2,T3,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T3,T12,T15
IdleSt->TimeoutSt	159	Covered	T2,T3,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T5,T31,T35
Phase0St->Phase1St	198	Covered	T2,T3,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T107,T80,T116
Phase1St->Phase2St	215	Covered	T2,T3,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T35,T36,T116
Phase2St->Phase3St	233	Covered	T2,T3,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T116,T117,T118
Phase3St->TerminalSt	249	Covered	T2,T3,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T4,T7
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T5,T22
TimeoutSt->Phase0St	172	Covered	T2,T3,T32

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T32
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T35,T36
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T107,T80,T116
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T35,T36,T116
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T12,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T116,T117,T118
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T12,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T7,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	547691932	230	0	0
CheckAccumTrig0_A	547691932	490	0	0
CheckAccumTrig1_A	547691932	18	0	0
CheckClr_A	547691932	203	0	0
CheckEn_A	547549190	230075401	0	0
CheckPhase0_A	547691932	536	0	0
CheckPhase1_A	547691932	526	0	0
CheckPhase2_A	547691932	512	0	0
CheckPhase3_A	547691932	502	0	0
CheckTimeout0_A	547691932	1139	0	0
CheckTimeoutSt1_A	547691932	108112	0	0
CheckTimeoutSt2_A	547691932	1074	0	0
CheckTimeoutStTrig_A	547691932	44	0	0
ErrorStAllEscAsserted_A	547691932	1205	0	0
ErrorStIsTerminal_A	547691932	995	0	0
EscStateOut_A	547547802	547479105	0	0
u_state_regs_A	547691932	547533520	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	230	0	0
T9	22202	45	0	0
T10	0	22	0	0
T11	0	25	0	0
T40	0	73	0	0
T41	0	65	0	0
T42	82283	0	0	0
T43	681451	0	0	0
T44	8976	0	0	0
T45	93509	0	0	0
T46	446227	0	0	0
T47	72144	0	0	0
T48	66449	0	0	0
T49	18783	0	0	0
T50	180304	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	490	0	0
T3	141218	1	0	0
T4	490271	1	0	0
T5	0	8	0	0
T6	546361	0	0	0
T7	278675	1	0	0
T8	100406	1	0	0
T12	21884	1	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T23	12834	0	0	0
T27	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	18	0	0
T28	168900	1	0	0
T53	108758	0	0	0
T59	0	1	0	0
T69	109896	0	0	0
T70	381640	0	0	0
T71	25567	0	0	0
T72	1636	0	0	0
T73	317567	0	0	0
T74	43920	0	0	0
T75	24952	0	0	0
T76	361295	0	0	0
T99	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	203	0	0
T3	141218	1	0	0
T4	490271	0	0	0
T5	0	3	0	0
T6	546361	0	0	0
T7	278675	1	0	0
T8	100406	0	0	0
T12	21884	0	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T23	12834	0	0	0
T27	0	1	0	0
T33	0	1	0	0
T35	0	4	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T107	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547549190	230075401	0	0
T1	24837	24748	0	0
T2	106995	3023	0	0
T3	141218	4321	0	0
T4	490271	426845	0	0
T6	546361	546267	0	0
T12	21884	6119	0	0
T13	38466	34573	0	0
T14	45007	10100	0	0
T15	21236	590	0	0
T23	12834	12756	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	536	0	0
T2	106995	1	0	0
T3	141218	2	0	0
T4	490271	1	0	0
T5	0	7	0	0
T6	546361	0	0	0
T7	278675	1	0	0
T8	0	1	0	0
T12	21884	1	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	1	0	0
T19	0	1	0	0
T23	12834	0	0	0
T27	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	526	0	0
T2	106995	1	0	0
T3	141218	2	0	0
T4	490271	1	0	0
T5	0	7	0	0
T6	546361	0	0	0
T7	278675	1	0	0
T8	0	1	0	0
T12	21884	1	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	1	0	0
T19	0	1	0	0
T23	12834	0	0	0
T27	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	512	0	0
T2	106995	1	0	0
T3	141218	2	0	0
T4	490271	1	0	0
T5	0	7	0	0
T6	546361	0	0	0
T7	278675	1	0	0
T8	0	1	0	0
T12	21884	1	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	1	0	0
T19	0	1	0	0
T23	12834	0	0	0
T27	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	502	0	0
T2	106995	1	0	0
T3	141218	2	0	0
T4	490271	1	0	0
T5	0	7	0	0
T6	546361	0	0	0
T7	278675	1	0	0
T8	0	1	0	0
T12	21884	1	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	1	0	0
T19	0	1	0	0
T23	12834	0	0	0
T27	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	1139	0	0
T2	106995	1	0	0
T3	141218	5	0	0
T4	490271	0	0	0
T5	0	2	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T12	21884	0	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T22	0	1	0	0
T23	12834	0	0	0
T31	0	4	0	0
T32	0	3	0	0
T77	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0
T87	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	108112	0	0
T2	106995	744	0	0
T3	141218	893	0	0
T4	490271	0	0	0
T5	0	89	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T12	21884	0	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T22	0	82	0	0
T23	12834	0	0	0
T31	0	1430	0	0
T32	0	667	0	0
T77	0	7	0	0
T84	0	88	0	0
T85	0	211	0	0
T87	0	16	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	1074	0	0
T3	141218	4	0	0
T4	490271	0	0	0
T5	0	2	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T8	100406	0	0	0
T12	21884	0	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T22	0	1	0	0
T23	12834	0	0	0
T31	0	4	0	0
T32	0	2	0	0
T34	0	2	0	0
T77	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0
T87	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	44	0	0
T2	106995	1	0	0
T3	141218	1	0	0
T4	490271	0	0	0
T6	546361	0	0	0
T7	278675	0	0	0
T12	21884	0	0	0
T13	38466	0	0	0
T14	45007	0	0	0
T15	21236	0	0	0
T23	12834	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T54	0	1	0	0
T56	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T93	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	1205	0	0
T9	22202	166	0	0
T10	0	169	0	0
T11	0	162	0	0
T40	0	381	0	0
T41	0	327	0	0
T42	82283	0	0	0
T43	681451	0	0	0
T44	8976	0	0	0
T45	93509	0	0	0
T46	446227	0	0	0
T47	72144	0	0	0
T48	66449	0	0	0
T49	18783	0	0	0
T50	180304	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	995	0	0
T9	22202	136	0	0
T10	0	139	0	0
T11	0	132	0	0
T40	0	321	0	0
T41	0	267	0	0
T42	82283	0	0	0
T43	681451	0	0	0
T44	8976	0	0	0
T45	93509	0	0	0
T46	446227	0	0	0
T47	72144	0	0	0
T48	66449	0	0	0
T49	18783	0	0	0
T50	180304	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547547802	547479105	0	0
T1	24837	24749	0	0
T2	106995	106905	0	0
T3	141218	141069	0	0
T4	490271	490169	0	0
T6	546361	546268	0	0
T12	21884	21833	0	0
T13	38466	38411	0	0
T14	45007	44918	0	0
T15	21236	21144	0	0
T23	12834	12757	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547691932	547533520	0	0
T1	24837	24749	0	0
T2	106995	106905	0	0
T3	141218	141069	0	0
T4	490271	490169	0	0
T6	546361	546268	0	0
T12	21884	21833	0	0
T13	38466	38411	0	0
T14	45007	44918	0	0
T15	21236	21144	0	0
T23	12834	12757	0	0