Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T42,T195
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T11,T12

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	17071	0	0
DisabledNoTrigBkwd_A	2147483647	661829	0	0
DisabledNoTrigFwd_A	2147483647	1230784408	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17071	0	0
T6	251474	0	0	0
T16	825654	0	0	0
T17	101643	0	0	0
T20	263327	0	0	0
T24	191046	0	0	0
T41	0	1886	0	0
T42	3838	385	0	0
T43	29887	0	0	0
T44	126913	0	0	0
T62	10647	0	0	0
T79	15907	0	0	0
T91	129200	0	0	0
T92	52291	0	0	0
T93	389041	0	0	0
T103	858478	0	0	0
T195	1260	444	0	0
T196	0	627	0	0
T197	1262	526	0	0
T198	3755	833	0	0
T199	0	1291	0	0
T200	0	524	0	0
T201	0	784	0	0
T202	0	589	0	0
T203	0	1537	0	0
T204	0	1003	0	0
T205	0	2001	0	0
T206	0	566	0	0
T207	0	757	0	0
T208	0	649	0	0
T209	0	836	0	0
T210	0	940	0	0
T211	0	465	0	0
T212	0	428	0	0
T213	22059	0	0	0
T214	27056	0	0	0
T215	172924	0	0	0
T216	47406	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	661829	0	0
T2	313650	395	0	0
T3	56526	0	0	0
T4	629572	2977	0	0
T5	524052	9544	0	0
T6	0	332	0	0
T7	1168224	1178	0	0
T11	1142800	395	0	0
T12	509688	40	0	0
T13	210288	0	0	0
T14	0	2802	0	0
T15	1545208	0	0	0
T16	0	8	0	0
T18	545000	9902	0	0
T19	0	3236	0	0
T21	307076	679	0	0
T41	10774	40	0	0
T42	0	1	0	0
T43	0	7	0	0
T44	0	36	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1230784408	0	0
T1	255780	186474	0	0
T2	627300	472444	0	0
T3	113052	81005	0	0
T4	629572	582304	0	0
T5	524052	828417	0	0
T7	1168224	314901	0	0
T11	1142800	301668	0	0
T12	509688	367725	0	0
T13	210288	206181	0	0
T21	307076	149209	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T42,T196,T201
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	561260441	4090	0	0
DisabledNoTrigBkwd_A	561260441	162878	0	0
DisabledNoTrigFwd_A	561260441	302125581	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	4090	0	0
T6	251474	0	0	0
T16	825654	0	0	0
T17	101643	0	0	0
T20	263327	0	0	0
T24	191046	0	0	0
T42	3838	385	0	0
T43	29887	0	0	0
T44	126913	0	0	0
T62	10647	0	0	0
T91	129200	0	0	0
T196	0	627	0	0
T201	0	784	0	0
T203	0	1537	0	0
T207	0	757	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	162878	0	0
T4	157393	140	0	0
T5	131013	90	0	0
T6	0	235	0	0
T7	292056	305	0	0
T11	285700	147	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T14	0	1243	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T21	76769	38	0	0
T41	5387	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	36	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	302125581	0	0
T1	63945	56625	0	0
T2	156825	156523	0	0
T3	28263	10487	0	0
T4	157393	144102	0	0
T5	131013	115611	0	0
T7	292056	18194	0	0
T11	285700	5233	0	0
T12	127422	127338	0	0
T13	52572	52492	0	0
T21	76769	5861	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T198,T199
1	1	Covered	T2,T3,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T12,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	561260441	5765	0	0
DisabledNoTrigBkwd_A	561260441	164351	0	0
DisabledNoTrigFwd_A	561260441	314145574	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	5765	0	0
T79	15907	0	0	0
T92	52291	0	0	0
T93	389041	0	0	0
T103	858478	0	0	0
T197	1262	526	0	0
T198	3755	833	0	0
T199	0	1291	0	0
T205	0	2001	0	0
T208	0	649	0	0
T211	0	465	0	0
T213	22059	0	0	0
T214	27056	0	0	0
T215	172924	0	0	0
T216	47406	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	164351	0	0
T2	156825	2	0	0
T3	28263	0	0	0
T4	157393	2719	0	0
T5	131013	1152	0	0
T6	0	30	0	0
T7	292056	0	0	0
T11	285700	0	0	0
T12	127422	5	0	0
T13	52572	0	0	0
T14	0	1549	0	0
T15	386302	0	0	0
T16	0	8	0	0
T18	0	8308	0	0
T19	0	11	0	0
T21	76769	204	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	314145574	0	0
T1	63945	63854	0	0
T2	156825	156393	0	0
T3	28263	14124	0	0
T4	157393	135729	0	0
T5	131013	479797	0	0
T7	292056	2325	0	0
T11	285700	274157	0	0
T12	127422	109944	0	0
T13	52572	52492	0	0
T21	76769	64324	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T13
1	0	Covered	T1,T3,T11
1	1	Covered	T2,T11,T13

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T195,T200,T202
1	1	Covered	T2,T11,T13

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T11,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	561260441	1557	0	0
DisabledNoTrigBkwd_A	561260441	187187	0	0
DisabledNoTrigFwd_A	561260441	299320324	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	1557	0	0
T27	343671	0	0	0
T50	41966	0	0	0
T51	105121	0	0	0
T118	999325	0	0	0
T195	1260	444	0	0
T200	0	524	0	0
T202	0	589	0	0
T217	203143	0	0	0
T218	5711	0	0	0
T219	33862	0	0	0
T220	385430	0	0	0
T221	321755	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	187187	0	0
T2	156825	393	0	0
T3	28263	0	0	0
T4	157393	11	0	0
T5	131013	7022	0	0
T6	0	66	0	0
T7	292056	873	0	0
T11	285700	175	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T14	0	7	0	0
T15	386302	0	0	0
T18	0	1591	0	0
T21	76769	265	0	0
T43	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	299320324	0	0
T1	63945	63854	0	0
T2	156825	3136	0	0
T3	28263	28197	0	0
T4	157393	155534	0	0
T5	131013	95246	0	0
T7	292056	2336	0	0
T11	285700	13716	0	0
T12	127422	127338	0	0
T13	52572	48705	0	0
T21	76769	11457	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T3,T11,T13
1	1	Covered	T1,T11,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T204,T206
1	1	Covered	T1,T11,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	561260441	5659	0	0
DisabledNoTrigBkwd_A	561260441	147413	0	0
DisabledNoTrigFwd_A	561260441	315192929	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	5659	0	0
T6	251474	0	0	0
T14	289732	0	0	0
T16	825654	0	0	0
T17	101643	0	0	0
T19	297161	0	0	0
T20	263327	0	0	0
T41	5387	1886	0	0
T42	3838	0	0	0
T43	29887	0	0	0
T62	10647	0	0	0
T204	0	1003	0	0
T206	0	566	0	0
T209	0	836	0	0
T210	0	940	0	0
T212	0	428	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	147413	0	0
T4	157393	107	0	0
T5	131013	1280	0	0
T6	0	1	0	0
T7	292056	0	0	0
T11	285700	73	0	0
T12	127422	35	0	0
T13	52572	0	0	0
T14	0	3	0	0
T15	386302	0	0	0
T18	272500	3	0	0
T19	0	3225	0	0
T21	76769	172	0	0
T41	5387	40	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	315192929	0	0
T1	63945	2141	0	0
T2	156825	156392	0	0
T3	28263	28197	0	0
T4	157393	146939	0	0
T5	131013	137763	0	0
T7	292056	292046	0	0
T11	285700	8562	0	0
T12	127422	3105	0	0
T13	52572	52492	0	0
T21	76769	67567	0	0