Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	100.00	89.36		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T11,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T12,T13
1	0	1	Covered	T1,T2,T11
1	1	0	Covered	T3,T12,T13
1	1	1	Covered	T3,T12,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T13
0	1	Covered	T3,T4,T6
1	0	Covered	T5,T21,T6

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T12,T13
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T21,T6

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T13
1	0	Not Covered
1	1	Covered	T3,T4,T6

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T4,T5,T21

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T4,T5,T21

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T2,T4,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T12
1	Covered	T2,T3,T11

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T12,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T11,T12

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T11
Phase1St	198	Covered	T2,T3,T11
Phase2St	215	Covered	T2,T3,T11
Phase3St	233	Covered	T2,T3,T11
TerminalSt	249	Covered	T2,T3,T11
TimeoutSt	159	Covered	T3,T12,T13

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T2,T11,T12
IdleSt->TimeoutSt	159	Covered	T3,T12,T13
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T6,T22,T23
Phase0St->Phase1St	198	Covered	T2,T3,T11
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T4,T24,T25
Phase1St->Phase2St	215	Covered	T2,T3,T11
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T5,T24,T26
Phase2St->Phase3St	233	Covered	T2,T3,T11
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T6,T27,T28
Phase3St->TerminalSt	249	Covered	T2,T3,T11
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T3,T4,T5
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T3,T12,T13
TimeoutSt->Phase0St	172	Covered	T3,T4,T5

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T13
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T29,T27
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T24,T25
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T24,T26
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T28,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	732	0	0
CheckAccumTrig0_A	2147483647	2051	0	0
CheckAccumTrig1_A	2147483647	122	0	0
CheckClr_A	2147483647	917	0	0
CheckEn_A	2147483647	965192130	0	0
CheckPhase0_A	2147483647	2328	0	0
CheckPhase1_A	2147483647	2261	0	0
CheckPhase2_A	2147483647	2234	0	0
CheckPhase3_A	2147483647	2205	0	0
CheckTimeout0_A	2147483647	4818	0	0
CheckTimeoutSt1_A	2147483647	589762	0	0
CheckTimeoutSt2_A	2147483647	4451	0	0
CheckTimeoutStTrig_A	2147483647	224	0	0
ErrorStAllEscAsserted_A	2147483647	4480	0	0
ErrorStIsTerminal_A	2147483647	3640	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	732	0	0
T8	767364	202	0	0
T9	0	102	0	0
T10	0	96	0	0
T30	2014160	0	0	0
T31	0	194	0	0
T32	0	138	0	0
T33	178336	0	0	0
T34	1889452	0	0	0
T35	90692	0	0	0
T36	41180	0	0	0
T37	671912	0	0	0
T38	457568	0	0	0
T39	1115352	0	0	0
T40	68036	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2051	0	0
T2	313650	2	0	0
T3	56526	0	0	0
T4	629572	17	0	0
T5	524052	15	0	0
T6	0	8	0	0
T7	1168224	4	0	0
T11	1142800	3	0	0
T12	509688	2	0	0
T13	210288	0	0	0
T14	0	12	0	0
T15	1545208	0	0	0
T16	0	1	0	0
T18	545000	13	0	0
T19	0	2	0	0
T20	0	8	0	0
T21	307076	1	0	0
T41	10774	1	0	0
T42	0	1	0	0
T43	0	6	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	122	0	0
T5	131013	1	0	0
T6	502948	1	0	0
T7	876168	0	0	0
T14	869196	0	0	0
T15	1158906	0	0	0
T18	817500	0	0	0
T19	891483	0	0	0
T21	230307	2	0	0
T25	18798	0	0	0
T40	0	1	0	0
T41	16161	0	0	0
T42	11514	0	0	0
T44	126913	0	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	4	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	31941	0	0	0
T63	119416	0	0	0
T64	279686	0	0	0
T65	98384	0	0	0
T66	331184	0	0	0
T67	955525	0	0	0
T68	15642	0	0	0
T69	353524	0	0	0
T70	34868	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	917	0	0
T3	28263	1	0	0
T4	472179	5	0	0
T5	393039	2	0	0
T6	251474	2	0	0
T7	1168224	2	0	0
T11	285700	0	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T14	869196	8	0	0
T15	1545208	0	0	0
T18	1090000	10	0	0
T19	891483	0	0	0
T20	0	6	0	0
T21	307076	0	0	0
T23	0	1	0	0
T24	0	6	0	0
T25	0	1	0	0
T41	16161	0	0	0
T42	11514	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	6	0	0
T46	0	3	0	0
T47	0	1	0	0
T62	10647	0	0	0
T64	0	1	0	0
T66	0	1	0	0
T69	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	965192130	0	0
T1	255780	186471	0	0
T2	627300	318366	0	0
T3	113052	81002	0	0
T4	629572	483560	0	0
T5	524052	1458035	0	0
T7	1168224	314901	0	0
T11	1142800	301667	0	0
T12	509688	273709	0	0
T13	210288	206177	0	0
T21	307076	88837	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2328	0	0
T2	313650	2	0	0
T3	84789	1	0	0
T4	629572	19	0	0
T5	524052	16	0	0
T6	0	11	0	0
T7	1168224	4	0	0
T11	1142800	3	0	0
T12	509688	2	0	0
T13	210288	0	0	0
T14	0	12	0	0
T15	1545208	0	0	0
T16	0	1	0	0
T18	545000	13	0	0
T19	0	2	0	0
T21	307076	4	0	0
T41	5387	1	0	0
T42	0	1	0	0
T43	0	4	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2261	0	0
T2	313650	2	0	0
T3	84789	1	0	0
T4	629572	18	0	0
T5	524052	16	0	0
T6	0	11	0	0
T7	1168224	4	0	0
T11	1142800	3	0	0
T12	509688	2	0	0
T13	210288	0	0	0
T14	0	12	0	0
T15	1545208	0	0	0
T16	0	1	0	0
T18	545000	13	0	0
T19	0	2	0	0
T21	307076	4	0	0
T41	5387	1	0	0
T42	0	1	0	0
T43	0	4	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2234	0	0
T2	313650	2	0	0
T3	84789	1	0	0
T4	629572	18	0	0
T5	524052	15	0	0
T6	0	11	0	0
T7	1168224	4	0	0
T11	1142800	3	0	0
T12	509688	2	0	0
T13	210288	0	0	0
T14	0	12	0	0
T15	1545208	0	0	0
T16	0	1	0	0
T18	545000	13	0	0
T19	0	2	0	0
T21	307076	4	0	0
T41	5387	1	0	0
T42	0	1	0	0
T43	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2205	0	0
T2	313650	2	0	0
T3	84789	1	0	0
T4	629572	18	0	0
T5	524052	15	0	0
T6	0	10	0	0
T7	1168224	4	0	0
T11	1142800	3	0	0
T12	509688	2	0	0
T13	210288	0	0	0
T14	0	12	0	0
T15	1545208	0	0	0
T16	0	1	0	0
T18	545000	13	0	0
T19	0	2	0	0
T21	307076	4	0	0
T41	5387	1	0	0
T42	0	1	0	0
T43	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4818	0	0
T3	56526	4	0	0
T4	629572	5	0	0
T5	524052	92	0	0
T6	0	11	0	0
T7	1168224	0	0	0
T11	571400	0	0	0
T12	382266	2	0	0
T13	210288	1	0	0
T14	579464	0	0	0
T15	1545208	0	0	0
T18	1090000	1	0	0
T19	297161	0	0	0
T21	307076	3	0	0
T22	0	3	0	0
T25	0	1	0	0
T41	10774	0	0	0
T43	0	3	0	0
T44	0	3	0	0
T47	0	1	0	0
T64	0	1	0	0
T66	0	7	0	0
T69	0	49	0	0
T70	0	11	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	589762	0	0
T3	56526	636	0	0
T4	629572	704	0	0
T5	524052	9934	0	0
T6	0	1507	0	0
T7	1168224	0	0	0
T11	571400	0	0	0
T12	382266	355	0	0
T13	210288	736	0	0
T14	579464	0	0	0
T15	1545208	0	0	0
T18	1090000	102	0	0
T19	297161	0	0	0
T21	307076	415	0	0
T22	0	294	0	0
T25	0	198	0	0
T41	10774	0	0	0
T43	0	244	0	0
T44	0	127	0	0
T47	0	1	0	0
T49	0	1325	0	0
T64	0	106	0	0
T66	0	1369	0	0
T69	0	6500	0	0
T70	0	507	0	0
T73	0	32	0	0
T74	0	136	0	0
T75	0	251	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4451	0	0
T3	56526	3	0	0
T4	629572	3	0	0
T5	524052	91	0	0
T6	0	5	0	0
T7	1168224	0	0	0
T11	571400	0	0	0
T12	382266	2	0	0
T13	210288	1	0	0
T14	579464	0	0	0
T15	1545208	0	0	0
T18	1090000	1	0	0
T19	297161	0	0	0
T21	307076	0	0	0
T22	0	3	0	0
T23	0	12	0	0
T25	0	1	0	0
T41	10774	0	0	0
T43	0	3	0	0
T44	0	2	0	0
T49	0	5	0	0
T64	0	1	0	0
T66	0	7	0	0
T69	0	49	0	0
T70	0	11	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	224	0	0
T3	28263	1	0	0
T4	314786	2	0	0
T5	262026	0	0	0
T6	251474	3	0	0
T7	584112	0	0	0
T11	285700	0	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T14	289732	0	0	0
T15	772604	0	0	0
T16	825654	0	0	0
T17	101643	0	0	0
T18	545000	0	0	0
T19	297161	0	0	0
T20	263327	0	0	0
T21	153538	0	0	0
T23	0	1	0	0
T24	191046	0	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	5387	0	0	0
T42	3838	0	0	0
T43	29887	0	0	0
T49	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	4	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	0	2	0	0
T84	0	3	0	0
T85	0	1	0	0
T86	0	4	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	129200	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4480	0	0
T8	767364	1257	0	0
T9	0	659	0	0
T10	0	636	0	0
T30	2014160	0	0	0
T31	0	1287	0	0
T32	0	641	0	0
T33	178336	0	0	0
T34	1889452	0	0	0
T35	90692	0	0	0
T36	41180	0	0	0
T37	671912	0	0	0
T38	457568	0	0	0
T39	1115352	0	0	0
T40	68036	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3640	0	0
T8	767364	1017	0	0
T9	0	539	0	0
T10	0	516	0	0
T30	2014160	0	0	0
T31	0	1047	0	0
T32	0	521	0	0
T33	178336	0	0	0
T34	1889452	0	0	0
T35	90692	0	0	0
T36	41180	0	0	0
T37	671912	0	0	0
T38	457568	0	0	0
T39	1115352	0	0	0
T40	68036	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	255780	255416	0	0
T2	627300	627272	0	0
T3	113052	112788	0	0
T4	629572	629400	0	0
T5	524052	523748	0	0
T7	1168224	1168184	0	0
T11	1142800	1142404	0	0
T12	509688	509352	0	0
T13	210288	209968	0	0
T21	307076	306696	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	255780	255416	0	0
T2	627300	627272	0	0
T3	113052	112788	0	0
T4	629572	629400	0	0
T5	524052	523748	0	0
T7	1168224	1168184	0	0
T11	1142800	1142404	0	0
T12	509688	509352	0	0
T13	210288	209968	0	0
T21	307076	306696	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T11,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T11,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T11,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T3,T12,T13
1	1	1	Covered	T3,T4,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T23
1	0	Covered	T5,T6,T45

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T45

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T3,T4,T23

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T11,T4
1	Covered	T4,T21,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T11,T4
1	Covered	T4,T5,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T11,T4
1	Covered	T4,T5,T7

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T21
1	Covered	T3,T11,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T11,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T11,T4
Phase1St	198	Covered	T3,T11,T4
Phase2St	215	Covered	T3,T11,T4
Phase3St	233	Covered	T3,T11,T4
TerminalSt	249	Covered	T3,T11,T4
TimeoutSt	159	Covered	T3,T4,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T11,T4,T5
IdleSt->TimeoutSt	159	Covered	T3,T4,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T23,T92,T93
Phase0St->Phase1St	198	Covered	T3,T11,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T69,T45,T46
Phase1St->Phase2St	215	Covered	T3,T11,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T5,T26,T81
Phase2St->Phase3St	233	Covered	T3,T11,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T28,T84,T56
Phase3St->TerminalSt	249	Covered	T3,T11,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T4,T5
TimeoutSt->Phase0St	172	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T92,T93,T94
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T11,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T11,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T69,T45,T46
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T11,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T11,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T26,T81
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T11,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T11,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T28,T84,T56
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T11,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T11,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T11,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	561260441	206	0	0
CheckAccumTrig0_A	561260441	749	0	0
CheckAccumTrig1_A	561260441	57	0	0
CheckClr_A	561260441	378	0	0
CheckEn_A	560975925	255865667	0	0
CheckPhase0_A	561260441	834	0	0
CheckPhase1_A	561260441	801	0	0
CheckPhase2_A	561260441	790	0	0
CheckPhase3_A	561260441	777	0	0
CheckTimeout0_A	561260441	1531	0	0
CheckTimeoutSt1_A	561260441	183758	0	0
CheckTimeoutSt2_A	561260441	1414	0	0
CheckTimeoutStTrig_A	561260441	54	0	0
ErrorStAllEscAsserted_A	561260441	1144	0	0
ErrorStIsTerminal_A	561260441	934	0	0
EscStateOut_A	560970317	560904326	0	0
u_state_regs_A	561260441	561104358	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	206	0	0
T8	191841	39	0	0
T9	0	34	0	0
T10	0	22	0	0
T30	503540	0	0	0
T31	0	63	0	0
T32	0	48	0	0
T33	44584	0	0	0
T34	472363	0	0	0
T35	22673	0	0	0
T36	10295	0	0	0
T37	167978	0	0	0
T38	114392	0	0	0
T39	278838	0	0	0
T40	17009	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	749	0	0
T4	157393	4	0	0
T5	131013	4	0	0
T6	0	3	0	0
T7	292056	2	0	0
T11	285700	1	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T14	0	3	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T21	76769	1	0	0
T41	5387	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	57	0	0
T5	131013	1	0	0
T6	0	1	0	0
T7	292056	0	0	0
T14	289732	0	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T19	297161	0	0	0
T21	76769	0	0	0
T41	5387	0	0	0
T42	3838	0	0	0
T45	0	2	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T62	10647	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	378	0	0
T3	28263	1	0	0
T4	157393	1	0	0
T5	131013	2	0	0
T6	0	1	0	0
T7	292056	1	0	0
T11	285700	0	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T14	0	2	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T21	76769	0	0	0
T45	0	6	0	0
T46	0	2	0	0
T64	0	1	0	0
T69	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560975925	255865667	0	0
T1	63945	56624	0	0
T2	156825	156523	0	0
T3	28263	10486	0	0
T4	157393	103694	0	0
T5	131013	961550	0	0
T7	292056	18194	0	0
T11	285700	5233	0	0
T12	127422	127337	0	0
T13	52572	52491	0	0
T21	76769	5861	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	834	0	0
T3	28263	1	0	0
T4	157393	5	0	0
T5	131013	5	0	0
T6	0	4	0	0
T7	292056	2	0	0
T11	285700	1	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T14	0	3	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T21	76769	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	801	0	0
T3	28263	1	0	0
T4	157393	5	0	0
T5	131013	5	0	0
T6	0	4	0	0
T7	292056	2	0	0
T11	285700	1	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T14	0	3	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T21	76769	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	790	0	0
T3	28263	1	0	0
T4	157393	5	0	0
T5	131013	4	0	0
T6	0	4	0	0
T7	292056	2	0	0
T11	285700	1	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T14	0	3	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T21	76769	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	777	0	0
T3	28263	1	0	0
T4	157393	5	0	0
T5	131013	4	0	0
T6	0	4	0	0
T7	292056	2	0	0
T11	285700	1	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T14	0	3	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T21	76769	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	1531	0	0
T3	28263	2	0	0
T4	157393	2	0	0
T5	131013	18	0	0
T6	0	5	0	0
T7	292056	0	0	0
T11	285700	0	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T21	76769	0	0	0
T25	0	1	0	0
T64	0	1	0	0
T66	0	3	0	0
T69	0	21	0	0
T70	0	1	0	0
T73	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	183758	0	0
T3	28263	274	0	0
T4	157393	538	0	0
T5	131013	2081	0	0
T6	0	528	0	0
T7	292056	0	0	0
T11	285700	0	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T21	76769	0	0	0
T25	0	198	0	0
T64	0	106	0	0
T66	0	1025	0	0
T69	0	2596	0	0
T70	0	43	0	0
T73	0	32	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	1414	0	0
T3	28263	1	0	0
T4	157393	1	0	0
T5	131013	17	0	0
T6	0	2	0	0
T7	292056	0	0	0
T11	285700	0	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T21	76769	0	0	0
T25	0	1	0	0
T64	0	1	0	0
T66	0	3	0	0
T69	0	21	0	0
T70	0	1	0	0
T73	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	54	0	0
T3	28263	1	0	0
T4	157393	1	0	0
T5	131013	0	0	0
T7	292056	0	0	0
T11	285700	0	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T21	76769	0	0	0
T23	0	1	0	0
T40	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	1144	0	0
T8	191841	311	0	0
T9	0	166	0	0
T10	0	161	0	0
T30	503540	0	0	0
T31	0	343	0	0
T32	0	163	0	0
T33	44584	0	0	0
T34	472363	0	0	0
T35	22673	0	0	0
T36	10295	0	0	0
T37	167978	0	0	0
T38	114392	0	0	0
T39	278838	0	0	0
T40	17009	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	934	0	0
T8	191841	251	0	0
T9	0	136	0	0
T10	0	131	0	0
T30	503540	0	0	0
T31	0	283	0	0
T32	0	133	0	0
T33	44584	0	0	0
T34	472363	0	0	0
T35	22673	0	0	0
T36	10295	0	0	0
T37	167978	0	0	0
T38	114392	0	0	0
T39	278838	0	0	0
T40	17009	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560970317	560904326	0	0
T1	63945	63854	0	0
T2	156825	156818	0	0
T3	28263	28197	0	0
T4	157393	157350	0	0
T5	131013	130937	0	0
T7	292056	292046	0	0
T11	285700	285601	0	0
T12	127422	127338	0	0
T13	52572	52492	0	0
T21	76769	76674	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	561104358	0	0
T1	63945	63854	0	0
T2	156825	156818	0	0
T3	28263	28197	0	0
T4	157393	157350	0	0
T5	131013	130937	0	0
T7	292056	292046	0	0
T11	285700	285601	0	0
T12	127422	127338	0	0
T13	52572	52492	0	0
T21	76769	76674	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T12,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T12,T4
1	0	1	Covered	T11,T4,T5
1	1	0	Covered	T3,T13,T4
1	1	1	Covered	T3,T12,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T4
0	1	Covered	T4,T77,T78
1	0	Covered	T21,T51,T52

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T12,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T21,T51,T52

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T4
1	0	Not Covered
1	1	Covered	T4,T77,T78

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T12,T4
1	Covered	T4,T5,T21

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T12,T4
1	Covered	T5,T14,T66

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12,T4,T5
1	Covered	T2,T18,T6

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T12,T4,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T12,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T12,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T12,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T12,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T12,T4
Phase1St	198	Covered	T2,T12,T4
Phase2St	215	Covered	T2,T12,T4
Phase3St	233	Covered	T2,T12,T4
TerminalSt	249	Covered	T2,T12,T4
TimeoutSt	159	Covered	T3,T12,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T2,T12,T4
IdleSt->TimeoutSt	159	Covered	T3,T12,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T22,T27,T95
Phase0St->Phase1St	198	Covered	T2,T12,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T4,T24,T71
Phase1St->Phase2St	215	Covered	T2,T12,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T24,T96,T90
Phase2St->Phase3St	233	Covered	T2,T12,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T97,T98,T99
Phase3St->TerminalSt	249	Covered	T2,T12,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T5,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T12,T4
TimeoutSt->Phase0St	172	Covered	T4,T21,T51

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T21,T51
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T100,T101
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T12,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T12,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T24,T71
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T12,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T12,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T24,T96,T90
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T12,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T12,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T97,T99,T102
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T12,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T12,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T14,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T12,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	561260441	181	0	0
CheckAccumTrig0_A	561260441	432	0	0
CheckAccumTrig1_A	561260441	26	0	0
CheckClr_A	561260441	179	0	0
CheckEn_A	560975925	230954922	0	0
CheckPhase0_A	561260441	511	0	0
CheckPhase1_A	561260441	496	0	0
CheckPhase2_A	561260441	492	0	0
CheckPhase3_A	561260441	486	0	0
CheckTimeout0_A	561260441	1891	0	0
CheckTimeoutSt1_A	561260441	228901	0	0
CheckTimeoutSt2_A	561260441	1795	0	0
CheckTimeoutStTrig_A	561260441	65	0	0
ErrorStAllEscAsserted_A	561260441	1130	0	0
ErrorStIsTerminal_A	561260441	920	0	0
EscStateOut_A	560970317	560904326	0	0
u_state_regs_A	561260441	561104358	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	181	0	0
T8	191841	61	0	0
T9	0	12	0	0
T10	0	38	0	0
T30	503540	0	0	0
T31	0	49	0	0
T32	0	21	0	0
T33	44584	0	0	0
T34	472363	0	0	0
T35	22673	0	0	0
T36	10295	0	0	0
T37	167978	0	0	0
T38	114392	0	0	0
T39	278838	0	0	0
T40	17009	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	432	0	0
T2	156825	1	0	0
T3	28263	0	0	0
T4	157393	6	0	0
T5	131013	2	0	0
T6	0	2	0	0
T7	292056	0	0	0
T11	285700	0	0	0
T12	127422	1	0	0
T13	52572	0	0	0
T14	0	5	0	0
T15	386302	0	0	0
T16	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	7	0	0
T21	76769	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	26	0	0
T6	251474	0	0	0
T7	292056	0	0	0
T14	289732	0	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T19	297161	0	0	0
T21	76769	1	0	0
T40	0	1	0	0
T41	5387	0	0	0
T42	3838	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	10647	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	179	0	0
T4	157393	3	0	0
T5	131013	0	0	0
T7	292056	0	0	0
T14	289732	4	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T19	297161	0	0	0
T20	0	6	0	0
T21	76769	0	0	0
T23	0	1	0	0
T24	0	5	0	0
T41	5387	0	0	0
T42	3838	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T66	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560975925	230954922	0	0
T1	63945	63853	0	0
T2	156825	3543	0	0
T3	28263	14124	0	0
T4	157393	96226	0	0
T5	131013	282742	0	0
T7	292056	2325	0	0
T11	285700	274156	0	0
T12	127422	15930	0	0
T13	52572	52491	0	0
T21	76769	6622	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	511	0	0
T2	156825	1	0	0
T3	28263	0	0	0
T4	157393	7	0	0
T5	131013	2	0	0
T6	0	2	0	0
T7	292056	0	0	0
T11	285700	0	0	0
T12	127422	1	0	0
T13	52572	0	0	0
T14	0	5	0	0
T15	386302	0	0	0
T16	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T21	76769	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	496	0	0
T2	156825	1	0	0
T3	28263	0	0	0
T4	157393	6	0	0
T5	131013	2	0	0
T6	0	2	0	0
T7	292056	0	0	0
T11	285700	0	0	0
T12	127422	1	0	0
T13	52572	0	0	0
T14	0	5	0	0
T15	386302	0	0	0
T16	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T21	76769	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	492	0	0
T2	156825	1	0	0
T3	28263	0	0	0
T4	157393	6	0	0
T5	131013	2	0	0
T6	0	2	0	0
T7	292056	0	0	0
T11	285700	0	0	0
T12	127422	1	0	0
T13	52572	0	0	0
T14	0	5	0	0
T15	386302	0	0	0
T16	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T21	76769	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	486	0	0
T2	156825	1	0	0
T3	28263	0	0	0
T4	157393	6	0	0
T5	131013	2	0	0
T6	0	2	0	0
T7	292056	0	0	0
T11	285700	0	0	0
T12	127422	1	0	0
T13	52572	0	0	0
T14	0	5	0	0
T15	386302	0	0	0
T16	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T21	76769	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	1891	0	0
T3	28263	2	0	0
T4	157393	3	0	0
T5	131013	19	0	0
T6	0	1	0	0
T7	292056	0	0	0
T11	285700	0	0	0
T12	127422	1	0	0
T13	52572	0	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T21	76769	1	0	0
T22	0	3	0	0
T43	0	1	0	0
T66	0	3	0	0
T70	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	228901	0	0
T3	28263	362	0	0
T4	157393	166	0	0
T5	131013	2001	0	0
T6	0	317	0	0
T7	292056	0	0	0
T11	285700	0	0	0
T12	127422	177	0	0
T13	52572	0	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T21	76769	2	0	0
T22	0	294	0	0
T43	0	167	0	0
T66	0	192	0	0
T70	0	330	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	1795	0	0
T3	28263	2	0	0
T4	157393	2	0	0
T5	131013	19	0	0
T6	0	1	0	0
T7	292056	0	0	0
T11	285700	0	0	0
T12	127422	1	0	0
T13	52572	0	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T21	76769	0	0	0
T22	0	3	0	0
T43	0	1	0	0
T66	0	3	0	0
T70	0	7	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	65	0	0
T4	157393	1	0	0
T5	131013	0	0	0
T7	292056	0	0	0
T14	289732	0	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T19	297161	0	0	0
T21	76769	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	5387	0	0	0
T42	3838	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T86	0	4	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	1130	0	0
T8	191841	336	0	0
T9	0	156	0	0
T10	0	158	0	0
T30	503540	0	0	0
T31	0	319	0	0
T32	0	161	0	0
T33	44584	0	0	0
T34	472363	0	0	0
T35	22673	0	0	0
T36	10295	0	0	0
T37	167978	0	0	0
T38	114392	0	0	0
T39	278838	0	0	0
T40	17009	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	920	0	0
T8	191841	276	0	0
T9	0	126	0	0
T10	0	128	0	0
T30	503540	0	0	0
T31	0	259	0	0
T32	0	131	0	0
T33	44584	0	0	0
T34	472363	0	0	0
T35	22673	0	0	0
T36	10295	0	0	0
T37	167978	0	0	0
T38	114392	0	0	0
T39	278838	0	0	0
T40	17009	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560970317	560904326	0	0
T1	63945	63854	0	0
T2	156825	156818	0	0
T3	28263	28197	0	0
T4	157393	157350	0	0
T5	131013	130937	0	0
T7	292056	292046	0	0
T11	285700	285601	0	0
T12	127422	127338	0	0
T13	52572	52492	0	0
T21	76769	76674	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	561104358	0	0
T1	63945	63854	0	0
T2	156825	156818	0	0
T3	28263	28197	0	0
T4	157393	157350	0	0
T5	131013	130937	0	0
T7	292056	292046	0	0
T11	285700	285601	0	0
T12	127422	127338	0	0
T13	52572	52492	0	0
T21	76769	76674	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T11,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T11,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T11,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T11,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T4,T5
1	0	1	Covered	T11,T4,T5
1	1	0	Covered	T3,T12,T13
1	1	1	Covered	T13,T5,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T5,T6
0	1	Covered	T6,T49,T79
1	0	Covered	T21,T47,T49

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T13,T5,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T21,T47,T49

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T5,T21
1	0	Not Covered
1	1	Covered	T6,T49,T79

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T4
1	Covered	T5,T14,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T4
1	Covered	T4,T21,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T4
1	Covered	T4,T5,T7

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T21
1	Covered	T2,T11,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T11,T4
Phase1St	198	Covered	T2,T11,T4
Phase2St	215	Covered	T2,T11,T4
Phase3St	233	Covered	T2,T11,T4
TerminalSt	249	Covered	T2,T11,T4
TimeoutSt	159	Covered	T13,T5,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T2,T11,T4
IdleSt->TimeoutSt	159	Covered	T13,T5,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T22,T37
Phase0St->Phase1St	198	Covered	T2,T11,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T25,T27,T58
Phase1St->Phase2St	215	Covered	T2,T11,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T103,T97,T104
Phase2St->Phase3St	233	Covered	T2,T11,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T6,T105,T106
Phase3St->TerminalSt	249	Covered	T2,T11,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T5,T7
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T13,T5,T6
TimeoutSt->Phase0St	172	Covered	T21,T6,T47

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T5,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T6,T47
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T13,T5,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T5,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T107,T89,T100
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T11,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T11,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T25,T27,T89
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T11,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T11,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T103,T97,T104
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T11,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T11,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T105,T106,T108
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T11,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T11,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T7,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T11,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	561260441	177	0	0
CheckAccumTrig0_A	561260441	442	0	0
CheckAccumTrig1_A	561260441	26	0	0
CheckClr_A	561260441	192	0	0
CheckEn_A	560975925	237975764	0	0
CheckPhase0_A	561260441	498	0	0
CheckPhase1_A	561260441	485	0	0
CheckPhase2_A	561260441	478	0	0
CheckPhase3_A	561260441	474	0	0
CheckTimeout0_A	561260441	455	0	0
CheckTimeoutSt1_A	561260441	57675	0	0
CheckTimeoutSt2_A	561260441	380	0	0
CheckTimeoutStTrig_A	561260441	46	0	0
ErrorStAllEscAsserted_A	561260441	1077	0	0
ErrorStIsTerminal_A	561260441	867	0	0
EscStateOut_A	560970317	560904326	0	0
u_state_regs_A	561260441	561104358	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	177	0	0
T8	191841	54	0	0
T9	0	14	0	0
T10	0	23	0	0
T30	503540	0	0	0
T31	0	42	0	0
T32	0	44	0	0
T33	44584	0	0	0
T34	472363	0	0	0
T35	22673	0	0	0
T36	10295	0	0	0
T37	167978	0	0	0
T38	114392	0	0	0
T39	278838	0	0	0
T40	17009	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	442	0	0
T2	156825	1	0	0
T3	28263	0	0	0
T4	157393	4	0	0
T5	131013	5	0	0
T6	0	2	0	0
T7	292056	2	0	0
T11	285700	1	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T14	0	3	0	0
T15	386302	0	0	0
T18	0	11	0	0
T20	0	1	0	0
T21	76769	0	0	0
T43	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	26	0	0
T6	251474	0	0	0
T7	292056	0	0	0
T14	289732	0	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T19	297161	0	0	0
T21	76769	1	0	0
T37	0	1	0	0
T41	5387	0	0	0
T42	3838	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T62	10647	0	0	0
T79	0	1	0	0
T86	0	1	0	0
T89	0	1	0	0
T104	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	192	0	0
T4	157393	1	0	0
T5	131013	0	0	0
T6	0	1	0	0
T7	292056	1	0	0
T14	289732	2	0	0
T15	386302	0	0	0
T18	272500	10	0	0
T19	297161	0	0	0
T21	76769	0	0	0
T24	0	1	0	0
T25	0	1	0	0
T41	5387	0	0	0
T42	3838	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T67	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560975925	237975764	0	0
T1	63945	63853	0	0
T2	156825	1908	0	0
T3	28263	28196	0	0
T4	157393	183297	0	0
T5	131013	77879	0	0
T7	292056	2336	0	0
T11	285700	13716	0	0
T12	127422	127337	0	0
T13	52572	48704	0	0
T21	76769	11457	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	498	0	0
T2	156825	1	0	0
T3	28263	0	0	0
T4	157393	4	0	0
T5	131013	5	0	0
T6	0	4	0	0
T7	292056	2	0	0
T11	285700	1	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T14	0	3	0	0
T15	386302	0	0	0
T18	0	11	0	0
T21	76769	1	0	0
T43	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	485	0	0
T2	156825	1	0	0
T3	28263	0	0	0
T4	157393	4	0	0
T5	131013	5	0	0
T6	0	4	0	0
T7	292056	2	0	0
T11	285700	1	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T14	0	3	0	0
T15	386302	0	0	0
T18	0	11	0	0
T21	76769	1	0	0
T43	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	478	0	0
T2	156825	1	0	0
T3	28263	0	0	0
T4	157393	4	0	0
T5	131013	5	0	0
T6	0	4	0	0
T7	292056	2	0	0
T11	285700	1	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T14	0	3	0	0
T15	386302	0	0	0
T18	0	11	0	0
T21	76769	1	0	0
T43	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	474	0	0
T2	156825	1	0	0
T3	28263	0	0	0
T4	157393	4	0	0
T5	131013	5	0	0
T6	0	3	0	0
T7	292056	2	0	0
T11	285700	1	0	0
T12	127422	0	0	0
T13	52572	0	0	0
T14	0	3	0	0
T15	386302	0	0	0
T18	0	11	0	0
T21	76769	1	0	0
T43	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	455	0	0
T4	157393	0	0	0
T5	131013	35	0	0
T6	0	5	0	0
T7	292056	0	0	0
T13	52572	1	0	0
T14	289732	0	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T19	297161	0	0	0
T21	76769	1	0	0
T41	5387	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T47	0	1	0	0
T66	0	1	0	0
T70	0	1	0	0
T74	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	57675	0	0
T4	157393	0	0	0
T5	131013	3429	0	0
T6	0	662	0	0
T7	292056	0	0	0
T13	52572	736	0	0
T14	289732	0	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T19	297161	0	0	0
T21	76769	0	0	0
T41	5387	0	0	0
T43	0	77	0	0
T44	0	62	0	0
T47	0	1	0	0
T49	0	1325	0	0
T66	0	152	0	0
T70	0	43	0	0
T74	0	136	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	380	0	0
T4	157393	0	0	0
T5	131013	35	0	0
T6	0	2	0	0
T7	292056	0	0	0
T13	52572	1	0	0
T14	289732	0	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T19	297161	0	0	0
T21	76769	0	0	0
T23	0	12	0	0
T41	5387	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T49	0	5	0	0
T66	0	1	0	0
T70	0	1	0	0
T74	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	46	0	0
T6	251474	3	0	0
T16	825654	0	0	0
T17	101643	0	0	0
T20	263327	0	0	0
T24	191046	0	0	0
T43	29887	0	0	0
T44	126913	0	0	0
T49	0	1	0	0
T63	119416	0	0	0
T64	279686	0	0	0
T79	0	1	0	0
T85	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	129200	0	0	0
T97	0	1	0	0
T111	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	1077	0	0
T8	191841	309	0	0
T9	0	169	0	0
T10	0	150	0	0
T30	503540	0	0	0
T31	0	298	0	0
T32	0	151	0	0
T33	44584	0	0	0
T34	472363	0	0	0
T35	22673	0	0	0
T36	10295	0	0	0
T37	167978	0	0	0
T38	114392	0	0	0
T39	278838	0	0	0
T40	17009	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	867	0	0
T8	191841	249	0	0
T9	0	139	0	0
T10	0	120	0	0
T30	503540	0	0	0
T31	0	238	0	0
T32	0	121	0	0
T33	44584	0	0	0
T34	472363	0	0	0
T35	22673	0	0	0
T36	10295	0	0	0
T37	167978	0	0	0
T38	114392	0	0	0
T39	278838	0	0	0
T40	17009	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560970317	560904326	0	0
T1	63945	63854	0	0
T2	156825	156818	0	0
T3	28263	28197	0	0
T4	157393	157350	0	0
T5	131013	130937	0	0
T7	292056	292046	0	0
T11	285700	285601	0	0
T12	127422	127338	0	0
T13	52572	52492	0	0
T21	76769	76674	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	561104358	0	0
T1	63945	63854	0	0
T2	156825	156818	0	0
T3	28263	28197	0	0
T4	157393	157350	0	0
T5	131013	130937	0	0
T7	292056	292046	0	0
T11	285700	285601	0	0
T12	127422	127338	0	0
T13	52572	52492	0	0
T21	76769	76674	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T12,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T11,T12,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T4,T5
1	0	1	Covered	T1,T11,T12
1	1	0	Covered	T3,T13,T4
1	1	1	Covered	T12,T5,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T5,T21
0	1	Covered	T21,T75,T49
1	0	Covered	T44,T72,T51

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T5,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T44,T72,T51

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T5,T21
1	0	Not Covered
1	1	Covered	T21,T75,T49

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T21
1	Covered	T11,T12,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T11,T12,T4
1	Covered	T5,T18,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T12,T4
1	Covered	T4,T43,T63

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T12,T4
1	Covered	T5,T21,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T12,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T12,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T12,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T5,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T11,T12,T4
Phase1St	198	Covered	T11,T12,T4
Phase2St	215	Covered	T11,T12,T4
Phase3St	233	Covered	T11,T12,T4
TerminalSt	249	Covered	T11,T12,T4
TimeoutSt	159	Covered	T12,T5,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T11,T12,T4
IdleSt->TimeoutSt	159	Covered	T12,T5,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T24,T29,T77
Phase0St->Phase1St	198	Covered	T11,T12,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T46,T23,T112
Phase1St->Phase2St	215	Covered	T11,T12,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T113,T58,T114
Phase2St->Phase3St	233	Covered	T11,T12,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T27,T30,T115
Phase3St->TerminalSt	249	Covered	T11,T12,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T5,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T12,T5,T18
TimeoutSt->Phase0St	172	Covered	T21,T44,T75

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T5,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T44,T75
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T5,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T12,T5,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T29,T77
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T11,T12,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T11,T12,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T46,T112,T116
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T11,T12,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T11,T12,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T114,T117,T102
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T11,T12,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T11,T12,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T30,T115
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T11,T12,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T11,T12,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T21,T14,T43
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T11,T12,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	561260441	168	0	0
CheckAccumTrig0_A	561260441	428	0	0
CheckAccumTrig1_A	561260441	13	0	0
CheckClr_A	561260441	168	0	0
CheckEn_A	560975925	240395777	0	0
CheckPhase0_A	561260441	485	0	0
CheckPhase1_A	561260441	479	0	0
CheckPhase2_A	561260441	474	0	0
CheckPhase3_A	561260441	468	0	0
CheckTimeout0_A	561260441	941	0	0
CheckTimeoutSt1_A	561260441	119428	0	0
CheckTimeoutSt2_A	561260441	862	0	0
CheckTimeoutStTrig_A	561260441	59	0	0
ErrorStAllEscAsserted_A	561260441	1129	0	0
ErrorStIsTerminal_A	561260441	919	0	0
EscStateOut_A	560970317	560904326	0	0
u_state_regs_A	561260441	561104358	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	168	0	0
T8	191841	48	0	0
T9	0	42	0	0
T10	0	13	0	0
T30	503540	0	0	0
T31	0	40	0	0
T32	0	25	0	0
T33	44584	0	0	0
T34	472363	0	0	0
T35	22673	0	0	0
T36	10295	0	0	0
T37	167978	0	0	0
T38	114392	0	0	0
T39	278838	0	0	0
T40	17009	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	428	0	0
T4	157393	3	0	0
T5	131013	4	0	0
T6	0	1	0	0
T7	292056	0	0	0
T11	285700	1	0	0
T12	127422	1	0	0
T13	52572	0	0	0
T14	0	1	0	0
T15	386302	0	0	0
T18	272500	1	0	0
T19	0	1	0	0
T21	76769	0	0	0
T41	5387	1	0	0
T43	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	13	0	0
T25	18798	0	0	0
T30	0	1	0	0
T44	126913	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T63	119416	0	0	0
T64	279686	0	0	0
T65	98384	0	0	0
T66	331184	0	0	0
T67	955525	0	0	0
T68	15642	0	0	0
T69	353524	0	0	0
T70	34868	0	0	0
T72	0	1	0	0
T101	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	168	0	0
T6	251474	0	0	0
T7	292056	0	0	0
T14	289732	1	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T19	297161	0	0	0
T20	0	1	0	0
T21	76769	1	0	0
T24	0	1	0	0
T29	0	2	0	0
T41	5387	0	0	0
T42	3838	0	0	0
T43	0	1	0	0
T44	0	4	0	0
T62	10647	0	0	0
T69	0	2	0	0
T75	0	1	0	0
T122	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560975925	240395777	0	0
T1	63945	2141	0	0
T2	156825	156392	0	0
T3	28263	28196	0	0
T4	157393	100343	0	0
T5	131013	135864	0	0
T7	292056	292046	0	0
T11	285700	8562	0	0
T12	127422	3105	0	0
T13	52572	52491	0	0
T21	76769	64897	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	485	0	0
T4	157393	3	0	0
T5	131013	4	0	0
T6	0	1	0	0
T7	292056	0	0	0
T11	285700	1	0	0
T12	127422	1	0	0
T13	52572	0	0	0
T14	0	1	0	0
T15	386302	0	0	0
T18	272500	1	0	0
T19	0	1	0	0
T21	76769	1	0	0
T41	5387	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	479	0	0
T4	157393	3	0	0
T5	131013	4	0	0
T6	0	1	0	0
T7	292056	0	0	0
T11	285700	1	0	0
T12	127422	1	0	0
T13	52572	0	0	0
T14	0	1	0	0
T15	386302	0	0	0
T18	272500	1	0	0
T19	0	1	0	0
T21	76769	1	0	0
T41	5387	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	474	0	0
T4	157393	3	0	0
T5	131013	4	0	0
T6	0	1	0	0
T7	292056	0	0	0
T11	285700	1	0	0
T12	127422	1	0	0
T13	52572	0	0	0
T14	0	1	0	0
T15	386302	0	0	0
T18	272500	1	0	0
T19	0	1	0	0
T21	76769	1	0	0
T41	5387	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	468	0	0
T4	157393	3	0	0
T5	131013	4	0	0
T6	0	1	0	0
T7	292056	0	0	0
T11	285700	1	0	0
T12	127422	1	0	0
T13	52572	0	0	0
T14	0	1	0	0
T15	386302	0	0	0
T18	272500	1	0	0
T19	0	1	0	0
T21	76769	1	0	0
T41	5387	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	941	0	0
T4	157393	0	0	0
T5	131013	20	0	0
T7	292056	0	0	0
T12	127422	1	0	0
T13	52572	0	0	0
T14	289732	0	0	0
T15	386302	0	0	0
T18	272500	1	0	0
T21	76769	1	0	0
T41	5387	0	0	0
T44	0	2	0	0
T69	0	28	0	0
T70	0	2	0	0
T75	0	2	0	0
T76	0	2	0	0
T123	0	10	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	119428	0	0
T4	157393	0	0	0
T5	131013	2423	0	0
T7	292056	0	0	0
T12	127422	178	0	0
T13	52572	0	0	0
T14	289732	0	0	0
T15	386302	0	0	0
T18	272500	102	0	0
T21	76769	413	0	0
T41	5387	0	0	0
T44	0	65	0	0
T69	0	3904	0	0
T70	0	91	0	0
T75	0	251	0	0
T76	0	109	0	0
T123	0	1719	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	862	0	0
T4	157393	0	0	0
T5	131013	20	0	0
T7	292056	0	0	0
T12	127422	1	0	0
T13	52572	0	0	0
T14	289732	0	0	0
T15	386302	0	0	0
T18	272500	1	0	0
T21	76769	0	0	0
T41	5387	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T69	0	28	0	0
T70	0	2	0	0
T75	0	1	0	0
T76	0	2	0	0
T123	0	10	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	59	0	0
T6	251474	0	0	0
T7	292056	0	0	0
T14	289732	0	0	0
T15	386302	0	0	0
T18	272500	0	0	0
T19	297161	0	0	0
T21	76769	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	5387	0	0	0
T42	3838	0	0	0
T49	0	1	0	0
T62	10647	0	0	0
T75	0	1	0	0
T77	0	3	0	0
T81	0	2	0	0
T84	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	1129	0	0
T8	191841	301	0	0
T9	0	168	0	0
T10	0	167	0	0
T30	503540	0	0	0
T31	0	327	0	0
T32	0	166	0	0
T33	44584	0	0	0
T34	472363	0	0	0
T35	22673	0	0	0
T36	10295	0	0	0
T37	167978	0	0	0
T38	114392	0	0	0
T39	278838	0	0	0
T40	17009	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	919	0	0
T8	191841	241	0	0
T9	0	138	0	0
T10	0	137	0	0
T30	503540	0	0	0
T31	0	267	0	0
T32	0	136	0	0
T33	44584	0	0	0
T34	472363	0	0	0
T35	22673	0	0	0
T36	10295	0	0	0
T37	167978	0	0	0
T38	114392	0	0	0
T39	278838	0	0	0
T40	17009	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	560970317	560904326	0	0
T1	63945	63854	0	0
T2	156825	156818	0	0
T3	28263	28197	0	0
T4	157393	157350	0	0
T5	131013	130937	0	0
T7	292056	292046	0	0
T11	285700	285601	0	0
T12	127422	127338	0	0
T13	52572	52492	0	0
T21	76769	76674	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561260441	561104358	0	0
T1	63945	63854	0	0
T2	156825	156818	0	0
T3	28263	28197	0	0
T4	157393	157350	0	0
T5	131013	130937	0	0
T7	292056	292046	0	0
T11	285700	285601	0	0
T12	127422	127338	0	0
T13	52572	52492	0	0
T21	76769	76674	0	0