Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T48,T183,T43
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13292	0	0
DisabledNoTrigBkwd_A	2147483647	727498	0	0
DisabledNoTrigFwd_A	2147483647	1249795815	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13292	0	0
T9	41412	0	0	0
T35	204689	0	0	0
T43	0	1008	0	0
T45	4841	1792	0	0
T46	76819	0	0	0
T47	444156	0	0	0
T48	1181	220	0	0
T53	29674	0	0	0
T183	0	530	0	0
T184	0	838	0	0
T185	0	444	0	0
T186	2098	1208	0	0
T187	0	537	0	0
T188	0	605	0	0
T189	0	780	0	0
T190	0	554	0	0
T191	0	848	0	0
T192	0	623	0	0
T193	0	439	0	0
T194	0	638	0	0
T195	0	402	0	0
T196	0	494	0	0
T197	0	217	0	0
T198	0	503	0	0
T199	0	612	0	0
T200	522972	0	0	0
T201	13841	0	0	0
T202	329079	0	0	0
T203	120238	0	0	0
T204	56814	0	0	0
T205	66789	0	0	0
T206	945846	0	0	0
T207	278527	0	0	0
T208	119510	0	0	0
T209	16397	0	0	0
T210	83552	0	0	0
T211	88362	0	0	0
T212	655764	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	727498	0	0
T1	1259332	5770	0	0
T2	202928	68	0	0
T3	23652	1	0	0
T4	1365492	452	0	0
T5	0	6154	0	0
T6	3691836	0	0	0
T7	1757960	1615	0	0
T11	137916	1	0	0
T12	721156	39	0	0
T13	0	2832	0	0
T14	0	523	0	0
T18	0	1	0	0
T19	0	2	0	0
T20	47272	142	0	0
T21	154636	38	0	0
T22	0	180	0	0
T23	0	115	0	0
T48	0	4	0	0
T49	0	6	0	0
T50	0	56	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1249795815	0	0
T1	1259332	2121639	0	0
T2	202928	108674	0	0
T3	23652	10452	0	0
T4	1365492	792404	0	0
T6	3691836	3497955	0	0
T7	1757960	1341476	0	0
T11	137916	135766	0	0
T12	721156	203767	0	0
T20	47272	38412	0	0
T21	154636	111554	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T45,T184,T185
1	1	Covered	T1,T4,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T11

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	606803802	4382	0	0
DisabledNoTrigBkwd_A	606803802	183791	0	0
DisabledNoTrigFwd_A	606803802	313237397	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	4382	0	0
T9	41412	0	0	0
T35	204689	0	0	0
T45	4841	1792	0	0
T46	76819	0	0	0
T47	444156	0	0	0
T53	29674	0	0	0
T184	0	838	0	0
T185	0	444	0	0
T187	0	537	0	0
T190	0	554	0	0
T197	0	217	0	0
T200	522972	0	0	0
T201	13841	0	0	0
T202	329079	0	0	0
T203	120238	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	183791	0	0
T1	314833	3043	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	103	0	0
T5	0	3666	0	0
T6	922959	0	0	0
T7	439490	1	0	0
T11	34479	1	0	0
T12	180289	0	0	0
T13	0	1767	0	0
T18	0	1	0	0
T20	11818	0	0	0
T21	38659	38	0	0
T22	0	14	0	0
T49	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	313237397	0	0
T1	314833	48409	0	0
T2	50732	50666	0	0
T3	5913	5824	0	0
T4	341373	198828	0	0
T6	922959	922888	0	0
T7	439490	437531	0	0
T11	34479	32626	0	0
T12	180289	17523	0	0
T20	11818	11750	0	0
T21	38659	2546	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T186,T191,T193
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	606803802	2495	0	0
DisabledNoTrigBkwd_A	606803802	164085	0	0
DisabledNoTrigFwd_A	606803802	332251942	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	2495	0	0
T186	2098	1208	0	0
T191	0	848	0	0
T193	0	439	0	0
T204	56814	0	0	0
T205	66789	0	0	0
T206	945846	0	0	0
T207	278527	0	0	0
T208	119510	0	0	0
T209	16397	0	0	0
T210	83552	0	0	0
T211	88362	0	0	0
T212	655764	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	164085	0	0
T1	314833	1593	0	0
T2	50732	5	0	0
T3	5913	0	0	0
T4	341373	92	0	0
T5	0	541	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T13	0	2	0	0
T14	0	519	0	0
T19	0	1	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T22	0	149	0	0
T23	0	43	0	0
T49	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	332251942	0	0
T1	314833	907147	0	0
T2	50732	4176	0	0
T3	5913	3198	0	0
T4	341373	200437	0	0
T6	922959	922888	0	0
T7	439490	439483	0	0
T11	34479	34380	0	0
T12	180289	24117	0	0
T20	11818	11750	0	0
T21	38659	38593	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T48,T183,T188
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	606803802	2874	0	0
DisabledNoTrigBkwd_A	606803802	193522	0	0
DisabledNoTrigFwd_A	606803802	303319353	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	2874	0	0
T5	918017	0	0	0
T14	354044	0	0	0
T15	460049	0	0	0
T17	157580	0	0	0
T22	43784	0	0	0
T23	84977	0	0	0
T48	1181	220	0	0
T49	7735	0	0	0
T68	35250	0	0	0
T69	38079	0	0	0
T183	0	530	0	0
T188	0	605	0	0
T192	0	623	0	0
T195	0	402	0	0
T196	0	494	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	193522	0	0
T1	314833	75	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	136	0	0
T5	0	1439	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	39	0	0
T13	0	1	0	0
T14	0	4	0	0
T20	11818	142	0	0
T21	38659	0	0	0
T22	0	17	0	0
T23	0	24	0	0
T48	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	303319353	0	0
T1	314833	298833	0	0
T2	50732	50666	0	0
T3	5913	713	0	0
T4	341373	218701	0	0
T6	922959	778082	0	0
T7	439490	439483	0	0
T11	34479	34380	0	0
T12	180289	18157	0	0
T20	11818	3162	0	0
T21	38659	38593	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T43,T189,T194
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	606803802	3541	0	0
DisabledNoTrigBkwd_A	606803802	186100	0	0
DisabledNoTrigFwd_A	606803802	300987123	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	3541	0	0
T9	41412	0	0	0
T35	204689	0	0	0
T43	3520	1008	0	0
T44	34248	0	0	0
T45	4841	0	0	0
T46	76819	0	0	0
T47	444156	0	0	0
T53	29674	0	0	0
T189	0	780	0	0
T194	0	638	0	0
T198	0	503	0	0
T199	0	612	0	0
T200	522972	0	0	0
T201	13841	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	186100	0	0
T1	314833	1059	0	0
T2	50732	63	0	0
T3	5913	1	0	0
T4	341373	121	0	0
T5	0	508	0	0
T6	922959	0	0	0
T7	439490	1614	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T13	0	1062	0	0
T19	0	1	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T23	0	48	0	0
T50	0	56	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	300987123	0	0
T1	314833	867250	0	0
T2	50732	3166	0	0
T3	5913	717	0	0
T4	341373	174438	0	0
T6	922959	874097	0	0
T7	439490	24979	0	0
T11	34479	34380	0	0
T12	180289	143970	0	0
T20	11818	11750	0	0
T21	38659	31822	0	0