Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T20
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T4,T20
1	1	1	Covered	T1,T4,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T20
0	1	Covered	T1,T22,T23
1	0	Covered	T1,T20,T13

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T20
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T20,T13

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T20
1	0	Covered	T24,T25,T26
1	1	Covered	T1,T22,T23

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T13

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T11,T13

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T4,T20

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T4,T20
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T27,T28,T29
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T23,T30,T31
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T27,T28,T32
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T21,T27,T28
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T4,T20
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T4,T20
TimeoutSt->Phase0St	172	Covered	T1,T20,T13

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T13
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T34,T35
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T23,T36,T37
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T28,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T27,T38
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	947	0	0
CheckAccumTrig0_A	2147483647	2340	0	0
CheckAccumTrig1_A	2147483647	117	0	0
CheckClr_A	2147483647	1034	0	0
CheckEn_A	2147483647	920665202	0	0
CheckPhase0_A	2147483647	2595	0	0
CheckPhase1_A	2147483647	2541	0	0
CheckPhase2_A	2147483647	2486	0	0
CheckPhase3_A	2147483647	2447	0	0
CheckTimeout0_A	2147483647	2559	0	0
CheckTimeoutSt1_A	2147483647	304157	0	0
CheckTimeoutSt2_A	2147483647	2216	0	0
CheckTimeoutStTrig_A	2147483647	208	0	0
ErrorStAllEscAsserted_A	2147483647	5100	0	0
ErrorStIsTerminal_A	2147483647	4140	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	947	0	0
T8	122900	223	0	0
T9	0	241	0	0
T10	0	250	0	0
T33	2079088	0	0	0
T34	1809716	0	0	0
T39	0	127	0	0
T40	0	106	0	0
T41	238608	0	0	0
T42	267260	0	0	0
T43	14080	0	0	0
T44	136992	0	0	0
T45	19364	0	0	0
T46	307276	0	0	0
T47	1776624	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2340	0	0
T1	1259332	15	0	0
T2	202928	2	0	0
T3	23652	1	0	0
T4	1365492	24	0	0
T5	0	17	0	0
T6	3691836	0	0	0
T7	1757960	2	0	0
T11	137916	1	0	0
T12	721156	1	0	0
T13	0	5	0	0
T14	0	2	0	0
T15	0	1	0	0
T18	0	1	0	0
T19	0	4	0	0
T20	47272	0	0	0
T21	154636	3	0	0
T22	0	4	0	0
T23	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	117	0	0
T1	629666	3	0	0
T2	101464	0	0	0
T3	11826	0	0	0
T4	682746	0	0	0
T5	918017	0	0	0
T6	2768877	0	0	0
T7	1318470	0	0	0
T11	103437	0	0	0
T12	360578	0	0	0
T13	336923	1	0	0
T14	354044	0	0	0
T15	460049	0	0	0
T17	157580	0	0	0
T20	35454	1	0	0
T21	115977	0	0	0
T22	43784	0	0	0
T23	84977	0	0	0
T28	0	1	0	0
T33	0	2	0	0
T48	1181	0	0	0
T49	7735	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	7	0	0
T57	0	1	0	0
T58	0	4	0	0
T59	0	3	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	35250	0	0	0
T69	38079	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1034	0	0
T1	1259332	8	0	0
T2	202928	0	0	0
T3	23652	0	0	0
T4	1365492	12	0	0
T5	0	6	0	0
T6	3691836	0	0	0
T7	1757960	0	0	0
T11	137916	0	0	0
T12	721156	0	0	0
T13	0	2	0	0
T16	0	1	0	0
T19	0	3	0	0
T20	47272	1	0	0
T21	154636	2	0	0
T22	0	2	0	0
T23	0	1	0	0
T27	0	7	0	0
T28	0	7	0	0
T29	0	2	0	0
T30	0	3	0	0
T49	0	1	0	0
T51	0	1	0	0
T70	0	5	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	920665202	0	0
T1	1259332	2099092	0	0
T2	202928	108672	0	0
T3	23652	10451	0	0
T4	1365492	667210	0	0
T6	3691836	3497951	0	0
T7	1757960	917440	0	0
T11	137916	104464	0	0
T12	721156	203766	0	0
T20	47272	38409	0	0
T21	154636	111551	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2595	0	0
T1	1259332	21	0	0
T2	202928	2	0	0
T3	23652	1	0	0
T4	1365492	24	0	0
T5	0	18	0	0
T6	3691836	0	0	0
T7	1757960	2	0	0
T11	137916	1	0	0
T12	721156	1	0	0
T13	0	6	0	0
T14	0	2	0	0
T18	0	1	0	0
T19	0	2	0	0
T20	47272	1	0	0
T21	154636	3	0	0
T22	0	5	0	0
T23	0	4	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2541	0	0
T1	1259332	21	0	0
T2	202928	2	0	0
T3	23652	1	0	0
T4	1365492	24	0	0
T5	0	18	0	0
T6	3691836	0	0	0
T7	1757960	2	0	0
T11	137916	1	0	0
T12	721156	1	0	0
T13	0	6	0	0
T14	0	2	0	0
T18	0	1	0	0
T19	0	2	0	0
T20	47272	1	0	0
T21	154636	3	0	0
T22	0	5	0	0
T23	0	3	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2486	0	0
T1	1259332	21	0	0
T2	202928	2	0	0
T3	23652	1	0	0
T4	1365492	24	0	0
T5	0	18	0	0
T6	3691836	0	0	0
T7	1757960	2	0	0
T11	137916	1	0	0
T12	721156	1	0	0
T13	0	6	0	0
T14	0	2	0	0
T18	0	1	0	0
T19	0	2	0	0
T20	47272	1	0	0
T21	154636	3	0	0
T22	0	5	0	0
T23	0	3	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2447	0	0
T1	1259332	21	0	0
T2	202928	2	0	0
T3	23652	1	0	0
T4	1365492	24	0	0
T5	0	18	0	0
T6	3691836	0	0	0
T7	1757960	2	0	0
T11	137916	1	0	0
T12	721156	1	0	0
T13	0	6	0	0
T14	0	2	0	0
T18	0	1	0	0
T19	0	2	0	0
T20	47272	1	0	0
T21	154636	2	0	0
T22	0	5	0	0
T23	0	3	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2559	0	0
T1	1259332	12	0	0
T2	202928	0	0	0
T3	23652	0	0	0
T4	1365492	21	0	0
T5	0	4	0	0
T6	3691836	0	0	0
T7	1757960	0	0	0
T11	137916	0	0	0
T12	721156	0	0	0
T13	0	2	0	0
T20	47272	2	0	0
T21	154636	0	0	0
T22	0	3	0	0
T23	0	5	0	0
T27	0	9	0	0
T28	0	16	0	0
T29	0	1	0	0
T30	0	1	0	0
T68	0	12	0	0
T69	0	11	0	0
T71	0	1	0	0
T73	0	1	0	0
T75	0	11	0	0
T76	0	1	0	0
T77	0	5	0	0
T78	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	304157	0	0
T1	1259332	1931	0	0
T2	202928	0	0	0
T3	23652	0	0	0
T4	1365492	1926	0	0
T5	0	121	0	0
T6	3691836	0	0	0
T7	1757960	0	0	0
T11	137916	0	0	0
T12	721156	0	0	0
T13	0	130	0	0
T20	47272	44	0	0
T21	154636	0	0	0
T22	0	996	0	0
T23	0	291	0	0
T27	0	1511	0	0
T28	0	962	0	0
T29	0	69	0	0
T30	0	80	0	0
T31	0	190	0	0
T68	0	1869	0	0
T69	0	489	0	0
T71	0	197	0	0
T73	0	108	0	0
T75	0	1821	0	0
T76	0	440	0	0
T77	0	554	0	0
T78	0	197	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2216	0	0
T1	944499	6	0	0
T2	152196	0	0	0
T3	17739	0	0	0
T4	1365492	21	0	0
T5	0	3	0	0
T6	3691836	0	0	0
T7	1757960	0	0	0
T11	137916	0	0	0
T12	721156	0	0	0
T13	336923	1	0	0
T20	47272	1	0	0
T21	154636	0	0	0
T22	0	2	0	0
T23	0	2	0	0
T27	0	4	0	0
T28	0	20	0	0
T29	0	1	0	0
T30	0	3	0	0
T31	0	20	0	0
T34	0	5	0	0
T48	1181	0	0	0
T49	7735	0	0	0
T68	0	12	0	0
T69	0	10	0	0
T71	0	1	0	0
T74	0	1	0	0
T75	0	11	0	0
T76	0	1	0	0
T77	0	3	0	0
T79	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	208	0	0
T1	314833	2	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	0	0	0
T5	918017	0	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T14	354044	0	0	0
T15	920098	0	0	0
T17	315160	0	0	0
T18	826892	0	0	0
T19	262630	0	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T22	43784	1	0	0
T23	169954	2	0	0
T28	0	2	0	0
T30	0	2	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T54	0	1	0	0
T59	0	2	0	0
T68	70500	0	0	0
T69	76158	1	0	0
T73	0	1	0	0
T75	179026	0	0	0
T80	0	2	0	0
T81	0	2	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5100	0	0
T8	122900	1235	0	0
T9	0	1310	0	0
T10	0	1256	0	0
T33	2079088	0	0	0
T34	1809716	0	0	0
T39	0	678	0	0
T40	0	621	0	0
T41	238608	0	0	0
T42	267260	0	0	0
T43	14080	0	0	0
T44	136992	0	0	0
T45	19364	0	0	0
T46	307276	0	0	0
T47	1776624	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4140	0	0
T8	122900	995	0	0
T9	0	1070	0	0
T10	0	1016	0	0
T33	2079088	0	0	0
T34	1809716	0	0	0
T39	0	558	0	0
T40	0	501	0	0
T41	238608	0	0	0
T42	267260	0	0	0
T43	14080	0	0	0
T44	136992	0	0	0
T45	19364	0	0	0
T46	307276	0	0	0
T47	1776624	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1259332	1259104	0	0
T2	202928	202664	0	0
T3	23652	23296	0	0
T4	1365492	1365032	0	0
T6	3691836	3691552	0	0
T7	1757960	1757932	0	0
T11	137916	137520	0	0
T12	721156	720780	0	0
T20	47272	47000	0	0
T21	154636	154372	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1259332	1259104	0	0
T2	202928	202664	0	0
T3	23652	23296	0	0
T4	1365492	1365032	0	0
T6	3691836	3691552	0	0
T7	1757960	1757932	0	0
T11	137916	137520	0	0
T12	721156	720780	0	0
T20	47272	47000	0	0
T21	154636	154372	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T11

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T11
1	0	1	Covered	T1,T4,T12
1	1	0	Covered	T1,T4,T20
1	1	1	Covered	T1,T4,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T13
0	1	Covered	T1,T28,T36
1	0	Covered	T1,T13,T52

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T13,T52

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T13
1	0	Not Covered
1	1	Covered	T1,T28,T36

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T11
1	Covered	T1,T4,T7

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T11
1	Covered	T1,T4,T50

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T11
1	Covered	T1,T4,T21

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T11,T13

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T11
Phase1St	198	Covered	T1,T4,T11
Phase2St	215	Covered	T1,T4,T11
Phase3St	233	Covered	T1,T4,T11
TerminalSt	249	Covered	T1,T4,T11
TimeoutSt	159	Covered	T1,T4,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T4,T11
IdleSt->TimeoutSt	159	Covered	T1,T4,T13
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T34,T35,T61
Phase0St->Phase1St	198	Covered	T1,T4,T11
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T30,T31,T36
Phase1St->Phase2St	215	Covered	T1,T4,T11
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T27,T28,T32
Phase2St->Phase3St	233	Covered	T1,T4,T11
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T21,T34,T88
Phase3St->TerminalSt	249	Covered	T1,T4,T11
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T13,T22
TimeoutSt->Phase0St	172	Covered	T1,T13,T28

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T11
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T13,T28
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T13,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T34,T35,T89
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T36,T37,T60
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T28,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T34,T88
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	606803802	225	0	0
CheckAccumTrig0_A	606803802	835	0	0
CheckAccumTrig1_A	606803802	42	0	0
CheckClr_A	606803802	396	0	0
CheckEn_A	606666094	222554898	0	0
CheckPhase0_A	606803802	906	0	0
CheckPhase1_A	606803802	884	0	0
CheckPhase2_A	606803802	869	0	0
CheckPhase3_A	606803802	854	0	0
CheckTimeout0_A	606803802	660	0	0
CheckTimeoutSt1_A	606803802	79526	0	0
CheckTimeoutSt2_A	606803802	563	0	0
CheckTimeoutStTrig_A	606803802	51	0	0
ErrorStAllEscAsserted_A	606803802	1285	0	0
ErrorStIsTerminal_A	606803802	1045	0	0
EscStateOut_A	606665254	606594861	0	0
u_state_regs_A	606803802	606631418	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	225	0	0
T8	30725	60	0	0
T9	0	66	0	0
T10	0	60	0	0
T33	519772	0	0	0
T34	452429	0	0	0
T39	0	10	0	0
T40	0	29	0	0
T41	59652	0	0	0
T42	66815	0	0	0
T43	3520	0	0	0
T44	34248	0	0	0
T45	4841	0	0	0
T46	76819	0	0	0
T47	444156	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	835	0	0
T1	314833	2	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	5	0	0
T5	0	6	0	0
T6	922959	0	0	0
T7	439490	1	0	0
T11	34479	1	0	0
T12	180289	0	0	0
T13	0	2	0	0
T18	0	1	0	0
T20	11818	0	0	0
T21	38659	3	0	0
T22	0	2	0	0
T49	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	42	0	0
T1	314833	1	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	0	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T13	0	1	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T52	0	1	0	0
T54	0	2	0	0
T56	0	3	0	0
T57	0	1	0	0
T58	0	1	0	0
T60	0	2	0	0
T62	0	1	0	0
T63	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	396	0	0
T1	314833	1	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	2	0	0
T5	0	2	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T13	0	2	0	0
T20	11818	0	0	0
T21	38659	2	0	0
T22	0	1	0	0
T27	0	2	0	0
T28	0	4	0	0
T49	0	1	0	0
T70	0	5	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606666094	222554898	0	0
T1	314833	44093	0	0
T2	50732	50665	0	0
T3	5913	5823	0	0
T4	341373	143382	0	0
T6	922959	922887	0	0
T7	439490	18643	0	0
T11	34479	1327	0	0
T12	180289	17523	0	0
T20	11818	11749	0	0
T21	38659	2546	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	906	0	0
T1	314833	5	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	5	0	0
T5	0	6	0	0
T6	922959	0	0	0
T7	439490	1	0	0
T11	34479	1	0	0
T12	180289	0	0	0
T13	0	3	0	0
T18	0	1	0	0
T20	11818	0	0	0
T21	38659	3	0	0
T22	0	2	0	0
T49	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	884	0	0
T1	314833	5	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	5	0	0
T5	0	6	0	0
T6	922959	0	0	0
T7	439490	1	0	0
T11	34479	1	0	0
T12	180289	0	0	0
T13	0	3	0	0
T18	0	1	0	0
T20	11818	0	0	0
T21	38659	3	0	0
T22	0	2	0	0
T49	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	869	0	0
T1	314833	5	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	5	0	0
T5	0	6	0	0
T6	922959	0	0	0
T7	439490	1	0	0
T11	34479	1	0	0
T12	180289	0	0	0
T13	0	3	0	0
T18	0	1	0	0
T20	11818	0	0	0
T21	38659	3	0	0
T22	0	2	0	0
T49	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	854	0	0
T1	314833	5	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	5	0	0
T5	0	6	0	0
T6	922959	0	0	0
T7	439490	1	0	0
T11	34479	1	0	0
T12	180289	0	0	0
T13	0	3	0	0
T18	0	1	0	0
T20	11818	0	0	0
T21	38659	2	0	0
T22	0	2	0	0
T49	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	660	0	0
T1	314833	3	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	17	0	0
T5	0	1	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T13	0	2	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T22	0	1	0	0
T27	0	2	0	0
T28	0	8	0	0
T68	0	1	0	0
T69	0	10	0	0
T71	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	79526	0	0
T1	314833	1018	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	1482	0	0
T5	0	34	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T13	0	130	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T22	0	71	0	0
T27	0	150	0	0
T28	0	531	0	0
T68	0	174	0	0
T69	0	473	0	0
T71	0	197	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	563	0	0
T4	341373	17	0	0
T5	0	1	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T13	336923	1	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T22	0	1	0	0
T28	0	6	0	0
T31	0	15	0	0
T48	1181	0	0	0
T49	7735	0	0	0
T68	0	1	0	0
T69	0	10	0	0
T71	0	1	0	0
T77	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	51	0	0
T1	314833	2	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	0	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T28	0	2	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T54	0	1	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	0	1	0	0
T84	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	1285	0	0
T8	30725	309	0	0
T9	0	313	0	0
T10	0	324	0	0
T33	519772	0	0	0
T34	452429	0	0	0
T39	0	184	0	0
T40	0	155	0	0
T41	59652	0	0	0
T42	66815	0	0	0
T43	3520	0	0	0
T44	34248	0	0	0
T45	4841	0	0	0
T46	76819	0	0	0
T47	444156	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	1045	0	0
T8	30725	249	0	0
T9	0	253	0	0
T10	0	264	0	0
T33	519772	0	0	0
T34	452429	0	0	0
T39	0	154	0	0
T40	0	125	0	0
T41	59652	0	0	0
T42	66815	0	0	0
T43	3520	0	0	0
T44	34248	0	0	0
T45	4841	0	0	0
T46	76819	0	0	0
T47	444156	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606665254	606594861	0	0
T1	314833	314776	0	0
T2	50732	50666	0	0
T3	5913	5824	0	0
T4	341373	341258	0	0
T6	922959	922888	0	0
T7	439490	439483	0	0
T11	34479	34380	0	0
T12	180289	180195	0	0
T20	11818	11750	0	0
T21	38659	38593	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	606631418	0	0
T1	314833	314776	0	0
T2	50732	50666	0	0
T3	5913	5824	0	0
T4	341373	341258	0	0
T6	922959	922888	0	0
T7	439490	439483	0	0
T11	34479	34380	0	0
T12	180289	180195	0	0
T20	11818	11750	0	0
T21	38659	38593	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T7
1	0	1	Covered	T2,T12,T6
1	1	0	Covered	T1,T4,T20
1	1	1	Covered	T1,T4,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T77,T78
1	0	Covered	T5,T23,T77

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T23,T77

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T1,T77,T78

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T50

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T23,T51

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T23
1	Covered	T1,T2,T3

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T4,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T4,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T59,T90,T91
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T51,T57,T92
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T55,T58,T93
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T72,T85,T54
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T4,T23
TimeoutSt->Phase0St	172	Covered	T1,T5,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T90,T91,T93
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T51,T57,T92
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T55,T58,T93
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T72,T85,T54
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T5,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	606803802	216	0	0
CheckAccumTrig0_A	606803802	508	0	0
CheckAccumTrig1_A	606803802	24	0	0
CheckClr_A	606803802	233	0	0
CheckEn_A	606666094	233774028	0	0
CheckPhase0_A	606803802	568	0	0
CheckPhase1_A	606803802	560	0	0
CheckPhase2_A	606803802	547	0	0
CheckPhase3_A	606803802	537	0	0
CheckTimeout0_A	606803802	801	0	0
CheckTimeoutSt1_A	606803802	97973	0	0
CheckTimeoutSt2_A	606803802	721	0	0
CheckTimeoutStTrig_A	606803802	54	0	0
ErrorStAllEscAsserted_A	606803802	1284	0	0
ErrorStIsTerminal_A	606803802	1044	0	0
EscStateOut_A	606665254	606594861	0	0
u_state_regs_A	606803802	606631418	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	216	0	0
T8	30725	60	0	0
T9	0	44	0	0
T10	0	57	0	0
T33	519772	0	0	0
T34	452429	0	0	0
T39	0	32	0	0
T40	0	23	0	0
T41	59652	0	0	0
T42	66815	0	0	0
T43	3520	0	0	0
T44	34248	0	0	0
T45	4841	0	0	0
T46	76819	0	0	0
T47	444156	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	508	0	0
T1	314833	3	0	0
T2	50732	1	0	0
T3	5913	1	0	0
T4	341373	3	0	0
T5	0	1	0	0
T6	922959	0	0	0
T7	439490	1	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T13	0	1	0	0
T19	0	1	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T50	0	1	0	0
T51	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	24	0	0
T5	918017	1	0	0
T15	460049	0	0	0
T17	157580	0	0	0
T18	413446	0	0	0
T19	262630	0	0	0
T23	84977	1	0	0
T50	27955	0	0	0
T58	0	2	0	0
T59	0	1	0	0
T64	0	1	0	0
T68	35250	0	0	0
T69	38079	0	0	0
T75	89513	0	0	0
T77	0	2	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	233	0	0
T1	314833	1	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	0	0	0
T5	0	1	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T19	0	1	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T27	0	1	0	0
T30	0	2	0	0
T51	0	1	0	0
T72	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T98	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606666094	233774028	0	0
T1	314833	860086	0	0
T2	50732	3166	0	0
T3	5913	717	0	0
T4	341373	166971	0	0
T6	922959	874096	0	0
T7	439490	19833	0	0
T11	34479	34379	0	0
T12	180289	143969	0	0
T20	11818	11749	0	0
T21	38659	31821	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	568	0	0
T1	314833	4	0	0
T2	50732	1	0	0
T3	5913	1	0	0
T4	341373	3	0	0
T5	0	2	0	0
T6	922959	0	0	0
T7	439490	1	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T13	0	1	0	0
T19	0	1	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T23	0	1	0	0
T50	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	560	0	0
T1	314833	4	0	0
T2	50732	1	0	0
T3	5913	1	0	0
T4	341373	3	0	0
T5	0	2	0	0
T6	922959	0	0	0
T7	439490	1	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T13	0	1	0	0
T19	0	1	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T23	0	1	0	0
T50	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	547	0	0
T1	314833	4	0	0
T2	50732	1	0	0
T3	5913	1	0	0
T4	341373	3	0	0
T5	0	2	0	0
T6	922959	0	0	0
T7	439490	1	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T13	0	1	0	0
T19	0	1	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T23	0	1	0	0
T50	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	537	0	0
T1	314833	4	0	0
T2	50732	1	0	0
T3	5913	1	0	0
T4	341373	3	0	0
T5	0	2	0	0
T6	922959	0	0	0
T7	439490	1	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T13	0	1	0	0
T19	0	1	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T23	0	1	0	0
T50	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	801	0	0
T1	314833	2	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	3	0	0
T5	0	1	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T23	0	3	0	0
T27	0	3	0	0
T28	0	6	0	0
T68	0	2	0	0
T75	0	1	0	0
T77	0	5	0	0
T78	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	97973	0	0
T1	314833	379	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	310	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T23	0	213	0	0
T27	0	674	0	0
T28	0	285	0	0
T31	0	190	0	0
T68	0	338	0	0
T75	0	170	0	0
T77	0	554	0	0
T78	0	197	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	721	0	0
T1	314833	1	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	3	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T23	0	2	0	0
T27	0	3	0	0
T28	0	6	0	0
T31	0	4	0	0
T68	0	2	0	0
T75	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	54	0	0
T1	314833	1	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	0	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T34	0	2	0	0
T36	0	1	0	0
T53	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T83	0	2	0	0
T86	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	1284	0	0
T8	30725	304	0	0
T9	0	337	0	0
T10	0	312	0	0
T33	519772	0	0	0
T34	452429	0	0	0
T39	0	169	0	0
T40	0	162	0	0
T41	59652	0	0	0
T42	66815	0	0	0
T43	3520	0	0	0
T44	34248	0	0	0
T45	4841	0	0	0
T46	76819	0	0	0
T47	444156	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	1044	0	0
T8	30725	244	0	0
T9	0	277	0	0
T10	0	252	0	0
T33	519772	0	0	0
T34	452429	0	0	0
T39	0	139	0	0
T40	0	132	0	0
T41	59652	0	0	0
T42	66815	0	0	0
T43	3520	0	0	0
T44	34248	0	0	0
T45	4841	0	0	0
T46	76819	0	0	0
T47	444156	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606665254	606594861	0	0
T1	314833	314776	0	0
T2	50732	50666	0	0
T3	5913	5824	0	0
T4	341373	341258	0	0
T6	922959	922888	0	0
T7	439490	439483	0	0
T11	34479	34380	0	0
T12	180289	180195	0	0
T20	11818	11750	0	0
T21	38659	38593	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	606631418	0	0
T1	314833	314776	0	0
T2	50732	50666	0	0
T3	5913	5824	0	0
T4	341373	341258	0	0
T6	922959	922888	0	0
T7	439490	439483	0	0
T11	34479	34380	0	0
T12	180289	180195	0	0
T20	11818	11750	0	0
T21	38659	38593	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T13
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T4,T20
1	1	1	Covered	T1,T22,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T5
0	1	Covered	T22,T73,T30
1	0	Covered	T1,T55,T56

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T22,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T55,T56

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T5
1	0	Covered	T26
1	1	Covered	T22,T73,T30

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T4,T22

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T13,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T13
1	Covered	T2,T49,T14

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T23,T27

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T49

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T1,T22,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T1,T22,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T28,T29,T89
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T35,T101,T102
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T28,T33,T54
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T28,T101,T103
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T5,T68
TimeoutSt->Phase0St	172	Covered	T1,T22,T73

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T73
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T68
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T89,T104,T105
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T101,T102,T106
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T33,T54
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T101,T103,T58
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	606803802	249	0	0
CheckAccumTrig0_A	606803802	494	0	0
CheckAccumTrig1_A	606803802	21	0	0
CheckClr_A	606803802	191	0	0
CheckEn_A	606666094	243878359	0	0
CheckPhase0_A	606803802	551	0	0
CheckPhase1_A	606803802	540	0	0
CheckPhase2_A	606803802	530	0	0
CheckPhase3_A	606803802	523	0	0
CheckTimeout0_A	606803802	438	0	0
CheckTimeoutSt1_A	606803802	58031	0	0
CheckTimeoutSt2_A	606803802	364	0	0
CheckTimeoutStTrig_A	606803802	46	0	0
ErrorStAllEscAsserted_A	606803802	1315	0	0
ErrorStIsTerminal_A	606803802	1075	0	0
EscStateOut_A	606665254	606594861	0	0
u_state_regs_A	606803802	606631418	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	249	0	0
T8	30725	57	0	0
T9	0	69	0	0
T10	0	68	0	0
T33	519772	0	0	0
T34	452429	0	0	0
T39	0	35	0	0
T40	0	20	0	0
T41	59652	0	0	0
T42	66815	0	0	0
T43	3520	0	0	0
T44	34248	0	0	0
T45	4841	0	0	0
T46	76819	0	0	0
T47	444156	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	494	0	0
T1	314833	6	0	0
T2	50732	1	0	0
T3	5913	0	0	0
T4	341373	13	0	0
T5	0	3	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T19	0	1	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T23	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	21	0	0
T1	314833	2	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	0	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T58	0	1	0	0
T59	0	2	0	0
T61	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	191	0	0
T1	314833	5	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	10	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T16	0	1	0	0
T19	0	1	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T27	0	3	0	0
T28	0	2	0	0
T29	0	2	0	0
T30	0	1	0	0
T72	0	1	0	0
T74	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606666094	243878359	0	0
T1	314833	896406	0	0
T2	50732	4176	0	0
T3	5913	3198	0	0
T4	341373	191007	0	0
T6	922959	922887	0	0
T7	439490	439482	0	0
T11	34479	34379	0	0
T12	180289	24117	0	0
T20	11818	11749	0	0
T21	38659	38592	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	551	0	0
T1	314833	8	0	0
T2	50732	1	0	0
T3	5913	0	0	0
T4	341373	13	0	0
T5	0	3	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T19	0	1	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T49	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	540	0	0
T1	314833	8	0	0
T2	50732	1	0	0
T3	5913	0	0	0
T4	341373	13	0	0
T5	0	3	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T19	0	1	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T49	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	530	0	0
T1	314833	8	0	0
T2	50732	1	0	0
T3	5913	0	0	0
T4	341373	13	0	0
T5	0	3	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T19	0	1	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T49	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	523	0	0
T1	314833	8	0	0
T2	50732	1	0	0
T3	5913	0	0	0
T4	341373	13	0	0
T5	0	3	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T19	0	1	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T49	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	438	0	0
T1	314833	5	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	0	0	0
T5	0	1	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T22	0	1	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	0	1	0	0
T30	0	1	0	0
T68	0	6	0	0
T73	0	1	0	0
T75	0	10	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	58031	0	0
T1	314833	318	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	0	0	0
T5	0	52	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T22	0	896	0	0
T27	0	338	0	0
T28	0	146	0	0
T29	0	69	0	0
T30	0	80	0	0
T68	0	901	0	0
T73	0	108	0	0
T75	0	1651	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	364	0	0
T1	314833	3	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	0	0	0
T5	0	1	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T27	0	1	0	0
T28	0	2	0	0
T29	0	1	0	0
T34	0	5	0	0
T68	0	6	0	0
T74	0	1	0	0
T75	0	10	0	0
T79	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	46	0	0
T5	918017	0	0	0
T14	354044	0	0	0
T15	460049	0	0	0
T17	157580	0	0	0
T18	413446	0	0	0
T22	43784	1	0	0
T23	84977	0	0	0
T30	0	1	0	0
T35	0	1	0	0
T59	0	2	0	0
T68	35250	0	0	0
T69	38079	0	0	0
T73	0	1	0	0
T75	89513	0	0	0
T80	0	1	0	0
T83	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	1315	0	0
T8	30725	305	0	0
T9	0	339	0	0
T10	0	338	0	0
T33	519772	0	0	0
T34	452429	0	0	0
T39	0	168	0	0
T40	0	165	0	0
T41	59652	0	0	0
T42	66815	0	0	0
T43	3520	0	0	0
T44	34248	0	0	0
T45	4841	0	0	0
T46	76819	0	0	0
T47	444156	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	1075	0	0
T8	30725	245	0	0
T9	0	279	0	0
T10	0	278	0	0
T33	519772	0	0	0
T34	452429	0	0	0
T39	0	138	0	0
T40	0	135	0	0
T41	59652	0	0	0
T42	66815	0	0	0
T43	3520	0	0	0
T44	34248	0	0	0
T45	4841	0	0	0
T46	76819	0	0	0
T47	444156	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606665254	606594861	0	0
T1	314833	314776	0	0
T2	50732	50666	0	0
T3	5913	5824	0	0
T4	341373	341258	0	0
T6	922959	922888	0	0
T7	439490	439483	0	0
T11	34479	34380	0	0
T12	180289	180195	0	0
T20	11818	11750	0	0
T21	38659	38593	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	606631418	0	0
T1	314833	314776	0	0
T2	50732	50666	0	0
T3	5913	5824	0	0
T4	341373	341258	0	0
T6	922959	922888	0	0
T7	439490	439483	0	0
T11	34479	34380	0	0
T12	180289	180195	0	0
T20	11818	11750	0	0
T21	38659	38593	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T20
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T1,T4,T13
1	1	1	Covered	T1,T4,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T20
0	1	Covered	T23,T69,T27
1	0	Covered	T20,T28,T33

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T20,T28,T33

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T20
1	0	Covered	T24,T25
1	1	Covered	T23,T69,T27

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T12,T13
1	Covered	T4,T20,T48

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T12
1	Covered	T13,T5,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T20
1	Covered	T1,T12,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T12
1	Covered	T1,T22,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T12
Phase1St	198	Covered	T1,T4,T12
Phase2St	215	Covered	T1,T4,T12
Phase3St	233	Covered	T1,T4,T12
TerminalSt	249	Covered	T1,T4,T12
TimeoutSt	159	Covered	T1,T4,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T4,T12
IdleSt->TimeoutSt	159	Covered	T1,T4,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T27,T107,T33
Phase0St->Phase1St	198	Covered	T1,T4,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T23,T108,T91
Phase1St->Phase2St	215	Covered	T1,T4,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T28,T109,T62
Phase2St->Phase3St	233	Covered	T1,T4,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T27,T38,T33
Phase3St->TerminalSt	249	Covered	T1,T4,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T4,T20
TimeoutSt->Phase0St	172	Covered	T20,T23,T69

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T23,T69
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T110,T111
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T23,T108,T91
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T109,T62
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T38,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T20,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	606803802	257	0	0
CheckAccumTrig0_A	606803802	503	0	0
CheckAccumTrig1_A	606803802	30	0	0
CheckClr_A	606803802	214	0	0
CheckEn_A	606666094	220457917	0	0
CheckPhase0_A	606803802	570	0	0
CheckPhase1_A	606803802	557	0	0
CheckPhase2_A	606803802	540	0	0
CheckPhase3_A	606803802	533	0	0
CheckTimeout0_A	606803802	660	0	0
CheckTimeoutSt1_A	606803802	68627	0	0
CheckTimeoutSt2_A	606803802	568	0	0
CheckTimeoutStTrig_A	606803802	57	0	0
ErrorStAllEscAsserted_A	606803802	1216	0	0
ErrorStIsTerminal_A	606803802	976	0	0
EscStateOut_A	606665254	606594861	0	0
u_state_regs_A	606803802	606631418	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	257	0	0
T8	30725	46	0	0
T9	0	62	0	0
T10	0	65	0	0
T33	519772	0	0	0
T34	452429	0	0	0
T39	0	50	0	0
T40	0	34	0	0
T41	59652	0	0	0
T42	66815	0	0	0
T43	3520	0	0	0
T44	34248	0	0	0
T45	4841	0	0	0
T46	76819	0	0	0
T47	444156	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	503	0	0
T1	314833	4	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	3	0	0
T5	0	7	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T19	0	2	0	0
T20	11818	0	0	0
T21	38659	0	0	0
T22	0	2	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	30	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T13	336923	0	0	0
T14	354044	0	0	0
T20	11818	1	0	0
T21	38659	0	0	0
T22	43784	0	0	0
T24	0	1	0	0
T28	0	1	0	0
T33	0	2	0	0
T48	1181	0	0	0
T49	7735	0	0	0
T53	0	1	0	0
T56	0	3	0	0
T58	0	2	0	0
T59	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	214	0	0
T1	314833	1	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	0	0	0
T5	0	3	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T19	0	1	0	0
T20	11818	1	0	0
T21	38659	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T27	0	1	0	0
T28	0	1	0	0
T71	0	1	0	0
T73	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606666094	220457917	0	0
T1	314833	298507	0	0
T2	50732	50665	0	0
T3	5913	713	0	0
T4	341373	165850	0	0
T6	922959	778081	0	0
T7	439490	439482	0	0
T11	34479	34379	0	0
T12	180289	18157	0	0
T20	11818	3162	0	0
T21	38659	38592	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	570	0	0
T1	314833	4	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	3	0	0
T5	0	7	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T20	11818	1	0	0
T21	38659	0	0	0
T22	0	2	0	0
T23	0	2	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	557	0	0
T1	314833	4	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	3	0	0
T5	0	7	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T20	11818	1	0	0
T21	38659	0	0	0
T22	0	2	0	0
T23	0	1	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	540	0	0
T1	314833	4	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	3	0	0
T5	0	7	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T20	11818	1	0	0
T21	38659	0	0	0
T22	0	2	0	0
T23	0	1	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	533	0	0
T1	314833	4	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	3	0	0
T5	0	7	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T20	11818	1	0	0
T21	38659	0	0	0
T22	0	2	0	0
T23	0	1	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	660	0	0
T1	314833	2	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	1	0	0
T5	0	1	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T20	11818	2	0	0
T21	38659	0	0	0
T22	0	1	0	0
T23	0	2	0	0
T27	0	2	0	0
T68	0	3	0	0
T69	0	1	0	0
T76	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	68627	0	0
T1	314833	216	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	134	0	0
T5	0	35	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T20	11818	44	0	0
T21	38659	0	0	0
T22	0	29	0	0
T23	0	78	0	0
T27	0	349	0	0
T68	0	456	0	0
T69	0	16	0	0
T76	0	440	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	568	0	0
T1	314833	2	0	0
T2	50732	0	0	0
T3	5913	0	0	0
T4	341373	1	0	0
T5	0	1	0	0
T6	922959	0	0	0
T7	439490	0	0	0
T11	34479	0	0	0
T12	180289	0	0	0
T20	11818	1	0	0
T21	38659	0	0	0
T22	0	1	0	0
T28	0	6	0	0
T30	0	3	0	0
T31	0	1	0	0
T68	0	3	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	57	0	0
T15	460049	0	0	0
T17	157580	0	0	0
T18	413446	0	0	0
T19	262630	0	0	0
T23	84977	2	0	0
T27	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T50	27955	0	0	0
T51	285245	0	0	0
T68	35250	0	0	0
T69	38079	1	0	0
T75	89513	0	0	0
T99	0	1	0	0
T114	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	1216	0	0
T8	30725	317	0	0
T9	0	321	0	0
T10	0	282	0	0
T33	519772	0	0	0
T34	452429	0	0	0
T39	0	157	0	0
T40	0	139	0	0
T41	59652	0	0	0
T42	66815	0	0	0
T43	3520	0	0	0
T44	34248	0	0	0
T45	4841	0	0	0
T46	76819	0	0	0
T47	444156	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	976	0	0
T8	30725	257	0	0
T9	0	261	0	0
T10	0	222	0	0
T33	519772	0	0	0
T34	452429	0	0	0
T39	0	127	0	0
T40	0	109	0	0
T41	59652	0	0	0
T42	66815	0	0	0
T43	3520	0	0	0
T44	34248	0	0	0
T45	4841	0	0	0
T46	76819	0	0	0
T47	444156	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606665254	606594861	0	0
T1	314833	314776	0	0
T2	50732	50666	0	0
T3	5913	5824	0	0
T4	341373	341258	0	0
T6	922959	922888	0	0
T7	439490	439483	0	0
T11	34479	34380	0	0
T12	180289	180195	0	0
T20	11818	11750	0	0
T21	38659	38593	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606803802	606631418	0	0
T1	314833	314776	0	0
T2	50732	50666	0	0
T3	5913	5824	0	0
T4	341373	341258	0	0
T6	922959	922888	0	0
T7	439490	439483	0	0
T11	34479	34380	0	0
T12	180289	180195	0	0
T20	11818	11750	0	0
T21	38659	38593	0	0