Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51141230	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24229296

1

T1

322

T2

813

T3

144

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12041880	1			T1	150		T2	313		T3	73
values[0x0]	31596759	1			T1	423		T2	1100		T3	186
values[0x1]	31731887	1			T1	439		T2	1070		T3	194

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44494285	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

30876241

1

T1

409

T2

1020

T3

183

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	245028	1			T1	13		T2	12		T3	2
valid_sources[0x01]	252528	1			T1	6		T2	11		T3	1
valid_sources[0x02]	230312	1			T2	9		T3	2		T18	5
valid_sources[0x03]	226876	1			T1	3		T2	9		T9	4
valid_sources[0x04]	230117	1			T1	6		T2	12		T3	2
valid_sources[0x05]	232035	1			T1	9		T2	7		T9	5
valid_sources[0x06]	227233	1			T1	2		T2	14		T3	5
valid_sources[0x07]	228838	1			T1	5		T2	8		T3	2
valid_sources[0x08]	439917	1			T1	5		T2	9		T9	5
valid_sources[0x09]	228811	1			T1	9		T2	9		T3	2
valid_sources[0x0a]	230975	1			T1	23		T2	7		T3	2
valid_sources[0x0b]	232136	1			T1	15		T2	11		T9	8
valid_sources[0x0c]	227902	1			T1	1		T2	6		T3	1
valid_sources[0x0d]	237239	1			T1	1		T2	8		T3	7
valid_sources[0x0e]	228644	1			T1	5		T2	4		T9	9
valid_sources[0x0f]	232211	1			T1	7		T2	9		T3	1
valid_sources[0x10]	238558	1			T2	6		T3	2		T9	7
valid_sources[0x11]	230647	1			T1	5		T2	8		T9	3
valid_sources[0x12]	254644	1			T2	9		T3	2		T9	3
valid_sources[0x13]	655895	1			T2	7		T3	8		T18	6
valid_sources[0x14]	232073	1			T1	1		T2	13		T3	1
valid_sources[0x15]	229413	1			T1	6		T2	7		T3	5
valid_sources[0x16]	224798	1			T1	16		T2	7		T18	1
valid_sources[0x17]	528411	1			T2	10		T3	4		T18	2
valid_sources[0x18]	233683	1			T2	8		T9	1		T11	6
valid_sources[0x19]	228667	1			T2	10		T3	3		T9	10
valid_sources[0x1a]	240800	1			T1	9		T2	16		T3	1
valid_sources[0x1b]	519082	1			T2	9		T3	1		T9	5
valid_sources[0x1c]	227180	1			T1	1		T2	5		T3	1
valid_sources[0x1d]	550922	1			T1	5		T2	5		T3	1
valid_sources[0x1e]	230258	1			T2	8		T3	1		T9	5
valid_sources[0x1f]	670208	1			T1	30		T2	8		T18	17
valid_sources[0x20]	227551	1			T2	17		T3	2		T9	3
valid_sources[0x21]	224935	1			T2	8		T3	4		T9	8
valid_sources[0x22]	722306	1			T2	8		T3	2		T9	7
valid_sources[0x23]	227457	1			T2	6		T3	2		T18	11
valid_sources[0x24]	228049	1			T2	14		T3	1		T9	5
valid_sources[0x25]	440130	1			T1	10		T2	7		T3	2
valid_sources[0x26]	228420	1			T1	1		T2	3		T3	2
valid_sources[0x27]	229970	1			T2	9		T3	1		T9	6
valid_sources[0x28]	230971	1			T2	5		T3	1		T9	5
valid_sources[0x29]	427219	1			T1	12		T2	7		T3	2
valid_sources[0x2a]	230724	1			T1	1		T2	8		T3	3
valid_sources[0x2b]	251149	1			T2	4		T3	6		T9	4
valid_sources[0x2c]	237539	1			T2	13		T3	2		T18	8
valid_sources[0x2d]	229022	1			T1	7		T2	11		T3	4
valid_sources[0x2e]	226583	1			T1	3		T2	8		T3	1
valid_sources[0x2f]	228073	1			T1	7		T2	7		T9	4
valid_sources[0x30]	707349	1			T1	1		T2	9		T3	2
valid_sources[0x31]	228350	1			T1	1		T2	12		T3	1
valid_sources[0x32]	254506	1			T2	10		T9	4		T4	3
valid_sources[0x33]	234863	1			T1	8		T2	11		T3	1
valid_sources[0x34]	229044	1			T2	12		T3	1		T9	6
valid_sources[0x35]	578416	1			T1	5		T2	13		T3	3
valid_sources[0x36]	467336	1			T1	24		T2	9		T9	9
valid_sources[0x37]	236103	1			T2	12		T18	3		T9	8
valid_sources[0x38]	227718	1			T1	3		T2	22		T3	5
valid_sources[0x39]	229335	1			T1	6		T2	8		T9	7
valid_sources[0x3a]	232971	1			T2	6		T3	2		T9	11
valid_sources[0x3b]	230684	1			T2	5		T3	3		T9	6
valid_sources[0x3c]	524458	1			T2	11		T3	1		T9	2
valid_sources[0x3d]	231314	1			T1	8		T2	8		T3	2
valid_sources[0x3e]	231399	1			T1	1		T2	18		T9	8
valid_sources[0x3f]	227793	1			T1	7		T2	8		T3	7
valid_sources[0x40]	632584	1			T1	9		T2	8		T3	1
valid_sources[0x41]	229584	1			T1	5		T2	6		T9	14
valid_sources[0x42]	237350	1			T1	4		T2	11		T3	3
valid_sources[0x43]	224676	1			T1	19		T2	12		T18	1
valid_sources[0x44]	229597	1			T2	17		T9	8		T4	2
valid_sources[0x45]	229897	1			T1	2		T2	7		T3	3
valid_sources[0x46]	585750	1			T1	20		T2	12		T3	1
valid_sources[0x47]	232958	1			T2	12		T3	2		T18	6
valid_sources[0x48]	231491	1			T2	9		T9	13		T4	1
valid_sources[0x49]	229959	1			T2	10		T18	1		T9	5
valid_sources[0x4a]	238906	1			T1	1		T2	15		T9	6
valid_sources[0x4b]	230779	1			T2	9		T3	2		T18	3
valid_sources[0x4c]	224582	1			T1	1		T2	5		T3	5
valid_sources[0x4d]	637073	1			T2	7		T3	2		T9	9
valid_sources[0x4e]	240950	1			T1	1		T2	14		T3	1
valid_sources[0x4f]	232550	1			T1	2		T2	9		T3	2
valid_sources[0x50]	306948	1			T2	8		T3	2		T9	5
valid_sources[0x51]	225409	1			T1	10		T2	12		T3	1
valid_sources[0x52]	263909	1			T1	1		T2	12		T3	2
valid_sources[0x53]	227591	1			T1	24		T2	4		T3	4
valid_sources[0x54]	261053	1			T1	5		T2	11		T3	3
valid_sources[0x55]	230945	1			T2	9		T3	3		T9	9
valid_sources[0x56]	234459	1			T2	11		T3	1		T9	6
valid_sources[0x57]	227931	1			T1	2		T2	11		T3	2
valid_sources[0x58]	428728	1			T1	4		T2	4		T3	1
valid_sources[0x59]	642045	1			T2	10		T18	6		T9	10
valid_sources[0x5a]	240260	1			T1	15		T2	9		T3	3
valid_sources[0x5b]	277221	1			T2	21		T9	7		T5	2
valid_sources[0x5c]	582079	1			T1	14		T2	8		T3	2
valid_sources[0x5d]	231687	1			T1	2		T2	8		T9	4
valid_sources[0x5e]	492570	1			T1	2		T2	12		T3	6
valid_sources[0x5f]	226318	1			T2	12		T3	3		T9	8
valid_sources[0x60]	237803	1			T1	2		T2	6		T18	7
valid_sources[0x61]	228121	1			T1	4		T2	11		T3	1
valid_sources[0x62]	649279	1			T1	5		T2	8		T3	2
valid_sources[0x63]	227280	1			T1	6		T2	8		T3	4
valid_sources[0x64]	241779	1			T2	8		T9	6		T4	1
valid_sources[0x65]	224800	1			T2	15		T3	1		T18	2
valid_sources[0x66]	235065	1			T1	2		T2	11		T3	1
valid_sources[0x67]	229589	1			T2	10		T3	4		T18	6
valid_sources[0x68]	226850	1			T1	2		T2	6		T3	1
valid_sources[0x69]	263760	1			T1	8		T2	13		T3	3
valid_sources[0x6a]	259981	1			T2	11		T3	3		T9	13
valid_sources[0x6b]	230480	1			T1	4		T2	8		T3	3
valid_sources[0x6c]	229047	1			T1	10		T2	19		T18	7
valid_sources[0x6d]	229253	1			T1	7		T2	12		T18	3
valid_sources[0x6e]	245960	1			T1	5		T2	14		T3	2
valid_sources[0x6f]	223895	1			T1	4		T2	7		T3	1
valid_sources[0x70]	230705	1			T2	6		T9	6		T11	3
valid_sources[0x71]	252327	1			T1	3		T2	11		T3	2
valid_sources[0x72]	229230	1			T2	8		T3	5		T9	8
valid_sources[0x73]	226962	1			T1	4		T2	13		T3	4
valid_sources[0x74]	235150	1			T2	10		T3	2		T9	3
valid_sources[0x75]	227471	1			T2	4		T3	1		T18	1
valid_sources[0x76]	228798	1			T2	8		T3	4		T9	9
valid_sources[0x77]	229070	1			T1	1		T2	8		T18	1
valid_sources[0x78]	270263	1			T2	6		T3	2		T9	11
valid_sources[0x79]	227240	1			T1	11		T2	16		T18	2
valid_sources[0x7a]	229523	1			T2	8		T3	1		T9	3
valid_sources[0x7b]	229629	1			T2	15		T3	2		T9	3
valid_sources[0x7c]	721532	1			T1	4		T2	9		T3	2
valid_sources[0x7d]	227491	1			T1	10		T2	13		T3	1
valid_sources[0x7e]	233715	1			T2	5		T18	6		T9	9
valid_sources[0x7f]	229918	1			T2	18		T3	3		T18	2
valid_sources[0x80]	707128	1			T2	10		T3	1		T9	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5766437

1

T1

67

T2

171

T3

40

values[0x0]

all_enables

biggest_size

11788805

1

T1

155

T2

426

T3

77

values[0x1]

all_enables

biggest_size

6674054

1

T1

100

T2

216

T3

27