Module Definition
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Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=6 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 70399 70399 0 0
OutputsKnown_A 2147483647 2147483647 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 2147483647 2147483647 0 89712
gen_no_flops.OutputDelay_A 2147483647 2147483647 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 70399 70399 0 0
T1 113 113 0 0
T2 113 113 0 0
T3 113 113 0 0
T4 113 113 0 0
T5 113 113 0 0
T9 113 113 0 0
T10 113 113 0 0
T11 113 113 0 0
T12 113 113 0 0
T18 113 113 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 336062 326796 0 0
T2 854506 843997 0 0
T3 2101800 2083494 0 0
T4 2545438 2530183 0 0
T5 2197172 741393 0 0
T9 2407352 2398425 0 0
T10 718341 710996 0 0
T11 555847 550197 0 0
T12 322728 316287 0 0
T18 188145 180122 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 89712
T1 142752 138672 0 144
T2 362976 358368 0 144
T3 892800 884736 0 144
T4 1081248 1074480 0 144
T5 933312 290304 0 144
T9 1022592 1018656 0 144
T10 305136 301872 0 144
T11 236112 233568 0 144
T12 137088 134208 0 144
T18 79920 76368 0 144

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 193310 187980 0 0
T2 491530 485485 0 0
T3 1209000 1198470 0 0
T4 1464190 1455415 0 0
T5 1263860 426465 0 0
T9 1384760 1379625 0 0
T10 413205 408980 0 0
T11 319735 316485 0 0
T12 185640 181935 0 0
T18 108225 103610 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 556159680 555968450 0 1869


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555968450 0 1869
T1 2974 2889 0 3
T2 7562 7466 0 3
T3 18600 18432 0 3
T4 22526 22385 0 3
T5 19444 6048 0 3
T9 21304 21222 0 3
T10 6357 6289 0 3
T11 4919 4866 0 3
T12 2856 2796 0 3
T18 1665 1591 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 623 623 0 0
OutputsKnown_A 556159680 555976364 0 0
gen_no_flops.OutputDelay_A 556159680 555976364 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 623 623 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556159680 555976364 0 0
T1 2974 2892 0 0
T2 7562 7469 0 0
T3 18600 18438 0 0
T4 22526 22391 0 0
T5 19444 6561 0 0
T9 21304 21225 0 0
T10 6357 6292 0 0
T11 4919 4869 0 0
T12 2856 2799 0 0
T18 1665 1594 0 0

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