Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T18
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T3,T9

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T10,T11
1	1	Covered	T1,T3,T9

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T10

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14222	0	0
DisabledNoTrigBkwd_A	2147483647	666749	0	0
DisabledNoTrigFwd_A	2147483647	1256566510	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14222	0	0
T4	67578	0	0	0
T5	58332	0	0	0
T6	21532	0	0	0
T7	114870	0	0	0
T9	21304	0	0	0
T10	12714	1560	0	0
T11	14757	1443	0	0
T12	8568	594	0	0
T13	3945	597	0	0
T14	19226	0	0	0
T15	31550	0	0	0
T16	25683	0	0	0
T18	1665	594	0	0
T19	33778	0	0	0
T20	80073	0	0	0
T21	90243	0	0	0
T25	48856	0	0	0
T31	64396	0	0	0
T45	46054	0	0	0
T46	28765	0	0	0
T48	34401	0	0	0
T60	0	567	0	0
T87	0	177	0	0
T101	0	584	0	0
T136	0	739	0	0
T199	0	1262	0	0
T225	0	149	0	0
T226	0	1594	0	0
T227	0	550	0	0
T228	0	568	0	0
T229	0	717	0	0
T230	0	665	0	0
T231	0	794	0	0
T232	0	470	0	0
T233	0	250	0	0
T234	0	348	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	666749	0	0
T4	67578	0	0	0
T5	58332	0	0	0
T6	10766	0	0	0
T7	114870	0	0	0
T9	42608	2	0	0
T10	19071	24	0	0
T11	14757	36	0	0
T12	8568	1	0	0
T13	2630	12	0	0
T14	19226	2	0	0
T15	31550	49	0	0
T16	25683	136	0	0
T17	0	3	0	0
T18	1665	0	0	0
T19	33778	0	0	0
T20	80073	0	0	0
T21	90243	14	0	0
T25	48856	0	0	0
T31	64396	0	0	0
T39	0	37	0	0
T42	0	18	0	0
T45	46054	48	0	0
T46	28765	20	0	0
T47	0	2	0	0
T48	34401	0	0	0
T53	0	97	0	0
T55	0	14	0	0
T59	0	5	0	0
T60	0	3	0	0
T61	0	176	0	0
T62	0	37	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1256566510	0	0
T1	11896	9411	0	0
T2	30248	29876	0	0
T3	74400	43669	0	0
T4	90104	2760	0	0
T5	77776	26244	0	0
T9	85216	66817	0	0
T10	25428	17700	0	0
T11	19676	12460	0	0
T12	11424	8740	0	0
T18	6660	3844	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T18,T9
1	0	Covered	T1,T2,T5
1	1	Covered	T9,T11,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T87
1	1	Covered	T9,T11,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T11,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	556159680	2214	0	0
DisabledNoTrigBkwd_A	556159680	186767	0	0
DisabledNoTrigFwd_A	556159680	311744289	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556159680	2214	0	0
T4	22526	0	0	0
T5	19444	0	0	0
T6	10766	0	0	0
T7	38290	0	0	0
T11	4919	1443	0	0
T12	2856	594	0	0
T13	1315	0	0	0
T20	26691	0	0	0
T21	30081	0	0	0
T31	32198	0	0	0
T87	0	177	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556159680	186767	0	0
T4	22526	0	0	0
T5	19444	0	0	0
T7	38290	0	0	0
T9	21304	2	0	0
T10	6357	0	0	0
T11	4919	36	0	0
T12	2856	1	0	0
T15	0	30	0	0
T16	0	41	0	0
T17	0	1	0	0
T20	26691	0	0	0
T21	30081	14	0	0
T31	32198	0	0	0
T45	0	48	0	0
T46	0	20	0	0
T59	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556159680	311744289	0	0
T1	2974	2892	0	0
T2	7562	7469	0	0
T3	18600	3390	0	0
T4	22526	684	0	0
T5	19444	6561	0	0
T9	21304	3142	0	0
T10	6357	4389	0	0
T11	4919	3086	0	0
T12	2856	2171	0	0
T18	1665	955	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T18
1	0	Covered	T14,T15,T48
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T229
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	556159680	1314	0	0
DisabledNoTrigBkwd_A	556159680	206712	0	0
DisabledNoTrigFwd_A	556159680	285985471	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556159680	1314	0	0
T6	10766	0	0	0
T13	1315	597	0	0
T14	19226	0	0	0
T15	31550	0	0	0
T16	25683	0	0	0
T19	33778	0	0	0
T25	48856	0	0	0
T45	46054	0	0	0
T46	28765	0	0	0
T48	34401	0	0	0
T229	0	717	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556159680	206712	0	0
T6	10766	0	0	0
T13	1315	12	0	0
T14	19226	2	0	0
T15	31550	19	0	0
T16	25683	42	0	0
T17	0	2	0	0
T19	33778	0	0	0
T25	48856	0	0	0
T39	0	4	0	0
T42	0	14	0	0
T45	46054	0	0	0
T46	28765	0	0	0
T48	34401	0	0	0
T53	0	97	0	0
T61	0	146	0	0
T62	0	37	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556159680	285985471	0	0
T1	2974	735	0	0
T2	7562	7469	0	0
T3	18600	3403	0	0
T4	22526	688	0	0
T5	19444	6561	0	0
T9	21304	21225	0	0
T10	6357	4413	0	0
T11	4919	3106	0	0
T12	2856	2178	0	0
T18	1665	959	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T10,T11
1	0	Covered	T1,T20,T14
1	1	Covered	T10,T20,T14

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T60,T101
1	1	Covered	T10,T20,T14

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T20,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T16,T47

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	556159680	5807	0	0
DisabledNoTrigBkwd_A	556159680	154049	0	0
DisabledNoTrigFwd_A	556159680	326619377	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556159680	5807	0	0
T4	22526	0	0	0
T5	19444	0	0	0
T7	38290	0	0	0
T10	6357	1560	0	0
T11	4919	0	0	0
T12	2856	0	0	0
T13	1315	0	0	0
T20	26691	0	0	0
T21	30081	0	0	0
T31	32198	0	0	0
T60	0	567	0	0
T101	0	584	0	0
T199	0	1262	0	0
T225	0	149	0	0
T227	0	550	0	0
T230	0	665	0	0
T232	0	470	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556159680	154049	0	0
T4	22526	0	0	0
T5	19444	0	0	0
T7	38290	0	0	0
T10	6357	24	0	0
T11	4919	0	0	0
T12	2856	0	0	0
T13	1315	0	0	0
T16	0	53	0	0
T20	26691	0	0	0
T21	30081	0	0	0
T31	32198	0	0	0
T39	0	33	0	0
T42	0	4	0	0
T47	0	2	0	0
T55	0	14	0	0
T60	0	3	0	0
T61	0	30	0	0
T65	0	54	0	0
T86	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556159680	326619377	0	0
T1	2974	2892	0	0
T2	7562	7469	0	0
T3	18600	18438	0	0
T4	22526	692	0	0
T5	19444	6561	0	0
T9	21304	21225	0	0
T10	6357	4435	0	0
T11	4919	3120	0	0
T12	2856	2191	0	0
T18	1665	963	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T10,T11
1	0	Covered	T1,T14,T48
1	1	Covered	T18,T20,T14

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T136,T226
1	1	Covered	T18,T20,T14

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T20,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T15,T16

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	556159680	4887	0	0
DisabledNoTrigBkwd_A	556159680	119221	0	0
DisabledNoTrigFwd_A	556159680	332217373	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556159680	4887	0	0
T4	22526	0	0	0
T5	19444	0	0	0
T7	38290	0	0	0
T9	21304	0	0	0
T10	6357	0	0	0
T11	4919	0	0	0
T12	2856	0	0	0
T18	1665	594	0	0
T20	26691	0	0	0
T21	30081	0	0	0
T136	0	739	0	0
T226	0	1594	0	0
T228	0	568	0	0
T231	0	794	0	0
T233	0	250	0	0
T234	0	348	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556159680	119221	0	0
T4	22526	0	0	0
T5	19444	0	0	0
T7	38290	0	0	0
T9	21304	0	0	0
T10	6357	0	0	0
T11	4919	0	0	0
T12	2856	0	0	0
T15	0	125	0	0
T16	0	25	0	0
T18	1665	6	0	0
T20	26691	0	0	0
T21	30081	0	0	0
T39	0	3	0	0
T42	0	3	0	0
T47	0	22	0	0
T55	0	536	0	0
T61	0	131	0	0
T65	0	24	0	0
T86	0	11	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556159680	332217373	0	0
T1	2974	2892	0	0
T2	7562	7469	0	0
T3	18600	18438	0	0
T4	22526	696	0	0
T5	19444	6561	0	0
T9	21304	21225	0	0
T10	6357	4463	0	0
T11	4919	3148	0	0
T12	2856	2200	0	0
T18	1665	967	0	0