Line Coverage for Module :
alert_handler_esc_timer
| Line No. | Total | Covered | Percent |
TOTAL | | 101 | 101 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
ALWAYS | 134 | 89 | 89 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
ALWAYS | 305 | 3 | 3 | 100.00 |
84 logic [EscCntDw-1:0] thresh;
85 1/1 assign cnt_ge = (esc_cnt_o >= thresh);
Tests: T1 T2 T3
86
87 //////////////
88 // Main FSM //
89 //////////////
90
91 logic [N_PHASES-1:0] phase_oh;
92
93 // SEC_CM: ESC_TIMER.FSM.SPARSE
94 // Encoding generated with:
95 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96 // -s 784905746 --language=sv
97 //
98 // Hamming distance histogram:
99 //
100 // 0: --
101 // 1: --
102 // 2: --
103 // 3: --
104 // 4: --
105 // 5: |||||||||||||||||||| (46.43%)
106 // 6: |||||||||||||||||||| (46.43%)
107 // 7: ||| (7.14%)
108 // 8: --
109 // 9: --
110 // 10: --
111 //
112 // Minimum Hamming distance: 5
113 // Maximum Hamming distance: 7
114 // Minimum Hamming weight: 3
115 // Maximum Hamming weight: 9
116 //
117 localparam int StateWidth = 10;
118 typedef enum logic [StateWidth-1:0] {
119 IdleSt = 10'b1011011010,
120 TimeoutSt = 10'b0000100110,
121 Phase0St = 10'b1110000101,
122 Phase1St = 10'b0101010100,
123 Phase2St = 10'b0000011001,
124 Phase3St = 10'b1001100001,
125 TerminalSt = 10'b1101111111,
126 FsmErrorSt = 10'b0111101000
127 } state_e;
128
129 logic fsm_error;
130 state_e state_d, state_q;
131
132 always_comb begin : p_fsm
133 // default
134 1/1 state_d = state_q;
Tests: T1 T2 T3
135 1/1 esc_state_o = Idle;
Tests: T1 T2 T3
136 1/1 cnt_en = 1'b0;
Tests: T1 T2 T3
137 1/1 cnt_clr = 1'b0;
Tests: T1 T2 T3
138 1/1 esc_trig_o = 1'b0;
Tests: T1 T2 T3
139 1/1 phase_oh = '0;
Tests: T1 T2 T3
140 1/1 thresh = timeout_cyc_i;
Tests: T1 T2 T3
141 1/1 fsm_error = 1'b0;
Tests: T1 T2 T3
142 1/1 latch_crashdump_o = 1'b0;
Tests: T1 T2 T3
143
144 1/1 unique case (state_q)
Tests: T1 T2 T3
145 // wait for an escalation trigger or an alert trigger
146 // the latter will trigger an interrupt timeout
147 IdleSt: begin
148 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T3
149 1/1 esc_state_o = Idle;
Tests: T1 T2 T3
150
151 1/1 if (accu_trig_i && en_i && !clr_i) begin
Tests: T1 T2 T3
152 1/1 state_d = Phase0St;
Tests: T3 T9 T10
153 1/1 cnt_en = 1'b1;
Tests: T3 T9 T10
154 1/1 esc_trig_o = 1'b1;
Tests: T3 T9 T10
155 // the counter is zero in this state. so if the
156 // timeout count is zero (==disabled), cnt_ge will be true.
157 1/1 end else if (timeout_en_i && !cnt_ge && en_i) begin
Tests: T1 T2 T3
158 1/1 cnt_en = 1'b1;
Tests: T21 T31 T19
159 1/1 state_d = TimeoutSt;
Tests: T21 T31 T19
160 end
MISSING_ELSE
161 end
162 // we are in interrupt timeout state
163 // in case an escalation comes in, we immediately have to
164 // switch over to the first escalation phase.
165 // in case the interrupt timeout hits it's cycle count, we
166 // also enter escalation phase0.
167 // ongoing timeouts can always be cleared.
168 TimeoutSt: begin
169 1/1 esc_state_o = Timeout;
Tests: T21 T31 T19
170
171 1/1 if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
Tests: T21 T31 T19
172 1/1 state_d = Phase0St;
Tests: T17 T32 T33
173 1/1 cnt_en = 1'b1;
Tests: T17 T32 T33
174 1/1 cnt_clr = 1'b1;
Tests: T17 T32 T33
175 1/1 esc_trig_o = 1'b1;
Tests: T17 T32 T33
176 // the timeout enable is connected to the irq state
177 // if that is cleared, stop the timeout counter
178 1/1 end else if (timeout_en_i) begin
Tests: T21 T31 T19
179 1/1 cnt_en = 1'b1;
Tests: T21 T31 T19
180 end else begin
181 1/1 state_d = IdleSt;
Tests: T21 T31 T19
182 1/1 cnt_clr = 1'b1;
Tests: T21 T31 T19
183 end
184 end
185 // note: autolocking the clear signal is done in the regfile
186 Phase0St: begin
187 1/1 cnt_en = 1'b1;
Tests: T9 T10 T11
188 1/1 phase_oh[0] = 1'b1;
Tests: T9 T10 T11
189 1/1 thresh = phase_cyc_i[0];
Tests: T9 T10 T11
190 1/1 esc_state_o = Phase0;
Tests: T9 T10 T11
191 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b00);
Tests: T9 T10 T11
192
193 1/1 if (clr_i) begin
Tests: T9 T10 T11
194 1/1 state_d = IdleSt;
Tests: T34 T35 T36
195 1/1 cnt_clr = 1'b1;
Tests: T34 T35 T36
196 1/1 cnt_en = 1'b0;
Tests: T34 T35 T36
197 1/1 end else if (cnt_ge) begin
Tests: T9 T10 T11
198 1/1 state_d = Phase1St;
Tests: T9 T10 T11
199 1/1 cnt_clr = 1'b1;
Tests: T9 T10 T11
200 1/1 cnt_en = 1'b1;
Tests: T9 T10 T11
201 end
MISSING_ELSE
202 end
203 Phase1St: begin
204 1/1 cnt_en = 1'b1;
Tests: T9 T10 T11
205 1/1 phase_oh[1] = 1'b1;
Tests: T9 T10 T11
206 1/1 thresh = phase_cyc_i[1];
Tests: T9 T10 T11
207 1/1 esc_state_o = Phase1;
Tests: T9 T10 T11
208 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b01);
Tests: T9 T10 T11
209
210 1/1 if (clr_i) begin
Tests: T9 T10 T11
211 1/1 state_d = IdleSt;
Tests: T34 T37 T38
212 1/1 cnt_clr = 1'b1;
Tests: T34 T37 T38
213 1/1 cnt_en = 1'b0;
Tests: T34 T37 T38
214 1/1 end else if (cnt_ge) begin
Tests: T9 T10 T11
215 1/1 state_d = Phase2St;
Tests: T9 T10 T11
216 1/1 cnt_clr = 1'b1;
Tests: T9 T10 T11
217 1/1 cnt_en = 1'b1;
Tests: T9 T10 T11
218 end
MISSING_ELSE
219 end
220 Phase2St: begin
221 1/1 cnt_en = 1'b1;
Tests: T9 T10 T11
222 1/1 phase_oh[2] = 1'b1;
Tests: T9 T10 T11
223 1/1 thresh = phase_cyc_i[2];
Tests: T9 T10 T11
224 1/1 esc_state_o = Phase2;
Tests: T9 T10 T11
225 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b10);
Tests: T9 T10 T11
226
227
228 1/1 if (clr_i) begin
Tests: T9 T10 T11
229 1/1 state_d = IdleSt;
Tests: T39 T40 T41
230 1/1 cnt_clr = 1'b1;
Tests: T39 T40 T41
231 1/1 cnt_en = 1'b0;
Tests: T39 T40 T41
232 1/1 end else if (cnt_ge) begin
Tests: T9 T10 T11
233 1/1 state_d = Phase3St;
Tests: T9 T10 T11
234 1/1 cnt_clr = 1'b1;
Tests: T9 T10 T11
235 end
MISSING_ELSE
236 end
237 Phase3St: begin
238 1/1 cnt_en = 1'b1;
Tests: T9 T10 T11
239 1/1 phase_oh[3] = 1'b1;
Tests: T9 T10 T11
240 1/1 thresh = phase_cyc_i[3];
Tests: T9 T10 T11
241 1/1 esc_state_o = Phase3;
Tests: T9 T10 T11
242 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b11);
Tests: T9 T10 T11
243
244 1/1 if (clr_i) begin
Tests: T9 T10 T11
245 1/1 state_d = IdleSt;
Tests: T42 T43 T44
246 1/1 cnt_clr = 1'b1;
Tests: T42 T43 T44
247 1/1 cnt_en = 1'b0;
Tests: T42 T43 T44
248 1/1 end else if (cnt_ge) begin
Tests: T9 T10 T11
249 1/1 state_d = TerminalSt;
Tests: T9 T10 T11
250 1/1 cnt_clr = 1'b1;
Tests: T9 T10 T11
251 1/1 cnt_en = 1'b0;
Tests: T9 T10 T11
252 end
MISSING_ELSE
253 end
254 // final, terminal state after escalation.
255 // if clr is locked down, only a system reset
256 // will get us out of this state
257 TerminalSt: begin
258 1/1 cnt_clr = 1'b1;
Tests: T9 T10 T11
259 1/1 esc_state_o = Terminal;
Tests: T9 T10 T11
260 1/1 if (clr_i) begin
Tests: T9 T10 T11
261 1/1 state_d = IdleSt;
Tests: T45 T46 T47
262 end
MISSING_ELSE
263 end
264 // error state, only reached if the FSM has been
265 // glitched. in this state, we trigger all escalation
266 // actions at once.
267 FsmErrorSt: begin
268 1/1 esc_state_o = FsmError;
Tests: T5 T7 T8
269 1/1 fsm_error = 1'b1;
Tests: T5 T7 T8
270 end
271 // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272 // catch glitches.
273 default: begin
274 state_d = FsmErrorSt;
275 esc_state_o = FsmError;
276 fsm_error = 1'b1;
277 end
278 endcase
279
280 // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281 // if any of the duplicate counter pairs has an inconsistent state
282 // we move into the terminal FSM error state.
283 1/1 if (accu_fail_i || cnt_error) begin
Tests: T1 T2 T3
284 1/1 state_d = FsmErrorSt;
Tests: T5 T7 T8
285 1/1 fsm_error = 1'b1;
Tests: T5 T7 T8
286 end
MISSING_ELSE
287 end
288
289 logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290 for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291 // generate configuration mask for escalation enable signals
292 4/4 assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
293 // mask reduce current phase state vector
294 // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295 4/4 assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
296 end
297
298 ///////////////////
299 // FSM Registers //
300 ///////////////////
301
302 // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303 // an alert signal, this condition is handled internally in the alert handler. The
304 // EnableAlertTriggerSVA parameter is therefore set to 0.
305 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1 `ifdef SIMULATION
305.2 prim_sparse_fsm_flop #(
305.3 .StateEnumT(state_e),
305.4 .Width($bits(state_e)),
305.5 .ResetValue($bits(state_e)'(IdleSt)),
305.6 .EnableAlertTriggerSVA(0),
305.7 .CustomForceName("state_q")
305.8 ) u_state_regs (
305.9 .clk_i ( clk_i ),
305.10 .rst_ni ( rst_ni ),
305.11 .state_i ( state_d ),
305.12 .state_o ( )
305.13 );
305.14 always_ff @(posedge clk_i or negedge rst_ni) begin
305.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
305.16 1/1 state_q <= IdleSt;
Tests: T1 T2 T3
305.17 end else begin
305.18 1/1 state_q <= state_d;
Tests: T1 T2 T3
305.19 end
305.20 end
305.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))
305.22 else begin
305.23 `ifdef UVM
305.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
305.25 "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);
305.26 `else
305.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
305.28 `PRIM_STRINGIFY(u_state_regs_A));
305.29 `endif
305.30 end
305.31 `else
305.32 prim_sparse_fsm_flop #(
305.33 .StateEnumT(state_e),
305.34 .Width($bits(state_e)),
305.35 .ResetValue($bits(state_e)'(IdleSt)),
305.36 .EnableAlertTriggerSVA(0)
305.37 ) u_state_regs (
305.38 .clk_i ( clk_i ),
305.39 .rst_ni ( rst_ni ),
305.40 .state_i ( state_d ),
305.41 .state_o ( state_q )
305.42 );
305.43 `endif
Cond Coverage for Module :
alert_handler_esc_timer
| Total | Covered | Percent |
Conditions | 47 | 43 | 91.49 |
Logical | 47 | 43 | 91.49 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 66
EXPRESSION (cnt_clr && ((!cnt_en)))
---1--- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T3,T9,T10 |
1 | 1 | Covered | T1,T2,T3 |
LINE 66
EXPRESSION (cnt_clr && cnt_en)
---1--- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T9,T21,T31 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T9,T10 |
LINE 151
EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T18 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T9,T10 |
LINE 157
EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
------1----- -----2----- --3-
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T9,T21 |
1 | 0 | 1 | Covered | T10,T11,T12 |
1 | 1 | 0 | Covered | T1,T15,T48 |
1 | 1 | 1 | Covered | T21,T31,T19 |
LINE 171
EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
-----------------1----------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T21,T31,T19 |
0 | 1 | Covered | T17,T32,T49 |
1 | 0 | Covered | T17,T33,T39 |
LINE 171
SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T21,T31,T19 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T17,T33,T39 |
LINE 171
SUB-EXPRESSION (cnt_ge && timeout_en_i)
---1-- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T21,T31,T19 |
1 | 0 | Covered | T50,T51,T52 |
1 | 1 | Covered | T17,T32,T49 |
LINE 191
EXPRESSION (crashdump_phase_i == 2'b0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T9,T21,T15 |
1 | Covered | T10,T11,T12 |
LINE 208
EXPRESSION (crashdump_phase_i == 2'b1)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T9,T10,T11 |
1 | Covered | T53,T54,T55 |
LINE 225
EXPRESSION (crashdump_phase_i == 2'b10)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T9,T10,T11 |
1 | Covered | T21,T15,T16 |
LINE 242
EXPRESSION (crashdump_phase_i == 2'b11)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T10,T11,T12 |
1 | Covered | T9,T45,T46 |
LINE 283
EXPRESSION (accu_fail_i || cnt_error)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T5,T7,T8 |
LINE 295
EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T9,T10,T11 |
LINE 295
EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T9,T10,T11 |
LINE 295
EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T10,T11,T12 |
LINE 295
EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T9,T10,T11 |
FSM Coverage for Module :
alert_handler_esc_timer
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
8 |
8 |
100.00 |
(Not included in score) |
Transitions |
20 |
14 |
70.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
FsmErrorSt |
284 |
Covered |
T5,T7,T8 |
IdleSt |
181 |
Covered |
T1,T2,T3 |
Phase0St |
152 |
Covered |
T9,T10,T11 |
Phase1St |
198 |
Covered |
T9,T10,T11 |
Phase2St |
215 |
Covered |
T9,T10,T11 |
Phase3St |
233 |
Covered |
T9,T10,T11 |
TerminalSt |
249 |
Covered |
T9,T10,T11 |
TimeoutSt |
159 |
Covered |
T21,T31,T19 |
transitions | Line No. | Covered | Tests |
IdleSt->FsmErrorSt |
284 |
Covered |
T5,T7,T8 |
IdleSt->Phase0St |
152 |
Covered |
T9,T10,T11 |
IdleSt->TimeoutSt |
159 |
Covered |
T21,T31,T19 |
Phase0St->FsmErrorSt |
284 |
Not Covered |
|
Phase0St->IdleSt |
194 |
Covered |
T34,T56,T44 |
Phase0St->Phase1St |
198 |
Covered |
T9,T10,T11 |
Phase1St->FsmErrorSt |
284 |
Not Covered |
|
Phase1St->IdleSt |
211 |
Covered |
T34,T56,T44 |
Phase1St->Phase2St |
215 |
Covered |
T9,T10,T11 |
Phase2St->FsmErrorSt |
284 |
Not Covered |
|
Phase2St->IdleSt |
229 |
Covered |
T39,T56,T40 |
Phase2St->Phase3St |
233 |
Covered |
T9,T10,T11 |
Phase3St->FsmErrorSt |
284 |
Not Covered |
|
Phase3St->IdleSt |
245 |
Covered |
T42,T43,T44 |
Phase3St->TerminalSt |
249 |
Covered |
T9,T10,T11 |
TerminalSt->FsmErrorSt |
284 |
Not Covered |
|
TerminalSt->IdleSt |
261 |
Covered |
T45,T46,T47 |
TimeoutSt->FsmErrorSt |
284 |
Not Covered |
|
TimeoutSt->IdleSt |
181 |
Covered |
T21,T31,T19 |
TimeoutSt->Phase0St |
172 |
Covered |
T17,T32,T33 |
Branch Coverage for Module :
alert_handler_esc_timer
| Line No. | Total | Covered | Percent |
Branches |
|
26 |
26 |
100.00 |
CASE |
144 |
22 |
22 |
100.00 |
IF |
283 |
2 |
2 |
100.00 |
IF |
305 |
2 |
2 |
100.00 |
144 unique case (state_q)
-1-
145 // wait for an escalation trigger or an alert trigger
146 // the latter will trigger an interrupt timeout
147 IdleSt: begin
148 cnt_clr = 1'b1;
149 esc_state_o = Idle;
150
151 if (accu_trig_i && en_i && !clr_i) begin
-2-
152 state_d = Phase0St;
==>
153 cnt_en = 1'b1;
154 esc_trig_o = 1'b1;
155 // the counter is zero in this state. so if the
156 // timeout count is zero (==disabled), cnt_ge will be true.
157 end else if (timeout_en_i && !cnt_ge && en_i) begin
-3-
158 cnt_en = 1'b1;
==>
159 state_d = TimeoutSt;
160 end
MISSING_ELSE
==>
161 end
162 // we are in interrupt timeout state
163 // in case an escalation comes in, we immediately have to
164 // switch over to the first escalation phase.
165 // in case the interrupt timeout hits it's cycle count, we
166 // also enter escalation phase0.
167 // ongoing timeouts can always be cleared.
168 TimeoutSt: begin
169 esc_state_o = Timeout;
170
171 if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
-4-
172 state_d = Phase0St;
==>
173 cnt_en = 1'b1;
174 cnt_clr = 1'b1;
175 esc_trig_o = 1'b1;
176 // the timeout enable is connected to the irq state
177 // if that is cleared, stop the timeout counter
178 end else if (timeout_en_i) begin
-5-
179 cnt_en = 1'b1;
==>
180 end else begin
181 state_d = IdleSt;
==>
182 cnt_clr = 1'b1;
183 end
184 end
185 // note: autolocking the clear signal is done in the regfile
186 Phase0St: begin
187 cnt_en = 1'b1;
188 phase_oh[0] = 1'b1;
189 thresh = phase_cyc_i[0];
190 esc_state_o = Phase0;
191 latch_crashdump_o = (crashdump_phase_i == 2'b00);
192
193 if (clr_i) begin
-6-
194 state_d = IdleSt;
==>
195 cnt_clr = 1'b1;
196 cnt_en = 1'b0;
197 end else if (cnt_ge) begin
-7-
198 state_d = Phase1St;
==>
199 cnt_clr = 1'b1;
200 cnt_en = 1'b1;
201 end
MISSING_ELSE
==>
202 end
203 Phase1St: begin
204 cnt_en = 1'b1;
205 phase_oh[1] = 1'b1;
206 thresh = phase_cyc_i[1];
207 esc_state_o = Phase1;
208 latch_crashdump_o = (crashdump_phase_i == 2'b01);
209
210 if (clr_i) begin
-8-
211 state_d = IdleSt;
==>
212 cnt_clr = 1'b1;
213 cnt_en = 1'b0;
214 end else if (cnt_ge) begin
-9-
215 state_d = Phase2St;
==>
216 cnt_clr = 1'b1;
217 cnt_en = 1'b1;
218 end
MISSING_ELSE
==>
219 end
220 Phase2St: begin
221 cnt_en = 1'b1;
222 phase_oh[2] = 1'b1;
223 thresh = phase_cyc_i[2];
224 esc_state_o = Phase2;
225 latch_crashdump_o = (crashdump_phase_i == 2'b10);
226
227
228 if (clr_i) begin
-10-
229 state_d = IdleSt;
==>
230 cnt_clr = 1'b1;
231 cnt_en = 1'b0;
232 end else if (cnt_ge) begin
-11-
233 state_d = Phase3St;
==>
234 cnt_clr = 1'b1;
235 end
MISSING_ELSE
==>
236 end
237 Phase3St: begin
238 cnt_en = 1'b1;
239 phase_oh[3] = 1'b1;
240 thresh = phase_cyc_i[3];
241 esc_state_o = Phase3;
242 latch_crashdump_o = (crashdump_phase_i == 2'b11);
243
244 if (clr_i) begin
-12-
245 state_d = IdleSt;
==>
246 cnt_clr = 1'b1;
247 cnt_en = 1'b0;
248 end else if (cnt_ge) begin
-13-
249 state_d = TerminalSt;
==>
250 cnt_clr = 1'b1;
251 cnt_en = 1'b0;
252 end
MISSING_ELSE
==>
253 end
254 // final, terminal state after escalation.
255 // if clr is locked down, only a system reset
256 // will get us out of this state
257 TerminalSt: begin
258 cnt_clr = 1'b1;
259 esc_state_o = Terminal;
260 if (clr_i) begin
-14-
261 state_d = IdleSt;
==>
262 end
MISSING_ELSE
==>
263 end
264 // error state, only reached if the FSM has been
265 // glitched. in this state, we trigger all escalation
266 // actions at once.
267 FsmErrorSt: begin
268 esc_state_o = FsmError;
==>
269 fsm_error = 1'b1;
270 end
271 // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272 // catch glitches.
273 default: begin
274 state_d = FsmErrorSt;
==>
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T3,T9,T10 |
IdleSt |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T21,T31,T19 |
IdleSt |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
TimeoutSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T17,T32,T33 |
TimeoutSt |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T21,T31,T19 |
TimeoutSt |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T21,T31,T19 |
Phase0St |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T34,T35,T36 |
Phase0St |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T9,T10,T11 |
Phase0St |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T9,T21,T14 |
Phase1St |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T34,T37,T38 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
Covered |
T9,T10,T11 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T9,T21,T14 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T39,T40,T41 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
Covered |
T9,T10,T11 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
Covered |
T9,T21,T14 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T42,T43,T44 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T9,T10,T11 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T9,T21,T14 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T45,T46,T47 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T9,T10,T11 |
FsmErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T7,T8 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T7,T8 |
283 if (accu_fail_i || cnt_error) begin
-1-
284 state_d = FsmErrorSt;
==>
285 fsm_error = 1'b1;
286 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T8 |
0 |
Covered |
T1,T2,T3 |
305 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
alert_handler_esc_timer
Assertion Details
AccuFailToFsmError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1077 |
0 |
0 |
T5 |
77776 |
120 |
0 |
0 |
T6 |
43064 |
0 |
0 |
0 |
T7 |
153160 |
209 |
0 |
0 |
T8 |
0 |
234 |
0 |
0 |
T13 |
5260 |
0 |
0 |
0 |
T14 |
76904 |
0 |
0 |
0 |
T15 |
126200 |
0 |
0 |
0 |
T20 |
106764 |
0 |
0 |
0 |
T21 |
120324 |
0 |
0 |
0 |
T31 |
128792 |
0 |
0 |
0 |
T45 |
184216 |
0 |
0 |
0 |
T57 |
0 |
255 |
0 |
0 |
T58 |
0 |
259 |
0 |
0 |
CheckAccumTrig0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2168 |
0 |
0 |
T4 |
67578 |
0 |
0 |
0 |
T5 |
58332 |
0 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
114870 |
0 |
0 |
0 |
T9 |
42608 |
1 |
0 |
0 |
T10 |
19071 |
1 |
0 |
0 |
T11 |
14757 |
1 |
0 |
0 |
T12 |
8568 |
1 |
0 |
0 |
T13 |
2630 |
1 |
0 |
0 |
T14 |
19226 |
1 |
0 |
0 |
T15 |
31550 |
2 |
0 |
0 |
T16 |
25683 |
3 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
1665 |
0 |
0 |
0 |
T19 |
33778 |
0 |
0 |
0 |
T20 |
80073 |
0 |
0 |
0 |
T21 |
90243 |
1 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T31 |
64396 |
0 |
0 |
0 |
T39 |
0 |
4 |
0 |
0 |
T45 |
46054 |
2 |
0 |
0 |
T46 |
28765 |
2 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T61 |
0 |
3 |
0 |
0 |
T62 |
0 |
5 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
CheckAccumTrig1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
112 |
0 |
0 |
T17 |
5047 |
1 |
0 |
0 |
T32 |
31996 |
0 |
0 |
0 |
T33 |
58734 |
1 |
0 |
0 |
T34 |
67420 |
0 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T37 |
0 |
3 |
0 |
0 |
T39 |
15465 |
1 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T42 |
29110 |
1 |
0 |
0 |
T47 |
15520 |
0 |
0 |
0 |
T49 |
17971 |
0 |
0 |
0 |
T53 |
69336 |
0 |
0 |
0 |
T54 |
16857 |
0 |
0 |
0 |
T55 |
67727 |
0 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T57 |
42098 |
0 |
0 |
0 |
T59 |
20510 |
0 |
0 |
0 |
T60 |
1256 |
0 |
0 |
0 |
T61 |
49675 |
0 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
94473 |
1 |
0 |
0 |
T68 |
0 |
1 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T72 |
0 |
1 |
0 |
0 |
T73 |
0 |
1 |
0 |
0 |
T74 |
0 |
3 |
0 |
0 |
T75 |
0 |
1 |
0 |
0 |
T76 |
0 |
1 |
0 |
0 |
T77 |
10813 |
0 |
0 |
0 |
T78 |
5395 |
0 |
0 |
0 |
T79 |
54114 |
0 |
0 |
0 |
T80 |
77680 |
0 |
0 |
0 |
T81 |
6034 |
0 |
0 |
0 |
CheckClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1048 |
0 |
0 |
T8 |
42546 |
0 |
0 |
0 |
T16 |
25683 |
0 |
0 |
0 |
T17 |
5047 |
0 |
0 |
0 |
T19 |
33778 |
0 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T26 |
24466 |
0 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T34 |
0 |
6 |
0 |
0 |
T37 |
0 |
3 |
0 |
0 |
T39 |
15465 |
3 |
0 |
0 |
T42 |
29110 |
1 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T45 |
46054 |
1 |
0 |
0 |
T46 |
28765 |
1 |
0 |
0 |
T47 |
15520 |
1 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T49 |
17971 |
0 |
0 |
0 |
T54 |
0 |
1 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T57 |
42098 |
0 |
0 |
0 |
T59 |
20510 |
0 |
0 |
0 |
T61 |
49675 |
1 |
0 |
0 |
T62 |
99275 |
7 |
0 |
0 |
T63 |
0 |
2 |
0 |
0 |
T65 |
98827 |
2 |
0 |
0 |
T68 |
0 |
2 |
0 |
0 |
T79 |
54114 |
0 |
0 |
0 |
T82 |
0 |
1 |
0 |
0 |
T83 |
0 |
1 |
0 |
0 |
T84 |
0 |
1 |
0 |
0 |
T85 |
0 |
1 |
0 |
0 |
T86 |
24272 |
0 |
0 |
0 |
T87 |
984 |
0 |
0 |
0 |
CheckEn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1004811883 |
0 |
0 |
T1 |
11896 |
9408 |
0 |
0 |
T2 |
30248 |
29872 |
0 |
0 |
T3 |
74400 |
43663 |
0 |
0 |
T4 |
90104 |
2756 |
0 |
0 |
T5 |
1308 |
992 |
0 |
0 |
T9 |
85216 |
66814 |
0 |
0 |
T10 |
25428 |
17700 |
0 |
0 |
T11 |
19676 |
12460 |
0 |
0 |
T12 |
11424 |
8740 |
0 |
0 |
T18 |
6660 |
3844 |
0 |
0 |
CheckPhase0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2457 |
0 |
0 |
T4 |
67578 |
0 |
0 |
0 |
T5 |
58332 |
0 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
114870 |
0 |
0 |
0 |
T9 |
42608 |
1 |
0 |
0 |
T10 |
19071 |
1 |
0 |
0 |
T11 |
14757 |
1 |
0 |
0 |
T12 |
8568 |
1 |
0 |
0 |
T13 |
2630 |
1 |
0 |
0 |
T14 |
19226 |
1 |
0 |
0 |
T15 |
31550 |
2 |
0 |
0 |
T16 |
25683 |
3 |
0 |
0 |
T17 |
0 |
3 |
0 |
0 |
T18 |
1665 |
0 |
0 |
0 |
T19 |
33778 |
0 |
0 |
0 |
T20 |
80073 |
0 |
0 |
0 |
T21 |
90243 |
1 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T31 |
64396 |
0 |
0 |
0 |
T39 |
0 |
5 |
0 |
0 |
T42 |
0 |
3 |
0 |
0 |
T45 |
46054 |
2 |
0 |
0 |
T46 |
28765 |
2 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T61 |
0 |
3 |
0 |
0 |
T62 |
0 |
5 |
0 |
0 |
CheckPhase1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2384 |
0 |
0 |
T4 |
67578 |
0 |
0 |
0 |
T5 |
58332 |
0 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
114870 |
0 |
0 |
0 |
T9 |
42608 |
1 |
0 |
0 |
T10 |
19071 |
1 |
0 |
0 |
T11 |
14757 |
1 |
0 |
0 |
T12 |
8568 |
1 |
0 |
0 |
T13 |
2630 |
1 |
0 |
0 |
T14 |
19226 |
1 |
0 |
0 |
T15 |
31550 |
2 |
0 |
0 |
T16 |
25683 |
3 |
0 |
0 |
T17 |
0 |
3 |
0 |
0 |
T18 |
1665 |
0 |
0 |
0 |
T19 |
33778 |
0 |
0 |
0 |
T20 |
80073 |
0 |
0 |
0 |
T21 |
90243 |
1 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T31 |
64396 |
0 |
0 |
0 |
T39 |
0 |
5 |
0 |
0 |
T42 |
0 |
3 |
0 |
0 |
T45 |
46054 |
2 |
0 |
0 |
T46 |
28765 |
2 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T61 |
0 |
3 |
0 |
0 |
T62 |
0 |
5 |
0 |
0 |
CheckPhase2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2331 |
0 |
0 |
T4 |
67578 |
0 |
0 |
0 |
T5 |
58332 |
0 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
114870 |
0 |
0 |
0 |
T9 |
42608 |
1 |
0 |
0 |
T10 |
19071 |
1 |
0 |
0 |
T11 |
14757 |
1 |
0 |
0 |
T12 |
8568 |
1 |
0 |
0 |
T13 |
2630 |
1 |
0 |
0 |
T14 |
19226 |
1 |
0 |
0 |
T15 |
31550 |
2 |
0 |
0 |
T16 |
25683 |
3 |
0 |
0 |
T17 |
0 |
3 |
0 |
0 |
T18 |
1665 |
0 |
0 |
0 |
T19 |
33778 |
0 |
0 |
0 |
T20 |
80073 |
0 |
0 |
0 |
T21 |
90243 |
1 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T31 |
64396 |
0 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T42 |
0 |
3 |
0 |
0 |
T45 |
46054 |
2 |
0 |
0 |
T46 |
28765 |
2 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T61 |
0 |
3 |
0 |
0 |
T62 |
0 |
5 |
0 |
0 |
CheckPhase3_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2284 |
0 |
0 |
T4 |
67578 |
0 |
0 |
0 |
T5 |
58332 |
0 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
114870 |
0 |
0 |
0 |
T9 |
42608 |
1 |
0 |
0 |
T10 |
19071 |
1 |
0 |
0 |
T11 |
14757 |
1 |
0 |
0 |
T12 |
8568 |
1 |
0 |
0 |
T13 |
2630 |
1 |
0 |
0 |
T14 |
19226 |
1 |
0 |
0 |
T15 |
31550 |
2 |
0 |
0 |
T16 |
25683 |
3 |
0 |
0 |
T17 |
0 |
3 |
0 |
0 |
T18 |
1665 |
0 |
0 |
0 |
T19 |
33778 |
0 |
0 |
0 |
T20 |
80073 |
0 |
0 |
0 |
T21 |
90243 |
1 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T31 |
64396 |
0 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T42 |
0 |
2 |
0 |
0 |
T45 |
46054 |
2 |
0 |
0 |
T46 |
28765 |
2 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T61 |
0 |
3 |
0 |
0 |
T62 |
0 |
5 |
0 |
0 |
CheckTimeout0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1995 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T8 |
42546 |
0 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T16 |
25683 |
1 |
0 |
0 |
T17 |
10094 |
2 |
0 |
0 |
T19 |
67556 |
2 |
0 |
0 |
T21 |
30081 |
1 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T26 |
24466 |
0 |
0 |
0 |
T31 |
32198 |
1 |
0 |
0 |
T32 |
0 |
5 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T39 |
0 |
2 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T46 |
28765 |
0 |
0 |
0 |
T47 |
31040 |
0 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T53 |
138672 |
0 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T59 |
41020 |
0 |
0 |
0 |
T60 |
1256 |
0 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T66 |
0 |
2 |
0 |
0 |
T67 |
0 |
3 |
0 |
0 |
T77 |
10813 |
3 |
0 |
0 |
T79 |
0 |
1 |
0 |
0 |
T83 |
0 |
16 |
0 |
0 |
T88 |
0 |
8 |
0 |
0 |
T89 |
0 |
20 |
0 |
0 |
CheckTimeoutSt1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
274850 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T8 |
42546 |
0 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T16 |
25683 |
90 |
0 |
0 |
T17 |
10094 |
762 |
0 |
0 |
T19 |
67556 |
346 |
0 |
0 |
T21 |
30081 |
72 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T26 |
24466 |
0 |
0 |
0 |
T31 |
32198 |
123 |
0 |
0 |
T32 |
0 |
610 |
0 |
0 |
T39 |
0 |
66 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T46 |
28765 |
0 |
0 |
0 |
T47 |
31040 |
0 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T49 |
0 |
25 |
0 |
0 |
T53 |
138672 |
0 |
0 |
0 |
T55 |
0 |
75 |
0 |
0 |
T59 |
41020 |
0 |
0 |
0 |
T60 |
1256 |
0 |
0 |
0 |
T61 |
0 |
873 |
0 |
0 |
T62 |
0 |
975 |
0 |
0 |
T63 |
0 |
68 |
0 |
0 |
T67 |
0 |
363 |
0 |
0 |
T77 |
10813 |
197 |
0 |
0 |
T79 |
0 |
178 |
0 |
0 |
T83 |
0 |
2595 |
0 |
0 |
T88 |
0 |
1450 |
0 |
0 |
T89 |
0 |
2933 |
0 |
0 |
T90 |
0 |
200 |
0 |
0 |
T91 |
0 |
333 |
0 |
0 |
T92 |
0 |
1448 |
0 |
0 |
CheckTimeoutSt2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1639 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T8 |
42546 |
0 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T16 |
25683 |
1 |
0 |
0 |
T17 |
5047 |
0 |
0 |
0 |
T19 |
67556 |
2 |
0 |
0 |
T21 |
30081 |
1 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T26 |
24466 |
0 |
0 |
0 |
T31 |
32198 |
1 |
0 |
0 |
T32 |
0 |
4 |
0 |
0 |
T39 |
0 |
1 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T46 |
28765 |
0 |
0 |
0 |
T47 |
15520 |
0 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T53 |
69336 |
0 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T59 |
20510 |
0 |
0 |
0 |
T60 |
1256 |
0 |
0 |
0 |
T62 |
0 |
4 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T68 |
0 |
1 |
0 |
0 |
T77 |
10813 |
3 |
0 |
0 |
T83 |
0 |
15 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
T89 |
0 |
22 |
0 |
0 |
T90 |
0 |
1 |
0 |
0 |
T91 |
0 |
3 |
0 |
0 |
T92 |
0 |
3 |
0 |
0 |
T93 |
0 |
2 |
0 |
0 |
T94 |
0 |
2 |
0 |
0 |
CheckTimeoutStTrig_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
232 |
0 |
0 |
T17 |
5047 |
1 |
0 |
0 |
T28 |
53053 |
0 |
0 |
0 |
T29 |
22250 |
0 |
0 |
0 |
T32 |
63992 |
1 |
0 |
0 |
T33 |
58734 |
0 |
0 |
0 |
T34 |
67420 |
0 |
0 |
0 |
T37 |
0 |
3 |
0 |
0 |
T39 |
15465 |
0 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T42 |
29110 |
0 |
0 |
0 |
T44 |
0 |
5 |
0 |
0 |
T49 |
17971 |
1 |
0 |
0 |
T54 |
16857 |
0 |
0 |
0 |
T55 |
67727 |
0 |
0 |
0 |
T57 |
42098 |
0 |
0 |
0 |
T61 |
49675 |
1 |
0 |
0 |
T66 |
57567 |
0 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T69 |
0 |
2 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T79 |
0 |
1 |
0 |
0 |
T83 |
110923 |
1 |
0 |
0 |
T88 |
19843 |
0 |
0 |
0 |
T89 |
0 |
2 |
0 |
0 |
T90 |
34854 |
0 |
0 |
0 |
T91 |
0 |
4 |
0 |
0 |
T93 |
102645 |
0 |
0 |
0 |
T94 |
0 |
1 |
0 |
0 |
T95 |
0 |
2 |
0 |
0 |
T96 |
0 |
1 |
0 |
0 |
T97 |
0 |
1 |
0 |
0 |
T98 |
0 |
1 |
0 |
0 |
T99 |
0 |
1 |
0 |
0 |
T100 |
0 |
1 |
0 |
0 |
T101 |
1271 |
0 |
0 |
0 |
T102 |
45963 |
0 |
0 |
0 |
T103 |
5568 |
0 |
0 |
0 |
ErrorStAllEscAsserted_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
5837 |
0 |
0 |
T5 |
77776 |
613 |
0 |
0 |
T6 |
43064 |
0 |
0 |
0 |
T7 |
153160 |
1266 |
0 |
0 |
T8 |
0 |
1309 |
0 |
0 |
T13 |
5260 |
0 |
0 |
0 |
T14 |
76904 |
0 |
0 |
0 |
T15 |
126200 |
0 |
0 |
0 |
T20 |
106764 |
0 |
0 |
0 |
T21 |
120324 |
0 |
0 |
0 |
T31 |
128792 |
0 |
0 |
0 |
T45 |
184216 |
0 |
0 |
0 |
T57 |
0 |
1325 |
0 |
0 |
T58 |
0 |
1324 |
0 |
0 |
ErrorStIsTerminal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
4757 |
0 |
0 |
T5 |
77776 |
493 |
0 |
0 |
T6 |
43064 |
0 |
0 |
0 |
T7 |
153160 |
1026 |
0 |
0 |
T8 |
0 |
1069 |
0 |
0 |
T13 |
5260 |
0 |
0 |
0 |
T14 |
76904 |
0 |
0 |
0 |
T15 |
126200 |
0 |
0 |
0 |
T20 |
106764 |
0 |
0 |
0 |
T21 |
120324 |
0 |
0 |
0 |
T31 |
128792 |
0 |
0 |
0 |
T45 |
184216 |
0 |
0 |
0 |
T57 |
0 |
1085 |
0 |
0 |
T58 |
0 |
1084 |
0 |
0 |
EscStateOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
11896 |
11568 |
0 |
0 |
T2 |
30248 |
29876 |
0 |
0 |
T3 |
74400 |
73752 |
0 |
0 |
T4 |
90104 |
89564 |
0 |
0 |
T5 |
312 |
0 |
0 |
0 |
T9 |
85216 |
84900 |
0 |
0 |
T10 |
25428 |
25168 |
0 |
0 |
T11 |
19676 |
19476 |
0 |
0 |
T12 |
11424 |
11196 |
0 |
0 |
T18 |
6660 |
6376 |
0 |
0 |
T20 |
0 |
106476 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
11896 |
11568 |
0 |
0 |
T2 |
30248 |
29876 |
0 |
0 |
T3 |
74400 |
73752 |
0 |
0 |
T4 |
90104 |
89564 |
0 |
0 |
T5 |
77776 |
26244 |
0 |
0 |
T9 |
85216 |
84900 |
0 |
0 |
T10 |
25428 |
25168 |
0 |
0 |
T11 |
19676 |
19476 |
0 |
0 |
T12 |
11424 |
11196 |
0 |
0 |
T18 |
6660 |
6376 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer
| Line No. | Total | Covered | Percent |
TOTAL | | 101 | 101 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
ALWAYS | 134 | 89 | 89 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
ALWAYS | 305 | 3 | 3 | 100.00 |
84 logic [EscCntDw-1:0] thresh;
85 1/1 assign cnt_ge = (esc_cnt_o >= thresh);
Tests: T1 T2 T3
86
87 //////////////
88 // Main FSM //
89 //////////////
90
91 logic [N_PHASES-1:0] phase_oh;
92
93 // SEC_CM: ESC_TIMER.FSM.SPARSE
94 // Encoding generated with:
95 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96 // -s 784905746 --language=sv
97 //
98 // Hamming distance histogram:
99 //
100 // 0: --
101 // 1: --
102 // 2: --
103 // 3: --
104 // 4: --
105 // 5: |||||||||||||||||||| (46.43%)
106 // 6: |||||||||||||||||||| (46.43%)
107 // 7: ||| (7.14%)
108 // 8: --
109 // 9: --
110 // 10: --
111 //
112 // Minimum Hamming distance: 5
113 // Maximum Hamming distance: 7
114 // Minimum Hamming weight: 3
115 // Maximum Hamming weight: 9
116 //
117 localparam int StateWidth = 10;
118 typedef enum logic [StateWidth-1:0] {
119 IdleSt = 10'b1011011010,
120 TimeoutSt = 10'b0000100110,
121 Phase0St = 10'b1110000101,
122 Phase1St = 10'b0101010100,
123 Phase2St = 10'b0000011001,
124 Phase3St = 10'b1001100001,
125 TerminalSt = 10'b1101111111,
126 FsmErrorSt = 10'b0111101000
127 } state_e;
128
129 logic fsm_error;
130 state_e state_d, state_q;
131
132 always_comb begin : p_fsm
133 // default
134 1/1 state_d = state_q;
Tests: T1 T2 T3
135 1/1 esc_state_o = Idle;
Tests: T1 T2 T3
136 1/1 cnt_en = 1'b0;
Tests: T1 T2 T3
137 1/1 cnt_clr = 1'b0;
Tests: T1 T2 T3
138 1/1 esc_trig_o = 1'b0;
Tests: T1 T2 T3
139 1/1 phase_oh = '0;
Tests: T1 T2 T3
140 1/1 thresh = timeout_cyc_i;
Tests: T1 T2 T3
141 1/1 fsm_error = 1'b0;
Tests: T1 T2 T3
142 1/1 latch_crashdump_o = 1'b0;
Tests: T1 T2 T3
143
144 1/1 unique case (state_q)
Tests: T1 T2 T3
145 // wait for an escalation trigger or an alert trigger
146 // the latter will trigger an interrupt timeout
147 IdleSt: begin
148 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T3
149 1/1 esc_state_o = Idle;
Tests: T1 T2 T3
150
151 1/1 if (accu_trig_i && en_i && !clr_i) begin
Tests: T1 T2 T3
152 1/1 state_d = Phase0St;
Tests: T9 T11 T12
153 1/1 cnt_en = 1'b1;
Tests: T9 T11 T12
154 1/1 esc_trig_o = 1'b1;
Tests: T9 T11 T12
155 // the counter is zero in this state. so if the
156 // timeout count is zero (==disabled), cnt_ge will be true.
157 1/1 end else if (timeout_en_i && !cnt_ge && en_i) begin
Tests: T1 T2 T3
158 1/1 cnt_en = 1'b1;
Tests: T21 T31 T77
159 1/1 state_d = TimeoutSt;
Tests: T21 T31 T77
160 end
MISSING_ELSE
161 end
162 // we are in interrupt timeout state
163 // in case an escalation comes in, we immediately have to
164 // switch over to the first escalation phase.
165 // in case the interrupt timeout hits it's cycle count, we
166 // also enter escalation phase0.
167 // ongoing timeouts can always be cleared.
168 TimeoutSt: begin
169 1/1 esc_state_o = Timeout;
Tests: T21 T31 T77
170
171 1/1 if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
Tests: T21 T31 T77
172 1/1 state_d = Phase0St;
Tests: T32 T33 T49
173 1/1 cnt_en = 1'b1;
Tests: T32 T33 T49
174 1/1 cnt_clr = 1'b1;
Tests: T32 T33 T49
175 1/1 esc_trig_o = 1'b1;
Tests: T32 T33 T49
176 // the timeout enable is connected to the irq state
177 // if that is cleared, stop the timeout counter
178 1/1 end else if (timeout_en_i) begin
Tests: T21 T31 T77
179 1/1 cnt_en = 1'b1;
Tests: T21 T31 T77
180 end else begin
181 1/1 state_d = IdleSt;
Tests: T21 T31 T77
182 1/1 cnt_clr = 1'b1;
Tests: T21 T31 T77
183 end
184 end
185 // note: autolocking the clear signal is done in the regfile
186 Phase0St: begin
187 1/1 cnt_en = 1'b1;
Tests: T9 T11 T12
188 1/1 phase_oh[0] = 1'b1;
Tests: T9 T11 T12
189 1/1 thresh = phase_cyc_i[0];
Tests: T9 T11 T12
190 1/1 esc_state_o = Phase0;
Tests: T9 T11 T12
191 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b00);
Tests: T9 T11 T12
192
193 1/1 if (clr_i) begin
Tests: T9 T11 T12
194 1/1 state_d = IdleSt;
Tests: T34 T36 T104
195 1/1 cnt_clr = 1'b1;
Tests: T34 T36 T104
196 1/1 cnt_en = 1'b0;
Tests: T34 T36 T104
197 1/1 end else if (cnt_ge) begin
Tests: T9 T11 T12
198 1/1 state_d = Phase1St;
Tests: T9 T11 T12
199 1/1 cnt_clr = 1'b1;
Tests: T9 T11 T12
200 1/1 cnt_en = 1'b1;
Tests: T9 T11 T12
201 end
MISSING_ELSE
202 end
203 Phase1St: begin
204 1/1 cnt_en = 1'b1;
Tests: T9 T11 T12
205 1/1 phase_oh[1] = 1'b1;
Tests: T9 T11 T12
206 1/1 thresh = phase_cyc_i[1];
Tests: T9 T11 T12
207 1/1 esc_state_o = Phase1;
Tests: T9 T11 T12
208 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b01);
Tests: T9 T11 T12
209
210 1/1 if (clr_i) begin
Tests: T9 T11 T12
211 1/1 state_d = IdleSt;
Tests: T34 T37 T38
212 1/1 cnt_clr = 1'b1;
Tests: T34 T37 T38
213 1/1 cnt_en = 1'b0;
Tests: T34 T37 T38
214 1/1 end else if (cnt_ge) begin
Tests: T9 T11 T12
215 1/1 state_d = Phase2St;
Tests: T9 T11 T12
216 1/1 cnt_clr = 1'b1;
Tests: T9 T11 T12
217 1/1 cnt_en = 1'b1;
Tests: T9 T11 T12
218 end
MISSING_ELSE
219 end
220 Phase2St: begin
221 1/1 cnt_en = 1'b1;
Tests: T9 T11 T12
222 1/1 phase_oh[2] = 1'b1;
Tests: T9 T11 T12
223 1/1 thresh = phase_cyc_i[2];
Tests: T9 T11 T12
224 1/1 esc_state_o = Phase2;
Tests: T9 T11 T12
225 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b10);
Tests: T9 T11 T12
226
227
228 1/1 if (clr_i) begin
Tests: T9 T11 T12
229 1/1 state_d = IdleSt;
Tests: T41 T105 T71
230 1/1 cnt_clr = 1'b1;
Tests: T41 T105 T71
231 1/1 cnt_en = 1'b0;
Tests: T41 T105 T71
232 1/1 end else if (cnt_ge) begin
Tests: T9 T11 T12
233 1/1 state_d = Phase3St;
Tests: T9 T11 T12
234 1/1 cnt_clr = 1'b1;
Tests: T9 T11 T12
235 end
MISSING_ELSE
236 end
237 Phase3St: begin
238 1/1 cnt_en = 1'b1;
Tests: T9 T11 T12
239 1/1 phase_oh[3] = 1'b1;
Tests: T9 T11 T12
240 1/1 thresh = phase_cyc_i[3];
Tests: T9 T11 T12
241 1/1 esc_state_o = Phase3;
Tests: T9 T11 T12
242 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b11);
Tests: T9 T11 T12
243
244 1/1 if (clr_i) begin
Tests: T9 T11 T12
245 1/1 state_d = IdleSt;
Tests: T43 T40 T98
246 1/1 cnt_clr = 1'b1;
Tests: T43 T40 T98
247 1/1 cnt_en = 1'b0;
Tests: T43 T40 T98
248 1/1 end else if (cnt_ge) begin
Tests: T9 T11 T12
249 1/1 state_d = TerminalSt;
Tests: T9 T11 T12
250 1/1 cnt_clr = 1'b1;
Tests: T9 T11 T12
251 1/1 cnt_en = 1'b0;
Tests: T9 T11 T12
252 end
MISSING_ELSE
253 end
254 // final, terminal state after escalation.
255 // if clr is locked down, only a system reset
256 // will get us out of this state
257 TerminalSt: begin
258 1/1 cnt_clr = 1'b1;
Tests: T9 T11 T12
259 1/1 esc_state_o = Terminal;
Tests: T9 T11 T12
260 1/1 if (clr_i) begin
Tests: T9 T11 T12
261 1/1 state_d = IdleSt;
Tests: T45 T46 T32
262 end
MISSING_ELSE
263 end
264 // error state, only reached if the FSM has been
265 // glitched. in this state, we trigger all escalation
266 // actions at once.
267 FsmErrorSt: begin
268 1/1 esc_state_o = FsmError;
Tests: T5 T7 T8
269 1/1 fsm_error = 1'b1;
Tests: T5 T7 T8
270 end
271 // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272 // catch glitches.
273 default: begin
274 state_d = FsmErrorSt;
275 esc_state_o = FsmError;
276 fsm_error = 1'b1;
277 end
278 endcase
279
280 // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281 // if any of the duplicate counter pairs has an inconsistent state
282 // we move into the terminal FSM error state.
283 1/1 if (accu_fail_i || cnt_error) begin
Tests: T1 T2 T3
284 1/1 state_d = FsmErrorSt;
Tests: T5 T7 T8
285 1/1 fsm_error = 1'b1;
Tests: T5 T7 T8
286 end
MISSING_ELSE
287 end
288
289 logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290 for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291 // generate configuration mask for escalation enable signals
292 4/4 assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
293 // mask reduce current phase state vector
294 // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295 4/4 assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
296 end
297
298 ///////////////////
299 // FSM Registers //
300 ///////////////////
301
302 // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303 // an alert signal, this condition is handled internally in the alert handler. The
304 // EnableAlertTriggerSVA parameter is therefore set to 0.
305 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1 `ifdef SIMULATION
305.2 prim_sparse_fsm_flop #(
305.3 .StateEnumT(state_e),
305.4 .Width($bits(state_e)),
305.5 .ResetValue($bits(state_e)'(IdleSt)),
305.6 .EnableAlertTriggerSVA(0),
305.7 .CustomForceName("state_q")
305.8 ) u_state_regs (
305.9 .clk_i ( clk_i ),
305.10 .rst_ni ( rst_ni ),
305.11 .state_i ( state_d ),
305.12 .state_o ( )
305.13 );
305.14 always_ff @(posedge clk_i or negedge rst_ni) begin
305.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
305.16 1/1 state_q <= IdleSt;
Tests: T1 T2 T3
305.17 end else begin
305.18 1/1 state_q <= state_d;
Tests: T1 T2 T3
305.19 end
305.20 end
305.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))
305.22 else begin
305.23 `ifdef UVM
305.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
305.25 "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);
305.26 `else
305.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
305.28 `PRIM_STRINGIFY(u_state_regs_A));
305.29 `endif
305.30 end
305.31 `else
305.32 prim_sparse_fsm_flop #(
305.33 .StateEnumT(state_e),
305.34 .Width($bits(state_e)),
305.35 .ResetValue($bits(state_e)'(IdleSt)),
305.36 .EnableAlertTriggerSVA(0)
305.37 ) u_state_regs (
305.38 .clk_i ( clk_i ),
305.39 .rst_ni ( rst_ni ),
305.40 .state_i ( state_d ),
305.41 .state_o ( state_q )
305.42 );
305.43 `endif
Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer
| Total | Covered | Percent |
Conditions | 45 | 42 | 93.33 |
Logical | 45 | 42 | 93.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 66
EXPRESSION (cnt_clr && ((!cnt_en)))
---1--- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T9,T11,T12 |
1 | 1 | Covered | T1,T2,T3 |
LINE 66
EXPRESSION (cnt_clr && cnt_en)
---1--- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T9,T21,T31 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T9,T11,T12 |
LINE 151
EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T3,T18,T9 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T9,T11,T12 |
LINE 157
EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
------1----- -----2----- --3-
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T9,T21,T31 |
1 | 0 | 1 | Covered | T11,T12,T20 |
1 | 1 | 0 | Covered | T1,T48,T19 |
1 | 1 | 1 | Covered | T21,T31,T77 |
LINE 171
EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
-----------------1----------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T21,T31,T77 |
0 | 1 | Covered | T32,T49,T61 |
1 | 0 | Covered | T33,T65,T56 |
LINE 171
SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T21,T31,T77 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T33,T65,T56 |
LINE 171
SUB-EXPRESSION (cnt_ge && timeout_en_i)
---1-- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T21,T31,T77 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T32,T49,T61 |
LINE 191
EXPRESSION (crashdump_phase_i == 2'b0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T9,T21,T15 |
1 | Covered | T11,T12,T46 |
LINE 208
EXPRESSION (crashdump_phase_i == 2'b1)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T9,T11,T12 |
1 | Covered | T54,T49,T62 |
LINE 225
EXPRESSION (crashdump_phase_i == 2'b10)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T9,T11,T12 |
1 | Covered | T21,T15,T17 |
LINE 242
EXPRESSION (crashdump_phase_i == 2'b11)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T11,T12,T21 |
1 | Covered | T9,T45,T46 |
LINE 283
EXPRESSION (accu_fail_i || cnt_error)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T5,T7,T8 |
LINE 295
EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T9,T11,T12 |
LINE 295
EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T9,T11,T12 |
LINE 295
EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T11,T12,T21 |
LINE 295
EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T9,T11,T12 |
FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
8 |
8 |
100.00 |
(Not included in score) |
Transitions |
14 |
14 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
FsmErrorSt |
284 |
Covered |
T5,T7,T8 |
IdleSt |
181 |
Covered |
T1,T2,T3 |
Phase0St |
152 |
Covered |
T9,T11,T12 |
Phase1St |
198 |
Covered |
T9,T11,T12 |
Phase2St |
215 |
Covered |
T9,T11,T12 |
Phase3St |
233 |
Covered |
T9,T11,T12 |
TerminalSt |
249 |
Covered |
T9,T11,T12 |
TimeoutSt |
159 |
Covered |
T21,T31,T77 |
transitions | Line No. | Covered | Tests | Exclude Annotation |
IdleSt->FsmErrorSt |
284 |
Covered |
T5,T7,T8 |
|
IdleSt->Phase0St |
152 |
Covered |
T9,T11,T12 |
|
IdleSt->TimeoutSt |
159 |
Covered |
T21,T31,T77 |
|
Phase0St->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase0St->IdleSt |
194 |
Covered |
T34,T56,T44 |
|
Phase0St->Phase1St |
198 |
Covered |
T9,T11,T12 |
|
Phase1St->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase1St->IdleSt |
211 |
Covered |
T34,T37,T38 |
|
Phase1St->Phase2St |
215 |
Covered |
T9,T11,T12 |
|
Phase2St->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase2St->IdleSt |
229 |
Covered |
T41,T105,T71 |
|
Phase2St->Phase3St |
233 |
Covered |
T9,T11,T12 |
|
Phase3St->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase3St->IdleSt |
245 |
Covered |
T43,T40,T98 |
|
Phase3St->TerminalSt |
249 |
Covered |
T9,T11,T12 |
|
TerminalSt->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
TerminalSt->IdleSt |
261 |
Covered |
T45,T46,T32 |
|
TimeoutSt->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
TimeoutSt->IdleSt |
181 |
Covered |
T21,T31,T77 |
|
TimeoutSt->Phase0St |
172 |
Covered |
T32,T33,T49 |
|
Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer
| Line No. | Total | Covered | Percent |
Branches |
|
26 |
26 |
100.00 |
CASE |
144 |
22 |
22 |
100.00 |
IF |
283 |
2 |
2 |
100.00 |
IF |
305 |
2 |
2 |
100.00 |
144 unique case (state_q)
-1-
145 // wait for an escalation trigger or an alert trigger
146 // the latter will trigger an interrupt timeout
147 IdleSt: begin
148 cnt_clr = 1'b1;
149 esc_state_o = Idle;
150
151 if (accu_trig_i && en_i && !clr_i) begin
-2-
152 state_d = Phase0St;
==>
153 cnt_en = 1'b1;
154 esc_trig_o = 1'b1;
155 // the counter is zero in this state. so if the
156 // timeout count is zero (==disabled), cnt_ge will be true.
157 end else if (timeout_en_i && !cnt_ge && en_i) begin
-3-
158 cnt_en = 1'b1;
==>
159 state_d = TimeoutSt;
160 end
MISSING_ELSE
==>
161 end
162 // we are in interrupt timeout state
163 // in case an escalation comes in, we immediately have to
164 // switch over to the first escalation phase.
165 // in case the interrupt timeout hits it's cycle count, we
166 // also enter escalation phase0.
167 // ongoing timeouts can always be cleared.
168 TimeoutSt: begin
169 esc_state_o = Timeout;
170
171 if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
-4-
172 state_d = Phase0St;
==>
173 cnt_en = 1'b1;
174 cnt_clr = 1'b1;
175 esc_trig_o = 1'b1;
176 // the timeout enable is connected to the irq state
177 // if that is cleared, stop the timeout counter
178 end else if (timeout_en_i) begin
-5-
179 cnt_en = 1'b1;
==>
180 end else begin
181 state_d = IdleSt;
==>
182 cnt_clr = 1'b1;
183 end
184 end
185 // note: autolocking the clear signal is done in the regfile
186 Phase0St: begin
187 cnt_en = 1'b1;
188 phase_oh[0] = 1'b1;
189 thresh = phase_cyc_i[0];
190 esc_state_o = Phase0;
191 latch_crashdump_o = (crashdump_phase_i == 2'b00);
192
193 if (clr_i) begin
-6-
194 state_d = IdleSt;
==>
195 cnt_clr = 1'b1;
196 cnt_en = 1'b0;
197 end else if (cnt_ge) begin
-7-
198 state_d = Phase1St;
==>
199 cnt_clr = 1'b1;
200 cnt_en = 1'b1;
201 end
MISSING_ELSE
==>
202 end
203 Phase1St: begin
204 cnt_en = 1'b1;
205 phase_oh[1] = 1'b1;
206 thresh = phase_cyc_i[1];
207 esc_state_o = Phase1;
208 latch_crashdump_o = (crashdump_phase_i == 2'b01);
209
210 if (clr_i) begin
-8-
211 state_d = IdleSt;
==>
212 cnt_clr = 1'b1;
213 cnt_en = 1'b0;
214 end else if (cnt_ge) begin
-9-
215 state_d = Phase2St;
==>
216 cnt_clr = 1'b1;
217 cnt_en = 1'b1;
218 end
MISSING_ELSE
==>
219 end
220 Phase2St: begin
221 cnt_en = 1'b1;
222 phase_oh[2] = 1'b1;
223 thresh = phase_cyc_i[2];
224 esc_state_o = Phase2;
225 latch_crashdump_o = (crashdump_phase_i == 2'b10);
226
227
228 if (clr_i) begin
-10-
229 state_d = IdleSt;
==>
230 cnt_clr = 1'b1;
231 cnt_en = 1'b0;
232 end else if (cnt_ge) begin
-11-
233 state_d = Phase3St;
==>
234 cnt_clr = 1'b1;
235 end
MISSING_ELSE
==>
236 end
237 Phase3St: begin
238 cnt_en = 1'b1;
239 phase_oh[3] = 1'b1;
240 thresh = phase_cyc_i[3];
241 esc_state_o = Phase3;
242 latch_crashdump_o = (crashdump_phase_i == 2'b11);
243
244 if (clr_i) begin
-12-
245 state_d = IdleSt;
==>
246 cnt_clr = 1'b1;
247 cnt_en = 1'b0;
248 end else if (cnt_ge) begin
-13-
249 state_d = TerminalSt;
==>
250 cnt_clr = 1'b1;
251 cnt_en = 1'b0;
252 end
MISSING_ELSE
==>
253 end
254 // final, terminal state after escalation.
255 // if clr is locked down, only a system reset
256 // will get us out of this state
257 TerminalSt: begin
258 cnt_clr = 1'b1;
259 esc_state_o = Terminal;
260 if (clr_i) begin
-14-
261 state_d = IdleSt;
==>
262 end
MISSING_ELSE
==>
263 end
264 // error state, only reached if the FSM has been
265 // glitched. in this state, we trigger all escalation
266 // actions at once.
267 FsmErrorSt: begin
268 esc_state_o = FsmError;
==>
269 fsm_error = 1'b1;
270 end
271 // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272 // catch glitches.
273 default: begin
274 state_d = FsmErrorSt;
==>
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T9,T11,T12 |
IdleSt |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T21,T31,T77 |
IdleSt |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
TimeoutSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T32,T33,T49 |
TimeoutSt |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T21,T31,T77 |
TimeoutSt |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T21,T31,T77 |
Phase0St |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T34,T36,T104 |
Phase0St |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T9,T11,T12 |
Phase0St |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T9,T21,T15 |
Phase1St |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T34,T37,T38 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
Covered |
T9,T11,T12 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T9,T21,T15 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T41,T105,T71 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
Covered |
T9,T11,T12 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
Covered |
T9,T21,T15 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T43,T40,T98 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T9,T11,T12 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T9,T21,T15 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T45,T46,T32 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T9,T11,T12 |
FsmErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T7,T8 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T7,T8 |
283 if (accu_fail_i || cnt_error) begin
-1-
284 state_d = FsmErrorSt;
==>
285 fsm_error = 1'b1;
286 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T8 |
0 |
Covered |
T1,T2,T3 |
305 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer
Assertion Details
AccuFailToFsmError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
291 |
0 |
0 |
T5 |
19444 |
27 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
88 |
0 |
0 |
T8 |
0 |
41 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T57 |
0 |
55 |
0 |
0 |
T58 |
0 |
80 |
0 |
0 |
CheckAccumTrig0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
799 |
0 |
0 |
T4 |
22526 |
0 |
0 |
0 |
T5 |
19444 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T9 |
21304 |
1 |
0 |
0 |
T10 |
6357 |
0 |
0 |
0 |
T11 |
4919 |
1 |
0 |
0 |
T12 |
2856 |
1 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
1 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T46 |
0 |
2 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
CheckAccumTrig1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
39 |
0 |
0 |
T33 |
29367 |
1 |
0 |
0 |
T34 |
33710 |
0 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T37 |
0 |
2 |
0 |
0 |
T39 |
15465 |
0 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T42 |
29110 |
0 |
0 |
0 |
T49 |
17971 |
0 |
0 |
0 |
T54 |
16857 |
0 |
0 |
0 |
T55 |
67727 |
0 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T57 |
42098 |
0 |
0 |
0 |
T61 |
49675 |
0 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T72 |
0 |
1 |
0 |
0 |
T73 |
0 |
1 |
0 |
0 |
T74 |
0 |
3 |
0 |
0 |
T76 |
0 |
1 |
0 |
0 |
T79 |
54114 |
0 |
0 |
0 |
CheckClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
413 |
0 |
0 |
T8 |
42546 |
0 |
0 |
0 |
T16 |
25683 |
0 |
0 |
0 |
T17 |
5047 |
0 |
0 |
0 |
T19 |
33778 |
0 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T26 |
24466 |
0 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T34 |
0 |
6 |
0 |
0 |
T45 |
46054 |
1 |
0 |
0 |
T46 |
28765 |
1 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T54 |
0 |
1 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T59 |
20510 |
0 |
0 |
0 |
T62 |
0 |
1 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
T65 |
0 |
2 |
0 |
0 |
T82 |
0 |
1 |
0 |
0 |
CheckEn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
555884031 |
233775390 |
0 |
0 |
T1 |
2974 |
2891 |
0 |
0 |
T2 |
7562 |
7468 |
0 |
0 |
T3 |
18600 |
3389 |
0 |
0 |
T4 |
22526 |
683 |
0 |
0 |
T5 |
327 |
248 |
0 |
0 |
T9 |
21304 |
3142 |
0 |
0 |
T10 |
6357 |
4389 |
0 |
0 |
T11 |
4919 |
3086 |
0 |
0 |
T12 |
2856 |
2171 |
0 |
0 |
T18 |
1665 |
955 |
0 |
0 |
CheckPhase0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
884 |
0 |
0 |
T4 |
22526 |
0 |
0 |
0 |
T5 |
19444 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T9 |
21304 |
1 |
0 |
0 |
T10 |
6357 |
0 |
0 |
0 |
T11 |
4919 |
1 |
0 |
0 |
T12 |
2856 |
1 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
1 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T46 |
0 |
2 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
CheckPhase1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
855 |
0 |
0 |
T4 |
22526 |
0 |
0 |
0 |
T5 |
19444 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T9 |
21304 |
1 |
0 |
0 |
T10 |
6357 |
0 |
0 |
0 |
T11 |
4919 |
1 |
0 |
0 |
T12 |
2856 |
1 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
1 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T46 |
0 |
2 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
CheckPhase2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
833 |
0 |
0 |
T4 |
22526 |
0 |
0 |
0 |
T5 |
19444 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T9 |
21304 |
1 |
0 |
0 |
T10 |
6357 |
0 |
0 |
0 |
T11 |
4919 |
1 |
0 |
0 |
T12 |
2856 |
1 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
1 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T46 |
0 |
2 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
CheckPhase3_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
811 |
0 |
0 |
T4 |
22526 |
0 |
0 |
0 |
T5 |
19444 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T9 |
21304 |
1 |
0 |
0 |
T10 |
6357 |
0 |
0 |
0 |
T11 |
4919 |
1 |
0 |
0 |
T12 |
2856 |
1 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
1 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T46 |
0 |
2 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
CheckTimeout0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
474 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T19 |
33778 |
0 |
0 |
0 |
T21 |
30081 |
1 |
0 |
0 |
T31 |
32198 |
1 |
0 |
0 |
T32 |
0 |
3 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T77 |
0 |
1 |
0 |
0 |
T79 |
0 |
1 |
0 |
0 |
CheckTimeoutSt1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
64305 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T19 |
33778 |
0 |
0 |
0 |
T21 |
30081 |
72 |
0 |
0 |
T31 |
32198 |
123 |
0 |
0 |
T32 |
0 |
373 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T49 |
0 |
25 |
0 |
0 |
T55 |
0 |
75 |
0 |
0 |
T61 |
0 |
873 |
0 |
0 |
T62 |
0 |
975 |
0 |
0 |
T77 |
0 |
74 |
0 |
0 |
T79 |
0 |
178 |
0 |
0 |
T88 |
0 |
467 |
0 |
0 |
CheckTimeoutSt2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
366 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T19 |
33778 |
0 |
0 |
0 |
T21 |
30081 |
1 |
0 |
0 |
T31 |
32198 |
1 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T62 |
0 |
4 |
0 |
0 |
T77 |
0 |
1 |
0 |
0 |
T88 |
0 |
5 |
0 |
0 |
T89 |
0 |
2 |
0 |
0 |
T90 |
0 |
1 |
0 |
0 |
T94 |
0 |
1 |
0 |
0 |
CheckTimeoutStTrig_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
65 |
0 |
0 |
T32 |
31996 |
1 |
0 |
0 |
T33 |
29367 |
0 |
0 |
0 |
T34 |
33710 |
0 |
0 |
0 |
T39 |
15465 |
0 |
0 |
0 |
T42 |
29110 |
0 |
0 |
0 |
T49 |
17971 |
1 |
0 |
0 |
T54 |
16857 |
0 |
0 |
0 |
T55 |
67727 |
0 |
0 |
0 |
T57 |
42098 |
0 |
0 |
0 |
T61 |
49675 |
1 |
0 |
0 |
T69 |
0 |
2 |
0 |
0 |
T79 |
0 |
1 |
0 |
0 |
T89 |
0 |
2 |
0 |
0 |
T91 |
0 |
2 |
0 |
0 |
T94 |
0 |
1 |
0 |
0 |
T96 |
0 |
1 |
0 |
0 |
T98 |
0 |
1 |
0 |
0 |
ErrorStAllEscAsserted_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
1463 |
0 |
0 |
T5 |
19444 |
140 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
351 |
0 |
0 |
T8 |
0 |
321 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T57 |
0 |
296 |
0 |
0 |
T58 |
0 |
355 |
0 |
0 |
ErrorStIsTerminal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
1193 |
0 |
0 |
T5 |
19444 |
110 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
291 |
0 |
0 |
T8 |
0 |
261 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T57 |
0 |
236 |
0 |
0 |
T58 |
0 |
295 |
0 |
0 |
EscStateOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
555881378 |
555813301 |
0 |
0 |
T1 |
2974 |
2892 |
0 |
0 |
T2 |
7562 |
7469 |
0 |
0 |
T3 |
18600 |
18438 |
0 |
0 |
T4 |
22526 |
22391 |
0 |
0 |
T5 |
78 |
0 |
0 |
0 |
T9 |
21304 |
21225 |
0 |
0 |
T10 |
6357 |
6292 |
0 |
0 |
T11 |
4919 |
4869 |
0 |
0 |
T12 |
2856 |
2799 |
0 |
0 |
T18 |
1665 |
1594 |
0 |
0 |
T20 |
0 |
26619 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
555976364 |
0 |
0 |
T1 |
2974 |
2892 |
0 |
0 |
T2 |
7562 |
7469 |
0 |
0 |
T3 |
18600 |
18438 |
0 |
0 |
T4 |
22526 |
22391 |
0 |
0 |
T5 |
19444 |
6561 |
0 |
0 |
T9 |
21304 |
21225 |
0 |
0 |
T10 |
6357 |
6292 |
0 |
0 |
T11 |
4919 |
4869 |
0 |
0 |
T12 |
2856 |
2799 |
0 |
0 |
T18 |
1665 |
1594 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer
| Line No. | Total | Covered | Percent |
TOTAL | | 101 | 101 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
ALWAYS | 134 | 89 | 89 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
ALWAYS | 305 | 3 | 3 | 100.00 |
84 logic [EscCntDw-1:0] thresh;
85 1/1 assign cnt_ge = (esc_cnt_o >= thresh);
Tests: T1 T2 T3
86
87 //////////////
88 // Main FSM //
89 //////////////
90
91 logic [N_PHASES-1:0] phase_oh;
92
93 // SEC_CM: ESC_TIMER.FSM.SPARSE
94 // Encoding generated with:
95 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96 // -s 784905746 --language=sv
97 //
98 // Hamming distance histogram:
99 //
100 // 0: --
101 // 1: --
102 // 2: --
103 // 3: --
104 // 4: --
105 // 5: |||||||||||||||||||| (46.43%)
106 // 6: |||||||||||||||||||| (46.43%)
107 // 7: ||| (7.14%)
108 // 8: --
109 // 9: --
110 // 10: --
111 //
112 // Minimum Hamming distance: 5
113 // Maximum Hamming distance: 7
114 // Minimum Hamming weight: 3
115 // Maximum Hamming weight: 9
116 //
117 localparam int StateWidth = 10;
118 typedef enum logic [StateWidth-1:0] {
119 IdleSt = 10'b1011011010,
120 TimeoutSt = 10'b0000100110,
121 Phase0St = 10'b1110000101,
122 Phase1St = 10'b0101010100,
123 Phase2St = 10'b0000011001,
124 Phase3St = 10'b1001100001,
125 TerminalSt = 10'b1101111111,
126 FsmErrorSt = 10'b0111101000
127 } state_e;
128
129 logic fsm_error;
130 state_e state_d, state_q;
131
132 always_comb begin : p_fsm
133 // default
134 1/1 state_d = state_q;
Tests: T1 T2 T3
135 1/1 esc_state_o = Idle;
Tests: T1 T2 T3
136 1/1 cnt_en = 1'b0;
Tests: T1 T2 T3
137 1/1 cnt_clr = 1'b0;
Tests: T1 T2 T3
138 1/1 esc_trig_o = 1'b0;
Tests: T1 T2 T3
139 1/1 phase_oh = '0;
Tests: T1 T2 T3
140 1/1 thresh = timeout_cyc_i;
Tests: T1 T2 T3
141 1/1 fsm_error = 1'b0;
Tests: T1 T2 T3
142 1/1 latch_crashdump_o = 1'b0;
Tests: T1 T2 T3
143
144 1/1 unique case (state_q)
Tests: T1 T2 T3
145 // wait for an escalation trigger or an alert trigger
146 // the latter will trigger an interrupt timeout
147 IdleSt: begin
148 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T3
149 1/1 esc_state_o = Idle;
Tests: T1 T2 T3
150
151 1/1 if (accu_trig_i && en_i && !clr_i) begin
Tests: T1 T2 T3
152 1/1 state_d = Phase0St;
Tests: T18 T15 T16
153 1/1 cnt_en = 1'b1;
Tests: T18 T15 T16
154 1/1 esc_trig_o = 1'b1;
Tests: T18 T15 T16
155 // the counter is zero in this state. so if the
156 // timeout count is zero (==disabled), cnt_ge will be true.
157 1/1 end else if (timeout_en_i && !cnt_ge && en_i) begin
Tests: T1 T2 T3
158 1/1 cnt_en = 1'b1;
Tests: T19 T16 T39
159 1/1 state_d = TimeoutSt;
Tests: T19 T16 T39
160 end
MISSING_ELSE
161 end
162 // we are in interrupt timeout state
163 // in case an escalation comes in, we immediately have to
164 // switch over to the first escalation phase.
165 // in case the interrupt timeout hits it's cycle count, we
166 // also enter escalation phase0.
167 // ongoing timeouts can always be cleared.
168 TimeoutSt: begin
169 1/1 esc_state_o = Timeout;
Tests: T19 T16 T39
170
171 1/1 if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
Tests: T19 T16 T39
172 1/1 state_d = Phase0St;
Tests: T19 T39 T61
173 1/1 cnt_en = 1'b1;
Tests: T19 T39 T61
174 1/1 cnt_clr = 1'b1;
Tests: T19 T39 T61
175 1/1 esc_trig_o = 1'b1;
Tests: T19 T39 T61
176 // the timeout enable is connected to the irq state
177 // if that is cleared, stop the timeout counter
178 1/1 end else if (timeout_en_i) begin
Tests: T19 T16 T39
179 1/1 cnt_en = 1'b1;
Tests: T19 T16 T39
180 end else begin
181 1/1 state_d = IdleSt;
Tests: T16 T39 T65
182 1/1 cnt_clr = 1'b1;
Tests: T16 T39 T65
183 end
184 end
185 // note: autolocking the clear signal is done in the regfile
186 Phase0St: begin
187 1/1 cnt_en = 1'b1;
Tests: T18 T15 T19
188 1/1 phase_oh[0] = 1'b1;
Tests: T18 T15 T19
189 1/1 thresh = phase_cyc_i[0];
Tests: T18 T15 T19
190 1/1 esc_state_o = Phase0;
Tests: T18 T15 T19
191 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b00);
Tests: T18 T15 T19
192
193 1/1 if (clr_i) begin
Tests: T18 T15 T19
194 1/1 state_d = IdleSt;
Tests: T106 T107 T108
195 1/1 cnt_clr = 1'b1;
Tests: T106 T107 T108
196 1/1 cnt_en = 1'b0;
Tests: T106 T107 T108
197 1/1 end else if (cnt_ge) begin
Tests: T18 T15 T19
198 1/1 state_d = Phase1St;
Tests: T18 T15 T19
199 1/1 cnt_clr = 1'b1;
Tests: T18 T15 T19
200 1/1 cnt_en = 1'b1;
Tests: T18 T15 T19
201 end
MISSING_ELSE
202 end
203 Phase1St: begin
204 1/1 cnt_en = 1'b1;
Tests: T18 T15 T19
205 1/1 phase_oh[1] = 1'b1;
Tests: T18 T15 T19
206 1/1 thresh = phase_cyc_i[1];
Tests: T18 T15 T19
207 1/1 esc_state_o = Phase1;
Tests: T18 T15 T19
208 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b01);
Tests: T18 T15 T19
209
210 1/1 if (clr_i) begin
Tests: T18 T15 T19
211 1/1 state_d = IdleSt;
Tests: T19 T40 T109
212 1/1 cnt_clr = 1'b1;
Tests: T19 T40 T109
213 1/1 cnt_en = 1'b0;
Tests: T19 T40 T109
214 1/1 end else if (cnt_ge) begin
Tests: T18 T15 T19
215 1/1 state_d = Phase2St;
Tests: T18 T15 T19
216 1/1 cnt_clr = 1'b1;
Tests: T18 T15 T19
217 1/1 cnt_en = 1'b1;
Tests: T18 T15 T19
218 end
MISSING_ELSE
219 end
220 Phase2St: begin
221 1/1 cnt_en = 1'b1;
Tests: T18 T15 T19
222 1/1 phase_oh[2] = 1'b1;
Tests: T18 T15 T19
223 1/1 thresh = phase_cyc_i[2];
Tests: T18 T15 T19
224 1/1 esc_state_o = Phase2;
Tests: T18 T15 T19
225 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b10);
Tests: T18 T15 T19
226
227
228 1/1 if (clr_i) begin
Tests: T18 T15 T19
229 1/1 state_d = IdleSt;
Tests: T19 T98 T110
230 1/1 cnt_clr = 1'b1;
Tests: T19 T98 T110
231 1/1 cnt_en = 1'b0;
Tests: T19 T98 T110
232 1/1 end else if (cnt_ge) begin
Tests: T18 T15 T19
233 1/1 state_d = Phase3St;
Tests: T18 T15 T19
234 1/1 cnt_clr = 1'b1;
Tests: T18 T15 T19
235 end
MISSING_ELSE
236 end
237 Phase3St: begin
238 1/1 cnt_en = 1'b1;
Tests: T18 T15 T19
239 1/1 phase_oh[3] = 1'b1;
Tests: T18 T15 T19
240 1/1 thresh = phase_cyc_i[3];
Tests: T18 T15 T19
241 1/1 esc_state_o = Phase3;
Tests: T18 T15 T19
242 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b11);
Tests: T18 T15 T19
243
244 1/1 if (clr_i) begin
Tests: T18 T15 T19
245 1/1 state_d = IdleSt;
Tests: T39 T85 T111
246 1/1 cnt_clr = 1'b1;
Tests: T39 T85 T111
247 1/1 cnt_en = 1'b0;
Tests: T39 T85 T111
248 1/1 end else if (cnt_ge) begin
Tests: T18 T15 T19
249 1/1 state_d = TerminalSt;
Tests: T18 T15 T19
250 1/1 cnt_clr = 1'b1;
Tests: T18 T15 T19
251 1/1 cnt_en = 1'b0;
Tests: T18 T15 T19
252 end
MISSING_ELSE
253 end
254 // final, terminal state after escalation.
255 // if clr is locked down, only a system reset
256 // will get us out of this state
257 TerminalSt: begin
258 1/1 cnt_clr = 1'b1;
Tests: T18 T15 T19
259 1/1 esc_state_o = Terminal;
Tests: T18 T15 T19
260 1/1 if (clr_i) begin
Tests: T18 T15 T19
261 1/1 state_d = IdleSt;
Tests: T19 T55 T61
262 end
MISSING_ELSE
263 end
264 // error state, only reached if the FSM has been
265 // glitched. in this state, we trigger all escalation
266 // actions at once.
267 FsmErrorSt: begin
268 1/1 esc_state_o = FsmError;
Tests: T5 T7 T8
269 1/1 fsm_error = 1'b1;
Tests: T5 T7 T8
270 end
271 // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272 // catch glitches.
273 default: begin
274 state_d = FsmErrorSt;
275 esc_state_o = FsmError;
276 fsm_error = 1'b1;
277 end
278 endcase
279
280 // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281 // if any of the duplicate counter pairs has an inconsistent state
282 // we move into the terminal FSM error state.
283 1/1 if (accu_fail_i || cnt_error) begin
Tests: T1 T2 T3
284 1/1 state_d = FsmErrorSt;
Tests: T5 T7 T8
285 1/1 fsm_error = 1'b1;
Tests: T5 T7 T8
286 end
MISSING_ELSE
287 end
288
289 logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290 for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291 // generate configuration mask for escalation enable signals
292 4/4 assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
293 // mask reduce current phase state vector
294 // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295 4/4 assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
296 end
297
298 ///////////////////
299 // FSM Registers //
300 ///////////////////
301
302 // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303 // an alert signal, this condition is handled internally in the alert handler. The
304 // EnableAlertTriggerSVA parameter is therefore set to 0.
305 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1 `ifdef SIMULATION
305.2 prim_sparse_fsm_flop #(
305.3 .StateEnumT(state_e),
305.4 .Width($bits(state_e)),
305.5 .ResetValue($bits(state_e)'(IdleSt)),
305.6 .EnableAlertTriggerSVA(0),
305.7 .CustomForceName("state_q")
305.8 ) u_state_regs (
305.9 .clk_i ( clk_i ),
305.10 .rst_ni ( rst_ni ),
305.11 .state_i ( state_d ),
305.12 .state_o ( )
305.13 );
305.14 always_ff @(posedge clk_i or negedge rst_ni) begin
305.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
305.16 1/1 state_q <= IdleSt;
Tests: T1 T2 T3
305.17 end else begin
305.18 1/1 state_q <= state_d;
Tests: T1 T2 T3
305.19 end
305.20 end
305.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))
305.22 else begin
305.23 `ifdef UVM
305.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
305.25 "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);
305.26 `else
305.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
305.28 `PRIM_STRINGIFY(u_state_regs_A));
305.29 `endif
305.30 end
305.31 `else
305.32 prim_sparse_fsm_flop #(
305.33 .StateEnumT(state_e),
305.34 .Width($bits(state_e)),
305.35 .ResetValue($bits(state_e)'(IdleSt)),
305.36 .EnableAlertTriggerSVA(0)
305.37 ) u_state_regs (
305.38 .clk_i ( clk_i ),
305.39 .rst_ni ( rst_ni ),
305.40 .state_i ( state_d ),
305.41 .state_o ( state_q )
305.42 );
305.43 `endif
Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer
| Total | Covered | Percent |
Conditions | 45 | 42 | 93.33 |
Logical | 45 | 42 | 93.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 66
EXPRESSION (cnt_clr && ((!cnt_en)))
---1--- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T18,T15,T19 |
1 | 1 | Covered | T1,T2,T3 |
LINE 66
EXPRESSION (cnt_clr && cnt_en)
---1--- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T15,T19,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T18,T15,T19 |
LINE 151
EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T18,T10,T11 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T18,T15,T16 |
LINE 157
EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
------1----- -----2----- --3-
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T19,T16,T47 |
1 | 0 | 1 | Covered | T18,T20,T14 |
1 | 1 | 0 | Covered | T1,T48,T47 |
1 | 1 | 1 | Covered | T19,T16,T39 |
LINE 171
EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
-----------------1----------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T19,T16,T39 |
0 | 1 | Covered | T19,T61,T83 |
1 | 0 | Covered | T39,T91,T37 |
LINE 171
SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T19,T16,T39 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T39,T91,T37 |
LINE 171
SUB-EXPRESSION (cnt_ge && timeout_en_i)
---1-- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T19,T16,T39 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T19,T61,T83 |
LINE 191
EXPRESSION (crashdump_phase_i == 2'b0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T15,T16,T47 |
1 | Covered | T18,T19,T39 |
LINE 208
EXPRESSION (crashdump_phase_i == 2'b1)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T18,T15,T19 |
1 | Covered | T47,T83,T67 |
LINE 225
EXPRESSION (crashdump_phase_i == 2'b10)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T18,T19,T47 |
1 | Covered | T15,T16,T55 |
LINE 242
EXPRESSION (crashdump_phase_i == 2'b11)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T18,T15,T19 |
1 | Covered | T86,T90,T93 |
LINE 283
EXPRESSION (accu_fail_i || cnt_error)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T5,T7,T8 |
LINE 295
EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T18,T19,T55 |
LINE 295
EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T18,T16,T55 |
LINE 295
EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T18,T19,T16 |
LINE 295
EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T18,T15,T16 |
FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
8 |
8 |
100.00 |
(Not included in score) |
Transitions |
14 |
14 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
FsmErrorSt |
284 |
Covered |
T5,T7,T8 |
IdleSt |
181 |
Covered |
T1,T2,T3 |
Phase0St |
152 |
Covered |
T18,T15,T19 |
Phase1St |
198 |
Covered |
T18,T15,T19 |
Phase2St |
215 |
Covered |
T18,T15,T19 |
Phase3St |
233 |
Covered |
T18,T15,T19 |
TerminalSt |
249 |
Covered |
T18,T15,T19 |
TimeoutSt |
159 |
Covered |
T19,T16,T39 |
transitions | Line No. | Covered | Tests | Exclude Annotation |
IdleSt->FsmErrorSt |
284 |
Covered |
T5,T7,T8 |
|
IdleSt->Phase0St |
152 |
Covered |
T18,T15,T16 |
|
IdleSt->TimeoutSt |
159 |
Covered |
T19,T16,T39 |
|
Phase0St->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase0St->IdleSt |
194 |
Covered |
T44,T85,T106 |
|
Phase0St->Phase1St |
198 |
Covered |
T18,T15,T19 |
|
Phase1St->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase1St->IdleSt |
211 |
Covered |
T19,T40,T37 |
|
Phase1St->Phase2St |
215 |
Covered |
T18,T15,T19 |
|
Phase2St->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase2St->IdleSt |
229 |
Covered |
T19,T98,T100 |
|
Phase2St->Phase3St |
233 |
Covered |
T18,T15,T19 |
|
Phase3St->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase3St->IdleSt |
245 |
Covered |
T39,T85,T111 |
|
Phase3St->TerminalSt |
249 |
Covered |
T18,T15,T19 |
|
TerminalSt->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
TerminalSt->IdleSt |
261 |
Covered |
T19,T55,T61 |
|
TimeoutSt->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
TimeoutSt->IdleSt |
181 |
Covered |
T16,T39,T65 |
|
TimeoutSt->Phase0St |
172 |
Covered |
T19,T39,T61 |
|
Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer
| Line No. | Total | Covered | Percent |
Branches |
|
26 |
26 |
100.00 |
CASE |
144 |
22 |
22 |
100.00 |
IF |
283 |
2 |
2 |
100.00 |
IF |
305 |
2 |
2 |
100.00 |
144 unique case (state_q)
-1-
145 // wait for an escalation trigger or an alert trigger
146 // the latter will trigger an interrupt timeout
147 IdleSt: begin
148 cnt_clr = 1'b1;
149 esc_state_o = Idle;
150
151 if (accu_trig_i && en_i && !clr_i) begin
-2-
152 state_d = Phase0St;
==>
153 cnt_en = 1'b1;
154 esc_trig_o = 1'b1;
155 // the counter is zero in this state. so if the
156 // timeout count is zero (==disabled), cnt_ge will be true.
157 end else if (timeout_en_i && !cnt_ge && en_i) begin
-3-
158 cnt_en = 1'b1;
==>
159 state_d = TimeoutSt;
160 end
MISSING_ELSE
==>
161 end
162 // we are in interrupt timeout state
163 // in case an escalation comes in, we immediately have to
164 // switch over to the first escalation phase.
165 // in case the interrupt timeout hits it's cycle count, we
166 // also enter escalation phase0.
167 // ongoing timeouts can always be cleared.
168 TimeoutSt: begin
169 esc_state_o = Timeout;
170
171 if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
-4-
172 state_d = Phase0St;
==>
173 cnt_en = 1'b1;
174 cnt_clr = 1'b1;
175 esc_trig_o = 1'b1;
176 // the timeout enable is connected to the irq state
177 // if that is cleared, stop the timeout counter
178 end else if (timeout_en_i) begin
-5-
179 cnt_en = 1'b1;
==>
180 end else begin
181 state_d = IdleSt;
==>
182 cnt_clr = 1'b1;
183 end
184 end
185 // note: autolocking the clear signal is done in the regfile
186 Phase0St: begin
187 cnt_en = 1'b1;
188 phase_oh[0] = 1'b1;
189 thresh = phase_cyc_i[0];
190 esc_state_o = Phase0;
191 latch_crashdump_o = (crashdump_phase_i == 2'b00);
192
193 if (clr_i) begin
-6-
194 state_d = IdleSt;
==>
195 cnt_clr = 1'b1;
196 cnt_en = 1'b0;
197 end else if (cnt_ge) begin
-7-
198 state_d = Phase1St;
==>
199 cnt_clr = 1'b1;
200 cnt_en = 1'b1;
201 end
MISSING_ELSE
==>
202 end
203 Phase1St: begin
204 cnt_en = 1'b1;
205 phase_oh[1] = 1'b1;
206 thresh = phase_cyc_i[1];
207 esc_state_o = Phase1;
208 latch_crashdump_o = (crashdump_phase_i == 2'b01);
209
210 if (clr_i) begin
-8-
211 state_d = IdleSt;
==>
212 cnt_clr = 1'b1;
213 cnt_en = 1'b0;
214 end else if (cnt_ge) begin
-9-
215 state_d = Phase2St;
==>
216 cnt_clr = 1'b1;
217 cnt_en = 1'b1;
218 end
MISSING_ELSE
==>
219 end
220 Phase2St: begin
221 cnt_en = 1'b1;
222 phase_oh[2] = 1'b1;
223 thresh = phase_cyc_i[2];
224 esc_state_o = Phase2;
225 latch_crashdump_o = (crashdump_phase_i == 2'b10);
226
227
228 if (clr_i) begin
-10-
229 state_d = IdleSt;
==>
230 cnt_clr = 1'b1;
231 cnt_en = 1'b0;
232 end else if (cnt_ge) begin
-11-
233 state_d = Phase3St;
==>
234 cnt_clr = 1'b1;
235 end
MISSING_ELSE
==>
236 end
237 Phase3St: begin
238 cnt_en = 1'b1;
239 phase_oh[3] = 1'b1;
240 thresh = phase_cyc_i[3];
241 esc_state_o = Phase3;
242 latch_crashdump_o = (crashdump_phase_i == 2'b11);
243
244 if (clr_i) begin
-12-
245 state_d = IdleSt;
==>
246 cnt_clr = 1'b1;
247 cnt_en = 1'b0;
248 end else if (cnt_ge) begin
-13-
249 state_d = TerminalSt;
==>
250 cnt_clr = 1'b1;
251 cnt_en = 1'b0;
252 end
MISSING_ELSE
==>
253 end
254 // final, terminal state after escalation.
255 // if clr is locked down, only a system reset
256 // will get us out of this state
257 TerminalSt: begin
258 cnt_clr = 1'b1;
259 esc_state_o = Terminal;
260 if (clr_i) begin
-14-
261 state_d = IdleSt;
==>
262 end
MISSING_ELSE
==>
263 end
264 // error state, only reached if the FSM has been
265 // glitched. in this state, we trigger all escalation
266 // actions at once.
267 FsmErrorSt: begin
268 esc_state_o = FsmError;
==>
269 fsm_error = 1'b1;
270 end
271 // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272 // catch glitches.
273 default: begin
274 state_d = FsmErrorSt;
==>
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T15,T16 |
IdleSt |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T19,T16,T39 |
IdleSt |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
TimeoutSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T19,T39,T61 |
TimeoutSt |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T19,T16,T39 |
TimeoutSt |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T16,T39,T65 |
Phase0St |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T106,T107,T108 |
Phase0St |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T15,T19 |
Phase0St |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T15,T19,T16 |
Phase1St |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T19,T40,T109 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
Covered |
T18,T15,T19 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T15,T19,T16 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T19,T98,T110 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
Covered |
T18,T15,T19 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
Covered |
T15,T19,T16 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T39,T85,T111 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T18,T15,T19 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T15,T19,T16 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T19,T55,T61 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T18,T15,T19 |
FsmErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T7,T8 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T7,T8 |
283 if (accu_fail_i || cnt_error) begin
-1-
284 state_d = FsmErrorSt;
==>
285 fsm_error = 1'b1;
286 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T8 |
0 |
Covered |
T1,T2,T3 |
305 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer
Assertion Details
AccuFailToFsmError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
229 |
0 |
0 |
T5 |
19444 |
32 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
33 |
0 |
0 |
T8 |
0 |
47 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T57 |
0 |
73 |
0 |
0 |
T58 |
0 |
44 |
0 |
0 |
CheckAccumTrig0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
436 |
0 |
0 |
T4 |
22526 |
0 |
0 |
0 |
T5 |
19444 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T9 |
21304 |
0 |
0 |
0 |
T10 |
6357 |
0 |
0 |
0 |
T11 |
4919 |
0 |
0 |
0 |
T12 |
2856 |
0 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T18 |
1665 |
1 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T86 |
0 |
1 |
0 |
0 |
CheckAccumTrig1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
20 |
0 |
0 |
T37 |
0 |
1 |
0 |
0 |
T39 |
15465 |
1 |
0 |
0 |
T42 |
29110 |
0 |
0 |
0 |
T49 |
17971 |
0 |
0 |
0 |
T57 |
42098 |
0 |
0 |
0 |
T61 |
49675 |
0 |
0 |
0 |
T62 |
99275 |
0 |
0 |
0 |
T65 |
98827 |
0 |
0 |
0 |
T79 |
54114 |
0 |
0 |
0 |
T86 |
24272 |
0 |
0 |
0 |
T87 |
984 |
0 |
0 |
0 |
T91 |
0 |
1 |
0 |
0 |
T98 |
0 |
1 |
0 |
0 |
T99 |
0 |
1 |
0 |
0 |
T107 |
0 |
1 |
0 |
0 |
T112 |
0 |
1 |
0 |
0 |
T113 |
0 |
1 |
0 |
0 |
T114 |
0 |
3 |
0 |
0 |
T115 |
0 |
1 |
0 |
0 |
CheckClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
182 |
0 |
0 |
T8 |
42546 |
0 |
0 |
0 |
T16 |
25683 |
0 |
0 |
0 |
T17 |
5047 |
0 |
0 |
0 |
T19 |
33778 |
3 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T26 |
24466 |
0 |
0 |
0 |
T37 |
0 |
5 |
0 |
0 |
T39 |
0 |
1 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T44 |
0 |
2 |
0 |
0 |
T46 |
28765 |
0 |
0 |
0 |
T47 |
15520 |
0 |
0 |
0 |
T53 |
69336 |
0 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T59 |
20510 |
0 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T90 |
0 |
1 |
0 |
0 |
CheckEn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
555884031 |
269562556 |
0 |
0 |
T1 |
2974 |
2891 |
0 |
0 |
T2 |
7562 |
7468 |
0 |
0 |
T3 |
18600 |
18436 |
0 |
0 |
T4 |
22526 |
695 |
0 |
0 |
T5 |
327 |
248 |
0 |
0 |
T9 |
21304 |
21224 |
0 |
0 |
T10 |
6357 |
4463 |
0 |
0 |
T11 |
4919 |
3148 |
0 |
0 |
T12 |
2856 |
2200 |
0 |
0 |
T18 |
1665 |
967 |
0 |
0 |
CheckPhase0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
498 |
0 |
0 |
T4 |
22526 |
0 |
0 |
0 |
T5 |
19444 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T9 |
21304 |
0 |
0 |
0 |
T10 |
6357 |
0 |
0 |
0 |
T11 |
4919 |
0 |
0 |
0 |
T12 |
2856 |
0 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T18 |
1665 |
1 |
0 |
0 |
T19 |
0 |
3 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T39 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T61 |
0 |
2 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
CheckPhase1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
482 |
0 |
0 |
T4 |
22526 |
0 |
0 |
0 |
T5 |
19444 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T9 |
21304 |
0 |
0 |
0 |
T10 |
6357 |
0 |
0 |
0 |
T11 |
4919 |
0 |
0 |
0 |
T12 |
2856 |
0 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T18 |
1665 |
1 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T39 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T61 |
0 |
2 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
CheckPhase2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
473 |
0 |
0 |
T4 |
22526 |
0 |
0 |
0 |
T5 |
19444 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T9 |
21304 |
0 |
0 |
0 |
T10 |
6357 |
0 |
0 |
0 |
T11 |
4919 |
0 |
0 |
0 |
T12 |
2856 |
0 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T18 |
1665 |
1 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T39 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T61 |
0 |
2 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
CheckPhase3_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
464 |
0 |
0 |
T4 |
22526 |
0 |
0 |
0 |
T5 |
19444 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T9 |
21304 |
0 |
0 |
0 |
T10 |
6357 |
0 |
0 |
0 |
T11 |
4919 |
0 |
0 |
0 |
T12 |
2856 |
0 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T18 |
1665 |
1 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T61 |
0 |
2 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T86 |
0 |
1 |
0 |
0 |
CheckTimeout0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
487 |
0 |
0 |
T8 |
42546 |
0 |
0 |
0 |
T16 |
25683 |
2 |
0 |
0 |
T17 |
5047 |
0 |
0 |
0 |
T19 |
33778 |
3 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T26 |
24466 |
0 |
0 |
0 |
T39 |
0 |
2 |
0 |
0 |
T46 |
28765 |
0 |
0 |
0 |
T47 |
15520 |
0 |
0 |
0 |
T53 |
69336 |
0 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T59 |
20510 |
0 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T66 |
0 |
3 |
0 |
0 |
T83 |
0 |
1 |
0 |
0 |
T89 |
0 |
2 |
0 |
0 |
T93 |
0 |
1 |
0 |
0 |
CheckTimeoutSt1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
65719 |
0 |
0 |
T8 |
42546 |
0 |
0 |
0 |
T16 |
25683 |
129 |
0 |
0 |
T17 |
5047 |
0 |
0 |
0 |
T19 |
33778 |
366 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T26 |
24466 |
0 |
0 |
0 |
T39 |
0 |
58 |
0 |
0 |
T46 |
28765 |
0 |
0 |
0 |
T47 |
15520 |
0 |
0 |
0 |
T53 |
69336 |
0 |
0 |
0 |
T56 |
0 |
53 |
0 |
0 |
T59 |
20510 |
0 |
0 |
0 |
T61 |
0 |
63 |
0 |
0 |
T65 |
0 |
367 |
0 |
0 |
T66 |
0 |
313 |
0 |
0 |
T83 |
0 |
25 |
0 |
0 |
T89 |
0 |
224 |
0 |
0 |
T93 |
0 |
163 |
0 |
0 |
CheckTimeoutSt2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
409 |
0 |
0 |
T8 |
42546 |
0 |
0 |
0 |
T16 |
25683 |
2 |
0 |
0 |
T17 |
5047 |
0 |
0 |
0 |
T26 |
24466 |
0 |
0 |
0 |
T39 |
0 |
1 |
0 |
0 |
T44 |
0 |
2 |
0 |
0 |
T47 |
15520 |
0 |
0 |
0 |
T53 |
69336 |
0 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T59 |
20510 |
0 |
0 |
0 |
T60 |
1256 |
0 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T66 |
0 |
3 |
0 |
0 |
T77 |
10813 |
0 |
0 |
0 |
T78 |
5395 |
0 |
0 |
0 |
T89 |
0 |
2 |
0 |
0 |
T91 |
0 |
2 |
0 |
0 |
T95 |
0 |
1 |
0 |
0 |
T116 |
0 |
2 |
0 |
0 |
CheckTimeoutStTrig_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
55 |
0 |
0 |
T8 |
42546 |
0 |
0 |
0 |
T16 |
25683 |
0 |
0 |
0 |
T17 |
5047 |
0 |
0 |
0 |
T19 |
33778 |
3 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T26 |
24466 |
0 |
0 |
0 |
T37 |
0 |
1 |
0 |
0 |
T46 |
28765 |
0 |
0 |
0 |
T47 |
15520 |
0 |
0 |
0 |
T53 |
69336 |
0 |
0 |
0 |
T59 |
20510 |
0 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T69 |
0 |
2 |
0 |
0 |
T83 |
0 |
1 |
0 |
0 |
T93 |
0 |
1 |
0 |
0 |
T97 |
0 |
1 |
0 |
0 |
T98 |
0 |
1 |
0 |
0 |
T117 |
0 |
1 |
0 |
0 |
T118 |
0 |
2 |
0 |
0 |
ErrorStAllEscAsserted_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
1480 |
0 |
0 |
T5 |
19444 |
164 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
301 |
0 |
0 |
T8 |
0 |
335 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T57 |
0 |
358 |
0 |
0 |
T58 |
0 |
322 |
0 |
0 |
ErrorStIsTerminal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
1210 |
0 |
0 |
T5 |
19444 |
134 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
241 |
0 |
0 |
T8 |
0 |
275 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T57 |
0 |
298 |
0 |
0 |
T58 |
0 |
262 |
0 |
0 |
EscStateOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
555881378 |
555813301 |
0 |
0 |
T1 |
2974 |
2892 |
0 |
0 |
T2 |
7562 |
7469 |
0 |
0 |
T3 |
18600 |
18438 |
0 |
0 |
T4 |
22526 |
22391 |
0 |
0 |
T5 |
78 |
0 |
0 |
0 |
T9 |
21304 |
21225 |
0 |
0 |
T10 |
6357 |
6292 |
0 |
0 |
T11 |
4919 |
4869 |
0 |
0 |
T12 |
2856 |
2799 |
0 |
0 |
T18 |
1665 |
1594 |
0 |
0 |
T20 |
0 |
26619 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
555976364 |
0 |
0 |
T1 |
2974 |
2892 |
0 |
0 |
T2 |
7562 |
7469 |
0 |
0 |
T3 |
18600 |
18438 |
0 |
0 |
T4 |
22526 |
22391 |
0 |
0 |
T5 |
19444 |
6561 |
0 |
0 |
T9 |
21304 |
21225 |
0 |
0 |
T10 |
6357 |
6292 |
0 |
0 |
T11 |
4919 |
4869 |
0 |
0 |
T12 |
2856 |
2799 |
0 |
0 |
T18 |
1665 |
1594 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer
| Line No. | Total | Covered | Percent |
TOTAL | | 101 | 101 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
ALWAYS | 134 | 89 | 89 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
ALWAYS | 305 | 3 | 3 | 100.00 |
84 logic [EscCntDw-1:0] thresh;
85 1/1 assign cnt_ge = (esc_cnt_o >= thresh);
Tests: T1 T2 T3
86
87 //////////////
88 // Main FSM //
89 //////////////
90
91 logic [N_PHASES-1:0] phase_oh;
92
93 // SEC_CM: ESC_TIMER.FSM.SPARSE
94 // Encoding generated with:
95 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96 // -s 784905746 --language=sv
97 //
98 // Hamming distance histogram:
99 //
100 // 0: --
101 // 1: --
102 // 2: --
103 // 3: --
104 // 4: --
105 // 5: |||||||||||||||||||| (46.43%)
106 // 6: |||||||||||||||||||| (46.43%)
107 // 7: ||| (7.14%)
108 // 8: --
109 // 9: --
110 // 10: --
111 //
112 // Minimum Hamming distance: 5
113 // Maximum Hamming distance: 7
114 // Minimum Hamming weight: 3
115 // Maximum Hamming weight: 9
116 //
117 localparam int StateWidth = 10;
118 typedef enum logic [StateWidth-1:0] {
119 IdleSt = 10'b1011011010,
120 TimeoutSt = 10'b0000100110,
121 Phase0St = 10'b1110000101,
122 Phase1St = 10'b0101010100,
123 Phase2St = 10'b0000011001,
124 Phase3St = 10'b1001100001,
125 TerminalSt = 10'b1101111111,
126 FsmErrorSt = 10'b0111101000
127 } state_e;
128
129 logic fsm_error;
130 state_e state_d, state_q;
131
132 always_comb begin : p_fsm
133 // default
134 1/1 state_d = state_q;
Tests: T1 T2 T3
135 1/1 esc_state_o = Idle;
Tests: T1 T2 T3
136 1/1 cnt_en = 1'b0;
Tests: T1 T2 T3
137 1/1 cnt_clr = 1'b0;
Tests: T1 T2 T3
138 1/1 esc_trig_o = 1'b0;
Tests: T1 T2 T3
139 1/1 phase_oh = '0;
Tests: T1 T2 T3
140 1/1 thresh = timeout_cyc_i;
Tests: T1 T2 T3
141 1/1 fsm_error = 1'b0;
Tests: T1 T2 T3
142 1/1 latch_crashdump_o = 1'b0;
Tests: T1 T2 T3
143
144 1/1 unique case (state_q)
Tests: T1 T2 T3
145 // wait for an escalation trigger or an alert trigger
146 // the latter will trigger an interrupt timeout
147 IdleSt: begin
148 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T3
149 1/1 esc_state_o = Idle;
Tests: T1 T2 T3
150
151 1/1 if (accu_trig_i && en_i && !clr_i) begin
Tests: T1 T2 T3
152 1/1 state_d = Phase0St;
Tests: T3 T4 T13
153 1/1 cnt_en = 1'b1;
Tests: T3 T4 T13
154 1/1 esc_trig_o = 1'b1;
Tests: T3 T4 T13
155 // the counter is zero in this state. so if the
156 // timeout count is zero (==disabled), cnt_ge will be true.
157 1/1 end else if (timeout_en_i && !cnt_ge && en_i) begin
Tests: T1 T2 T3
158 1/1 cnt_en = 1'b1;
Tests: T19 T16 T17
159 1/1 state_d = TimeoutSt;
Tests: T19 T16 T17
160 end
MISSING_ELSE
161 end
162 // we are in interrupt timeout state
163 // in case an escalation comes in, we immediately have to
164 // switch over to the first escalation phase.
165 // in case the interrupt timeout hits it's cycle count, we
166 // also enter escalation phase0.
167 // ongoing timeouts can always be cleared.
168 TimeoutSt: begin
169 1/1 esc_state_o = Timeout;
Tests: T19 T16 T17
170
171 1/1 if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
Tests: T19 T16 T17
172 1/1 state_d = Phase0St;
Tests: T17 T39 T42
173 1/1 cnt_en = 1'b1;
Tests: T17 T39 T42
174 1/1 cnt_clr = 1'b1;
Tests: T17 T39 T42
175 1/1 esc_trig_o = 1'b1;
Tests: T17 T39 T42
176 // the timeout enable is connected to the irq state
177 // if that is cleared, stop the timeout counter
178 1/1 end else if (timeout_en_i) begin
Tests: T19 T16 T17
179 1/1 cnt_en = 1'b1;
Tests: T19 T16 T17
180 end else begin
181 1/1 state_d = IdleSt;
Tests: T19 T16 T39
182 1/1 cnt_clr = 1'b1;
Tests: T19 T16 T39
183 end
184 end
185 // note: autolocking the clear signal is done in the regfile
186 Phase0St: begin
187 1/1 cnt_en = 1'b1;
Tests: T13 T14 T15
188 1/1 phase_oh[0] = 1'b1;
Tests: T13 T14 T15
189 1/1 thresh = phase_cyc_i[0];
Tests: T13 T14 T15
190 1/1 esc_state_o = Phase0;
Tests: T13 T14 T15
191 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b00);
Tests: T13 T14 T15
192
193 1/1 if (clr_i) begin
Tests: T13 T14 T15
194 1/1 state_d = IdleSt;
Tests: T119 T120 T121
195 1/1 cnt_clr = 1'b1;
Tests: T119 T120 T121
196 1/1 cnt_en = 1'b0;
Tests: T119 T120 T121
197 1/1 end else if (cnt_ge) begin
Tests: T13 T14 T15
198 1/1 state_d = Phase1St;
Tests: T13 T14 T15
199 1/1 cnt_clr = 1'b1;
Tests: T13 T14 T15
200 1/1 cnt_en = 1'b1;
Tests: T13 T14 T15
201 end
MISSING_ELSE
202 end
203 Phase1St: begin
204 1/1 cnt_en = 1'b1;
Tests: T13 T14 T15
205 1/1 phase_oh[1] = 1'b1;
Tests: T13 T14 T15
206 1/1 thresh = phase_cyc_i[1];
Tests: T13 T14 T15
207 1/1 esc_state_o = Phase1;
Tests: T13 T14 T15
208 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b01);
Tests: T13 T14 T15
209
210 1/1 if (clr_i) begin
Tests: T13 T14 T15
211 1/1 state_d = IdleSt;
Tests: T122 T70 T123
212 1/1 cnt_clr = 1'b1;
Tests: T122 T70 T123
213 1/1 cnt_en = 1'b0;
Tests: T122 T70 T123
214 1/1 end else if (cnt_ge) begin
Tests: T13 T14 T15
215 1/1 state_d = Phase2St;
Tests: T13 T14 T15
216 1/1 cnt_clr = 1'b1;
Tests: T13 T14 T15
217 1/1 cnt_en = 1'b1;
Tests: T13 T14 T15
218 end
MISSING_ELSE
219 end
220 Phase2St: begin
221 1/1 cnt_en = 1'b1;
Tests: T13 T14 T15
222 1/1 phase_oh[2] = 1'b1;
Tests: T13 T14 T15
223 1/1 thresh = phase_cyc_i[2];
Tests: T13 T14 T15
224 1/1 esc_state_o = Phase2;
Tests: T13 T14 T15
225 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b10);
Tests: T13 T14 T15
226
227
228 1/1 if (clr_i) begin
Tests: T13 T14 T15
229 1/1 state_d = IdleSt;
Tests: T39 T41 T124
230 1/1 cnt_clr = 1'b1;
Tests: T39 T41 T124
231 1/1 cnt_en = 1'b0;
Tests: T39 T41 T124
232 1/1 end else if (cnt_ge) begin
Tests: T13 T14 T15
233 1/1 state_d = Phase3St;
Tests: T13 T14 T15
234 1/1 cnt_clr = 1'b1;
Tests: T13 T14 T15
235 end
MISSING_ELSE
236 end
237 Phase3St: begin
238 1/1 cnt_en = 1'b1;
Tests: T13 T14 T15
239 1/1 phase_oh[3] = 1'b1;
Tests: T13 T14 T15
240 1/1 thresh = phase_cyc_i[3];
Tests: T13 T14 T15
241 1/1 esc_state_o = Phase3;
Tests: T13 T14 T15
242 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b11);
Tests: T13 T14 T15
243
244 1/1 if (clr_i) begin
Tests: T13 T14 T15
245 1/1 state_d = IdleSt;
Tests: T125 T126
246 1/1 cnt_clr = 1'b1;
Tests: T125 T126
247 1/1 cnt_en = 1'b0;
Tests: T125 T126
248 1/1 end else if (cnt_ge) begin
Tests: T13 T14 T15
249 1/1 state_d = TerminalSt;
Tests: T13 T14 T15
250 1/1 cnt_clr = 1'b1;
Tests: T13 T14 T15
251 1/1 cnt_en = 1'b0;
Tests: T13 T14 T15
252 end
MISSING_ELSE
253 end
254 // final, terminal state after escalation.
255 // if clr is locked down, only a system reset
256 // will get us out of this state
257 TerminalSt: begin
258 1/1 cnt_clr = 1'b1;
Tests: T13 T14 T15
259 1/1 esc_state_o = Terminal;
Tests: T13 T14 T15
260 1/1 if (clr_i) begin
Tests: T13 T14 T15
261 1/1 state_d = IdleSt;
Tests: T62 T63 T83
262 end
MISSING_ELSE
263 end
264 // error state, only reached if the FSM has been
265 // glitched. in this state, we trigger all escalation
266 // actions at once.
267 FsmErrorSt: begin
268 1/1 esc_state_o = FsmError;
Tests: T5 T7 T8
269 1/1 fsm_error = 1'b1;
Tests: T5 T7 T8
270 end
271 // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272 // catch glitches.
273 default: begin
274 state_d = FsmErrorSt;
275 esc_state_o = FsmError;
276 fsm_error = 1'b1;
277 end
278 endcase
279
280 // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281 // if any of the duplicate counter pairs has an inconsistent state
282 // we move into the terminal FSM error state.
283 1/1 if (accu_fail_i || cnt_error) begin
Tests: T1 T2 T3
284 1/1 state_d = FsmErrorSt;
Tests: T5 T7 T8
285 1/1 fsm_error = 1'b1;
Tests: T5 T7 T8
286 end
MISSING_ELSE
287 end
288
289 logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290 for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291 // generate configuration mask for escalation enable signals
292 4/4 assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
293 // mask reduce current phase state vector
294 // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295 4/4 assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
296 end
297
298 ///////////////////
299 // FSM Registers //
300 ///////////////////
301
302 // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303 // an alert signal, this condition is handled internally in the alert handler. The
304 // EnableAlertTriggerSVA parameter is therefore set to 0.
305 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1 `ifdef SIMULATION
305.2 prim_sparse_fsm_flop #(
305.3 .StateEnumT(state_e),
305.4 .Width($bits(state_e)),
305.5 .ResetValue($bits(state_e)'(IdleSt)),
305.6 .EnableAlertTriggerSVA(0),
305.7 .CustomForceName("state_q")
305.8 ) u_state_regs (
305.9 .clk_i ( clk_i ),
305.10 .rst_ni ( rst_ni ),
305.11 .state_i ( state_d ),
305.12 .state_o ( )
305.13 );
305.14 always_ff @(posedge clk_i or negedge rst_ni) begin
305.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
305.16 1/1 state_q <= IdleSt;
Tests: T1 T2 T3
305.17 end else begin
305.18 1/1 state_q <= state_d;
Tests: T1 T2 T3
305.19 end
305.20 end
305.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))
305.22 else begin
305.23 `ifdef UVM
305.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
305.25 "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);
305.26 `else
305.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
305.28 `PRIM_STRINGIFY(u_state_regs_A));
305.29 `endif
305.30 end
305.31 `else
305.32 prim_sparse_fsm_flop #(
305.33 .StateEnumT(state_e),
305.34 .Width($bits(state_e)),
305.35 .ResetValue($bits(state_e)'(IdleSt)),
305.36 .EnableAlertTriggerSVA(0)
305.37 ) u_state_regs (
305.38 .clk_i ( clk_i ),
305.39 .rst_ni ( rst_ni ),
305.40 .state_i ( state_d ),
305.41 .state_o ( state_q )
305.42 );
305.43 `endif
Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer
| Total | Covered | Percent |
Conditions | 45 | 43 | 95.56 |
Logical | 45 | 43 | 95.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 66
EXPRESSION (cnt_clr && ((!cnt_en)))
---1--- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T3,T4,T13 |
1 | 1 | Covered | T1,T2,T3 |
LINE 66
EXPRESSION (cnt_clr && cnt_en)
---1--- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T13 |
LINE 151
EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T1,T3,T18 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T13 |
LINE 157
EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
------1----- -----2----- --3-
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T21,T15 |
1 | 0 | 1 | Covered | T20,T13,T15 |
1 | 1 | 0 | Covered | T15,T48,T19 |
1 | 1 | 1 | Covered | T19,T16,T17 |
LINE 171
EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
-----------------1----------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T19,T16,T17 |
0 | 1 | Covered | T83,T67,T95 |
1 | 0 | Covered | T17,T39,T42 |
LINE 171
SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T19,T16,T17 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T17,T39,T42 |
LINE 171
SUB-EXPRESSION (cnt_ge && timeout_en_i)
---1-- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T19,T16,T17 |
1 | 0 | Covered | T50,T52 |
1 | 1 | Covered | T83,T67,T95 |
LINE 191
EXPRESSION (crashdump_phase_i == 2'b0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T15,T16,T17 |
1 | Covered | T13,T14,T67 |
LINE 208
EXPRESSION (crashdump_phase_i == 2'b1)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T13,T14,T15 |
1 | Covered | T53,T42,T62 |
LINE 225
EXPRESSION (crashdump_phase_i == 2'b10)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T13,T14,T16 |
1 | Covered | T15,T17,T39 |
LINE 242
EXPRESSION (crashdump_phase_i == 2'b11)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T13,T14,T15 |
1 | Covered | T16,T39,T90 |
LINE 283
EXPRESSION (accu_fail_i || cnt_error)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T5,T7,T8 |
LINE 295
EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T13,T17,T53 |
LINE 295
EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T13,T14,T15 |
LINE 295
EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T13,T14,T15 |
LINE 295
EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T13,T14,T17 |
FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
8 |
8 |
100.00 |
(Not included in score) |
Transitions |
14 |
14 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
FsmErrorSt |
284 |
Covered |
T5,T7,T8 |
IdleSt |
181 |
Covered |
T1,T2,T3 |
Phase0St |
152 |
Covered |
T13,T14,T15 |
Phase1St |
198 |
Covered |
T13,T14,T15 |
Phase2St |
215 |
Covered |
T13,T14,T15 |
Phase3St |
233 |
Covered |
T13,T14,T15 |
TerminalSt |
249 |
Covered |
T13,T14,T15 |
TimeoutSt |
159 |
Covered |
T19,T16,T17 |
transitions | Line No. | Covered | Tests | Exclude Annotation |
IdleSt->FsmErrorSt |
284 |
Covered |
T5,T7,T8 |
|
IdleSt->Phase0St |
152 |
Covered |
T13,T14,T15 |
|
IdleSt->TimeoutSt |
159 |
Covered |
T19,T16,T17 |
|
Phase0St->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase0St->IdleSt |
194 |
Covered |
T100,T119,T120 |
|
Phase0St->Phase1St |
198 |
Covered |
T13,T14,T15 |
|
Phase1St->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase1St->IdleSt |
211 |
Covered |
T56,T122,T70 |
|
Phase1St->Phase2St |
215 |
Covered |
T13,T14,T15 |
|
Phase2St->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase2St->IdleSt |
229 |
Covered |
T39,T56,T41 |
|
Phase2St->Phase3St |
233 |
Covered |
T13,T14,T15 |
|
Phase3St->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase3St->IdleSt |
245 |
Covered |
T125,T126 |
|
Phase3St->TerminalSt |
249 |
Covered |
T13,T14,T15 |
|
TerminalSt->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
TerminalSt->IdleSt |
261 |
Covered |
T62,T63,T83 |
|
TimeoutSt->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
TimeoutSt->IdleSt |
181 |
Covered |
T19,T16,T39 |
|
TimeoutSt->Phase0St |
172 |
Covered |
T17,T39,T42 |
|
Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer
| Line No. | Total | Covered | Percent |
Branches |
|
26 |
26 |
100.00 |
CASE |
144 |
22 |
22 |
100.00 |
IF |
283 |
2 |
2 |
100.00 |
IF |
305 |
2 |
2 |
100.00 |
144 unique case (state_q)
-1-
145 // wait for an escalation trigger or an alert trigger
146 // the latter will trigger an interrupt timeout
147 IdleSt: begin
148 cnt_clr = 1'b1;
149 esc_state_o = Idle;
150
151 if (accu_trig_i && en_i && !clr_i) begin
-2-
152 state_d = Phase0St;
==>
153 cnt_en = 1'b1;
154 esc_trig_o = 1'b1;
155 // the counter is zero in this state. so if the
156 // timeout count is zero (==disabled), cnt_ge will be true.
157 end else if (timeout_en_i && !cnt_ge && en_i) begin
-3-
158 cnt_en = 1'b1;
==>
159 state_d = TimeoutSt;
160 end
MISSING_ELSE
==>
161 end
162 // we are in interrupt timeout state
163 // in case an escalation comes in, we immediately have to
164 // switch over to the first escalation phase.
165 // in case the interrupt timeout hits it's cycle count, we
166 // also enter escalation phase0.
167 // ongoing timeouts can always be cleared.
168 TimeoutSt: begin
169 esc_state_o = Timeout;
170
171 if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
-4-
172 state_d = Phase0St;
==>
173 cnt_en = 1'b1;
174 cnt_clr = 1'b1;
175 esc_trig_o = 1'b1;
176 // the timeout enable is connected to the irq state
177 // if that is cleared, stop the timeout counter
178 end else if (timeout_en_i) begin
-5-
179 cnt_en = 1'b1;
==>
180 end else begin
181 state_d = IdleSt;
==>
182 cnt_clr = 1'b1;
183 end
184 end
185 // note: autolocking the clear signal is done in the regfile
186 Phase0St: begin
187 cnt_en = 1'b1;
188 phase_oh[0] = 1'b1;
189 thresh = phase_cyc_i[0];
190 esc_state_o = Phase0;
191 latch_crashdump_o = (crashdump_phase_i == 2'b00);
192
193 if (clr_i) begin
-6-
194 state_d = IdleSt;
==>
195 cnt_clr = 1'b1;
196 cnt_en = 1'b0;
197 end else if (cnt_ge) begin
-7-
198 state_d = Phase1St;
==>
199 cnt_clr = 1'b1;
200 cnt_en = 1'b1;
201 end
MISSING_ELSE
==>
202 end
203 Phase1St: begin
204 cnt_en = 1'b1;
205 phase_oh[1] = 1'b1;
206 thresh = phase_cyc_i[1];
207 esc_state_o = Phase1;
208 latch_crashdump_o = (crashdump_phase_i == 2'b01);
209
210 if (clr_i) begin
-8-
211 state_d = IdleSt;
==>
212 cnt_clr = 1'b1;
213 cnt_en = 1'b0;
214 end else if (cnt_ge) begin
-9-
215 state_d = Phase2St;
==>
216 cnt_clr = 1'b1;
217 cnt_en = 1'b1;
218 end
MISSING_ELSE
==>
219 end
220 Phase2St: begin
221 cnt_en = 1'b1;
222 phase_oh[2] = 1'b1;
223 thresh = phase_cyc_i[2];
224 esc_state_o = Phase2;
225 latch_crashdump_o = (crashdump_phase_i == 2'b10);
226
227
228 if (clr_i) begin
-10-
229 state_d = IdleSt;
==>
230 cnt_clr = 1'b1;
231 cnt_en = 1'b0;
232 end else if (cnt_ge) begin
-11-
233 state_d = Phase3St;
==>
234 cnt_clr = 1'b1;
235 end
MISSING_ELSE
==>
236 end
237 Phase3St: begin
238 cnt_en = 1'b1;
239 phase_oh[3] = 1'b1;
240 thresh = phase_cyc_i[3];
241 esc_state_o = Phase3;
242 latch_crashdump_o = (crashdump_phase_i == 2'b11);
243
244 if (clr_i) begin
-12-
245 state_d = IdleSt;
==>
246 cnt_clr = 1'b1;
247 cnt_en = 1'b0;
248 end else if (cnt_ge) begin
-13-
249 state_d = TerminalSt;
==>
250 cnt_clr = 1'b1;
251 cnt_en = 1'b0;
252 end
MISSING_ELSE
==>
253 end
254 // final, terminal state after escalation.
255 // if clr is locked down, only a system reset
256 // will get us out of this state
257 TerminalSt: begin
258 cnt_clr = 1'b1;
259 esc_state_o = Terminal;
260 if (clr_i) begin
-14-
261 state_d = IdleSt;
==>
262 end
MISSING_ELSE
==>
263 end
264 // error state, only reached if the FSM has been
265 // glitched. in this state, we trigger all escalation
266 // actions at once.
267 FsmErrorSt: begin
268 esc_state_o = FsmError;
==>
269 fsm_error = 1'b1;
270 end
271 // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272 // catch glitches.
273 default: begin
274 state_d = FsmErrorSt;
==>
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T3,T4,T13 |
IdleSt |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T19,T16,T17 |
IdleSt |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
TimeoutSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T17,T39,T42 |
TimeoutSt |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T19,T16,T17 |
TimeoutSt |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T19,T16,T39 |
Phase0St |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T119,T120,T121 |
Phase0St |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T13,T14,T15 |
Phase0St |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T14,T15,T16 |
Phase1St |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T122,T70,T123 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
Covered |
T13,T14,T15 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T14,T15,T16 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T39,T41,T124 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
Covered |
T13,T14,T15 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
Covered |
T14,T15,T16 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T125,T126 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T13,T14,T15 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T14,T15,T16 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T62,T63,T83 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T13,T14,T15 |
FsmErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T7,T8 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T7,T8 |
283 if (accu_fail_i || cnt_error) begin
-1-
284 state_d = FsmErrorSt;
==>
285 fsm_error = 1'b1;
286 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T8 |
0 |
Covered |
T1,T2,T3 |
305 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer
Assertion Details
AccuFailToFsmError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
252 |
0 |
0 |
T5 |
19444 |
29 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
40 |
0 |
0 |
T8 |
0 |
69 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T57 |
0 |
53 |
0 |
0 |
T58 |
0 |
61 |
0 |
0 |
CheckAccumTrig0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
469 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T13 |
1315 |
1 |
0 |
0 |
T14 |
19226 |
1 |
0 |
0 |
T15 |
31550 |
1 |
0 |
0 |
T16 |
25683 |
1 |
0 |
0 |
T19 |
33778 |
0 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T39 |
0 |
1 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T46 |
28765 |
0 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T62 |
0 |
5 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
CheckAccumTrig1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
22 |
0 |
0 |
T17 |
5047 |
1 |
0 |
0 |
T32 |
31996 |
0 |
0 |
0 |
T33 |
29367 |
0 |
0 |
0 |
T34 |
33710 |
0 |
0 |
0 |
T39 |
0 |
1 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T47 |
15520 |
0 |
0 |
0 |
T53 |
69336 |
0 |
0 |
0 |
T59 |
20510 |
0 |
0 |
0 |
T60 |
1256 |
0 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T68 |
0 |
1 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T75 |
0 |
1 |
0 |
0 |
T77 |
10813 |
0 |
0 |
0 |
T78 |
5395 |
0 |
0 |
0 |
CheckClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
211 |
0 |
0 |
T37 |
0 |
3 |
0 |
0 |
T39 |
15465 |
1 |
0 |
0 |
T42 |
29110 |
0 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T49 |
17971 |
0 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T57 |
42098 |
0 |
0 |
0 |
T61 |
49675 |
0 |
0 |
0 |
T62 |
99275 |
4 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
T65 |
98827 |
0 |
0 |
0 |
T68 |
0 |
2 |
0 |
0 |
T79 |
54114 |
0 |
0 |
0 |
T83 |
0 |
1 |
0 |
0 |
T84 |
0 |
1 |
0 |
0 |
T85 |
0 |
1 |
0 |
0 |
T86 |
24272 |
0 |
0 |
0 |
T87 |
984 |
0 |
0 |
0 |
CheckEn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
555884031 |
232791736 |
0 |
0 |
T1 |
2974 |
735 |
0 |
0 |
T2 |
7562 |
7468 |
0 |
0 |
T3 |
18600 |
3402 |
0 |
0 |
T4 |
22526 |
687 |
0 |
0 |
T5 |
327 |
248 |
0 |
0 |
T9 |
21304 |
21224 |
0 |
0 |
T10 |
6357 |
4413 |
0 |
0 |
T11 |
4919 |
3106 |
0 |
0 |
T12 |
2856 |
2178 |
0 |
0 |
T18 |
1665 |
959 |
0 |
0 |
CheckPhase0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
527 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T13 |
1315 |
1 |
0 |
0 |
T14 |
19226 |
1 |
0 |
0 |
T15 |
31550 |
1 |
0 |
0 |
T16 |
25683 |
1 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T19 |
33778 |
0 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T39 |
0 |
2 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T46 |
28765 |
0 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T62 |
0 |
5 |
0 |
0 |
CheckPhase1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
509 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T13 |
1315 |
1 |
0 |
0 |
T14 |
19226 |
1 |
0 |
0 |
T15 |
31550 |
1 |
0 |
0 |
T16 |
25683 |
1 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T19 |
33778 |
0 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T39 |
0 |
2 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T46 |
28765 |
0 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T62 |
0 |
5 |
0 |
0 |
CheckPhase2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
500 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T13 |
1315 |
1 |
0 |
0 |
T14 |
19226 |
1 |
0 |
0 |
T15 |
31550 |
1 |
0 |
0 |
T16 |
25683 |
1 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T19 |
33778 |
0 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T39 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T46 |
28765 |
0 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T62 |
0 |
5 |
0 |
0 |
CheckPhase3_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
498 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T13 |
1315 |
1 |
0 |
0 |
T14 |
19226 |
1 |
0 |
0 |
T15 |
31550 |
1 |
0 |
0 |
T16 |
25683 |
1 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T19 |
33778 |
0 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T39 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T46 |
28765 |
0 |
0 |
0 |
T48 |
34401 |
0 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T62 |
0 |
5 |
0 |
0 |
CheckTimeout0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
481 |
0 |
0 |
T8 |
42546 |
0 |
0 |
0 |
T16 |
25683 |
1 |
0 |
0 |
T17 |
5047 |
1 |
0 |
0 |
T19 |
33778 |
2 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T26 |
24466 |
0 |
0 |
0 |
T39 |
0 |
2 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T46 |
28765 |
0 |
0 |
0 |
T47 |
15520 |
0 |
0 |
0 |
T53 |
69336 |
0 |
0 |
0 |
T59 |
20510 |
0 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T83 |
0 |
8 |
0 |
0 |
T88 |
0 |
8 |
0 |
0 |
T89 |
0 |
11 |
0 |
0 |
CheckTimeoutSt1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
67253 |
0 |
0 |
T8 |
42546 |
0 |
0 |
0 |
T16 |
25683 |
90 |
0 |
0 |
T17 |
5047 |
6 |
0 |
0 |
T19 |
33778 |
346 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T26 |
24466 |
0 |
0 |
0 |
T39 |
0 |
66 |
0 |
0 |
T46 |
28765 |
0 |
0 |
0 |
T47 |
15520 |
0 |
0 |
0 |
T53 |
69336 |
0 |
0 |
0 |
T59 |
20510 |
0 |
0 |
0 |
T67 |
0 |
314 |
0 |
0 |
T83 |
0 |
1227 |
0 |
0 |
T88 |
0 |
983 |
0 |
0 |
T89 |
0 |
1656 |
0 |
0 |
T91 |
0 |
333 |
0 |
0 |
T92 |
0 |
1448 |
0 |
0 |
CheckTimeoutSt2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
407 |
0 |
0 |
T8 |
42546 |
0 |
0 |
0 |
T16 |
25683 |
1 |
0 |
0 |
T17 |
5047 |
0 |
0 |
0 |
T19 |
33778 |
2 |
0 |
0 |
T25 |
48856 |
0 |
0 |
0 |
T26 |
24466 |
0 |
0 |
0 |
T39 |
0 |
1 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T46 |
28765 |
0 |
0 |
0 |
T47 |
15520 |
0 |
0 |
0 |
T53 |
69336 |
0 |
0 |
0 |
T59 |
20510 |
0 |
0 |
0 |
T68 |
0 |
1 |
0 |
0 |
T83 |
0 |
7 |
0 |
0 |
T88 |
0 |
8 |
0 |
0 |
T89 |
0 |
11 |
0 |
0 |
T91 |
0 |
1 |
0 |
0 |
T92 |
0 |
3 |
0 |
0 |
CheckTimeoutStTrig_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
48 |
0 |
0 |
T28 |
53053 |
0 |
0 |
0 |
T29 |
22250 |
0 |
0 |
0 |
T37 |
0 |
3 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T44 |
0 |
2 |
0 |
0 |
T66 |
57567 |
0 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T83 |
110923 |
1 |
0 |
0 |
T88 |
19843 |
0 |
0 |
0 |
T90 |
34854 |
0 |
0 |
0 |
T93 |
102645 |
0 |
0 |
0 |
T95 |
0 |
1 |
0 |
0 |
T97 |
0 |
1 |
0 |
0 |
T99 |
0 |
1 |
0 |
0 |
T100 |
0 |
1 |
0 |
0 |
T101 |
1271 |
0 |
0 |
0 |
T102 |
45963 |
0 |
0 |
0 |
T103 |
5568 |
0 |
0 |
0 |
ErrorStAllEscAsserted_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
1426 |
0 |
0 |
T5 |
19444 |
143 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
333 |
0 |
0 |
T8 |
0 |
313 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T57 |
0 |
328 |
0 |
0 |
T58 |
0 |
309 |
0 |
0 |
ErrorStIsTerminal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
1156 |
0 |
0 |
T5 |
19444 |
113 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
273 |
0 |
0 |
T8 |
0 |
253 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T57 |
0 |
268 |
0 |
0 |
T58 |
0 |
249 |
0 |
0 |
EscStateOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
555881378 |
555813301 |
0 |
0 |
T1 |
2974 |
2892 |
0 |
0 |
T2 |
7562 |
7469 |
0 |
0 |
T3 |
18600 |
18438 |
0 |
0 |
T4 |
22526 |
22391 |
0 |
0 |
T5 |
78 |
0 |
0 |
0 |
T9 |
21304 |
21225 |
0 |
0 |
T10 |
6357 |
6292 |
0 |
0 |
T11 |
4919 |
4869 |
0 |
0 |
T12 |
2856 |
2799 |
0 |
0 |
T18 |
1665 |
1594 |
0 |
0 |
T20 |
0 |
26619 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
555976364 |
0 |
0 |
T1 |
2974 |
2892 |
0 |
0 |
T2 |
7562 |
7469 |
0 |
0 |
T3 |
18600 |
18438 |
0 |
0 |
T4 |
22526 |
22391 |
0 |
0 |
T5 |
19444 |
6561 |
0 |
0 |
T9 |
21304 |
21225 |
0 |
0 |
T10 |
6357 |
6292 |
0 |
0 |
T11 |
4919 |
4869 |
0 |
0 |
T12 |
2856 |
2799 |
0 |
0 |
T18 |
1665 |
1594 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer
| Line No. | Total | Covered | Percent |
TOTAL | | 101 | 101 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
ALWAYS | 134 | 89 | 89 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
ALWAYS | 305 | 3 | 3 | 100.00 |
84 logic [EscCntDw-1:0] thresh;
85 1/1 assign cnt_ge = (esc_cnt_o >= thresh);
Tests: T1 T2 T3
86
87 //////////////
88 // Main FSM //
89 //////////////
90
91 logic [N_PHASES-1:0] phase_oh;
92
93 // SEC_CM: ESC_TIMER.FSM.SPARSE
94 // Encoding generated with:
95 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96 // -s 784905746 --language=sv
97 //
98 // Hamming distance histogram:
99 //
100 // 0: --
101 // 1: --
102 // 2: --
103 // 3: --
104 // 4: --
105 // 5: |||||||||||||||||||| (46.43%)
106 // 6: |||||||||||||||||||| (46.43%)
107 // 7: ||| (7.14%)
108 // 8: --
109 // 9: --
110 // 10: --
111 //
112 // Minimum Hamming distance: 5
113 // Maximum Hamming distance: 7
114 // Minimum Hamming weight: 3
115 // Maximum Hamming weight: 9
116 //
117 localparam int StateWidth = 10;
118 typedef enum logic [StateWidth-1:0] {
119 IdleSt = 10'b1011011010,
120 TimeoutSt = 10'b0000100110,
121 Phase0St = 10'b1110000101,
122 Phase1St = 10'b0101010100,
123 Phase2St = 10'b0000011001,
124 Phase3St = 10'b1001100001,
125 TerminalSt = 10'b1101111111,
126 FsmErrorSt = 10'b0111101000
127 } state_e;
128
129 logic fsm_error;
130 state_e state_d, state_q;
131
132 always_comb begin : p_fsm
133 // default
134 1/1 state_d = state_q;
Tests: T1 T2 T3
135 1/1 esc_state_o = Idle;
Tests: T1 T2 T3
136 1/1 cnt_en = 1'b0;
Tests: T1 T2 T3
137 1/1 cnt_clr = 1'b0;
Tests: T1 T2 T3
138 1/1 esc_trig_o = 1'b0;
Tests: T1 T2 T3
139 1/1 phase_oh = '0;
Tests: T1 T2 T3
140 1/1 thresh = timeout_cyc_i;
Tests: T1 T2 T3
141 1/1 fsm_error = 1'b0;
Tests: T1 T2 T3
142 1/1 latch_crashdump_o = 1'b0;
Tests: T1 T2 T3
143
144 1/1 unique case (state_q)
Tests: T1 T2 T3
145 // wait for an escalation trigger or an alert trigger
146 // the latter will trigger an interrupt timeout
147 IdleSt: begin
148 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T3
149 1/1 esc_state_o = Idle;
Tests: T1 T2 T3
150
151 1/1 if (accu_trig_i && en_i && !clr_i) begin
Tests: T1 T2 T3
152 1/1 state_d = Phase0St;
Tests: T10 T16 T47
153 1/1 cnt_en = 1'b1;
Tests: T10 T16 T47
154 1/1 esc_trig_o = 1'b1;
Tests: T10 T16 T47
155 // the counter is zero in this state. so if the
156 // timeout count is zero (==disabled), cnt_ge will be true.
157 1/1 end else if (timeout_en_i && !cnt_ge && en_i) begin
Tests: T1 T2 T3
158 1/1 cnt_en = 1'b1;
Tests: T17 T77 T32
159 1/1 state_d = TimeoutSt;
Tests: T17 T77 T32
160 end
MISSING_ELSE
161 end
162 // we are in interrupt timeout state
163 // in case an escalation comes in, we immediately have to
164 // switch over to the first escalation phase.
165 // in case the interrupt timeout hits it's cycle count, we
166 // also enter escalation phase0.
167 // ongoing timeouts can always be cleared.
168 TimeoutSt: begin
169 1/1 esc_state_o = Timeout;
Tests: T17 T77 T32
170
171 1/1 if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
Tests: T17 T77 T32
172 1/1 state_d = Phase0St;
Tests: T17 T90 T67
173 1/1 cnt_en = 1'b1;
Tests: T17 T90 T67
174 1/1 cnt_clr = 1'b1;
Tests: T17 T90 T67
175 1/1 esc_trig_o = 1'b1;
Tests: T17 T90 T67
176 // the timeout enable is connected to the irq state
177 // if that is cleared, stop the timeout counter
178 1/1 end else if (timeout_en_i) begin
Tests: T17 T77 T32
179 1/1 cnt_en = 1'b1;
Tests: T17 T77 T32
180 end else begin
181 1/1 state_d = IdleSt;
Tests: T77 T32 T63
182 1/1 cnt_clr = 1'b1;
Tests: T77 T32 T63
183 end
184 end
185 // note: autolocking the clear signal is done in the regfile
186 Phase0St: begin
187 1/1 cnt_en = 1'b1;
Tests: T10 T16 T17
188 1/1 phase_oh[0] = 1'b1;
Tests: T10 T16 T17
189 1/1 thresh = phase_cyc_i[0];
Tests: T10 T16 T17
190 1/1 esc_state_o = Phase0;
Tests: T10 T16 T17
191 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b00);
Tests: T10 T16 T17
192
193 1/1 if (clr_i) begin
Tests: T10 T16 T17
194 1/1 state_d = IdleSt;
Tests: T35 T127 T128
195 1/1 cnt_clr = 1'b1;
Tests: T35 T127 T128
196 1/1 cnt_en = 1'b0;
Tests: T35 T127 T128
197 1/1 end else if (cnt_ge) begin
Tests: T10 T16 T17
198 1/1 state_d = Phase1St;
Tests: T10 T16 T17
199 1/1 cnt_clr = 1'b1;
Tests: T10 T16 T17
200 1/1 cnt_en = 1'b1;
Tests: T10 T16 T17
201 end
MISSING_ELSE
202 end
203 Phase1St: begin
204 1/1 cnt_en = 1'b1;
Tests: T10 T16 T17
205 1/1 phase_oh[1] = 1'b1;
Tests: T10 T16 T17
206 1/1 thresh = phase_cyc_i[1];
Tests: T10 T16 T17
207 1/1 esc_state_o = Phase1;
Tests: T10 T16 T17
208 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b01);
Tests: T10 T16 T17
209
210 1/1 if (clr_i) begin
Tests: T10 T16 T17
211 1/1 state_d = IdleSt;
Tests: T129 T75 T130
212 1/1 cnt_clr = 1'b1;
Tests: T129 T75 T130
213 1/1 cnt_en = 1'b0;
Tests: T129 T75 T130
214 1/1 end else if (cnt_ge) begin
Tests: T10 T16 T17
215 1/1 state_d = Phase2St;
Tests: T10 T16 T17
216 1/1 cnt_clr = 1'b1;
Tests: T10 T16 T17
217 1/1 cnt_en = 1'b1;
Tests: T10 T16 T17
218 end
MISSING_ELSE
219 end
220 Phase2St: begin
221 1/1 cnt_en = 1'b1;
Tests: T10 T16 T17
222 1/1 phase_oh[2] = 1'b1;
Tests: T10 T16 T17
223 1/1 thresh = phase_cyc_i[2];
Tests: T10 T16 T17
224 1/1 esc_state_o = Phase2;
Tests: T10 T16 T17
225 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b10);
Tests: T10 T16 T17
226
227
228 1/1 if (clr_i) begin
Tests: T10 T16 T17
229 1/1 state_d = IdleSt;
Tests: T39 T40 T131
230 1/1 cnt_clr = 1'b1;
Tests: T39 T40 T131
231 1/1 cnt_en = 1'b0;
Tests: T39 T40 T131
232 1/1 end else if (cnt_ge) begin
Tests: T10 T16 T17
233 1/1 state_d = Phase3St;
Tests: T10 T16 T17
234 1/1 cnt_clr = 1'b1;
Tests: T10 T16 T17
235 end
MISSING_ELSE
236 end
237 Phase3St: begin
238 1/1 cnt_en = 1'b1;
Tests: T10 T16 T17
239 1/1 phase_oh[3] = 1'b1;
Tests: T10 T16 T17
240 1/1 thresh = phase_cyc_i[3];
Tests: T10 T16 T17
241 1/1 esc_state_o = Phase3;
Tests: T10 T16 T17
242 1/1 latch_crashdump_o = (crashdump_phase_i == 2'b11);
Tests: T10 T16 T17
243
244 1/1 if (clr_i) begin
Tests: T10 T16 T17
245 1/1 state_d = IdleSt;
Tests: T42 T44 T40
246 1/1 cnt_clr = 1'b1;
Tests: T42 T44 T40
247 1/1 cnt_en = 1'b0;
Tests: T42 T44 T40
248 1/1 end else if (cnt_ge) begin
Tests: T10 T16 T17
249 1/1 state_d = TerminalSt;
Tests: T10 T16 T17
250 1/1 cnt_clr = 1'b1;
Tests: T10 T16 T17
251 1/1 cnt_en = 1'b0;
Tests: T10 T16 T17
252 end
MISSING_ELSE
253 end
254 // final, terminal state after escalation.
255 // if clr is locked down, only a system reset
256 // will get us out of this state
257 TerminalSt: begin
258 1/1 cnt_clr = 1'b1;
Tests: T10 T16 T17
259 1/1 esc_state_o = Terminal;
Tests: T10 T16 T17
260 1/1 if (clr_i) begin
Tests: T10 T16 T17
261 1/1 state_d = IdleSt;
Tests: T47 T55 T39
262 end
MISSING_ELSE
263 end
264 // error state, only reached if the FSM has been
265 // glitched. in this state, we trigger all escalation
266 // actions at once.
267 FsmErrorSt: begin
268 1/1 esc_state_o = FsmError;
Tests: T5 T7 T8
269 1/1 fsm_error = 1'b1;
Tests: T5 T7 T8
270 end
271 // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272 // catch glitches.
273 default: begin
274 state_d = FsmErrorSt;
275 esc_state_o = FsmError;
276 fsm_error = 1'b1;
277 end
278 endcase
279
280 // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281 // if any of the duplicate counter pairs has an inconsistent state
282 // we move into the terminal FSM error state.
283 1/1 if (accu_fail_i || cnt_error) begin
Tests: T1 T2 T3
284 1/1 state_d = FsmErrorSt;
Tests: T5 T7 T8
285 1/1 fsm_error = 1'b1;
Tests: T5 T7 T8
286 end
MISSING_ELSE
287 end
288
289 logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290 for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291 // generate configuration mask for escalation enable signals
292 4/4 assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
293 // mask reduce current phase state vector
294 // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295 4/4 assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
296 end
297
298 ///////////////////
299 // FSM Registers //
300 ///////////////////
301
302 // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303 // an alert signal, this condition is handled internally in the alert handler. The
304 // EnableAlertTriggerSVA parameter is therefore set to 0.
305 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1 `ifdef SIMULATION
305.2 prim_sparse_fsm_flop #(
305.3 .StateEnumT(state_e),
305.4 .Width($bits(state_e)),
305.5 .ResetValue($bits(state_e)'(IdleSt)),
305.6 .EnableAlertTriggerSVA(0),
305.7 .CustomForceName("state_q")
305.8 ) u_state_regs (
305.9 .clk_i ( clk_i ),
305.10 .rst_ni ( rst_ni ),
305.11 .state_i ( state_d ),
305.12 .state_o ( )
305.13 );
305.14 always_ff @(posedge clk_i or negedge rst_ni) begin
305.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
305.16 1/1 state_q <= IdleSt;
Tests: T1 T2 T3
305.17 end else begin
305.18 1/1 state_q <= state_d;
Tests: T1 T2 T3
305.19 end
305.20 end
305.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))
305.22 else begin
305.23 `ifdef UVM
305.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
305.25 "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);
305.26 `else
305.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
305.28 `PRIM_STRINGIFY(u_state_regs_A));
305.29 `endif
305.30 end
305.31 `else
305.32 prim_sparse_fsm_flop #(
305.33 .StateEnumT(state_e),
305.34 .Width($bits(state_e)),
305.35 .ResetValue($bits(state_e)'(IdleSt)),
305.36 .EnableAlertTriggerSVA(0)
305.37 ) u_state_regs (
305.38 .clk_i ( clk_i ),
305.39 .rst_ni ( rst_ni ),
305.40 .state_i ( state_d ),
305.41 .state_o ( state_q )
305.42 );
305.43 `endif
Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer
| Total | Covered | Percent |
Conditions | 45 | 43 | 95.56 |
Logical | 45 | 43 | 95.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 66
EXPRESSION (cnt_clr && ((!cnt_en)))
---1--- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T10,T16,T17 |
1 | 1 | Covered | T1,T2,T3 |
LINE 66
EXPRESSION (cnt_clr && cnt_en)
---1--- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T17,T47 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T10,T16,T17 |
LINE 151
EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T18,T10,T11 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T10,T16,T47 |
LINE 157
EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
------1----- -----2----- --3-
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T21,T48,T16 |
1 | 0 | 1 | Covered | T10,T20,T14 |
1 | 1 | 0 | Covered | T1,T48,T16 |
1 | 1 | 1 | Covered | T17,T77,T32 |
LINE 171
EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
-----------------1----------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T17,T77,T32 |
0 | 1 | Covered | T17,T90,T91 |
1 | 0 | Covered | T67,T92,T40 |
LINE 171
SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T17,T77,T32 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T67,T92,T40 |
LINE 171
SUB-EXPRESSION (cnt_ge && timeout_en_i)
---1-- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T17,T77,T32 |
1 | 0 | Covered | T51 |
1 | 1 | Covered | T17,T90,T91 |
LINE 191
EXPRESSION (crashdump_phase_i == 2'b0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T16,T17,T55 |
1 | Covered | T10,T47,T60 |
LINE 208
EXPRESSION (crashdump_phase_i == 2'b1)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T10,T16,T17 |
1 | Covered | T55,T66,T91 |
LINE 225
EXPRESSION (crashdump_phase_i == 2'b10)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T10,T17,T47 |
1 | Covered | T16,T61,T67 |
LINE 242
EXPRESSION (crashdump_phase_i == 2'b11)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T10,T16,T47 |
1 | Covered | T17,T42,T65 |
LINE 283
EXPRESSION (accu_fail_i || cnt_error)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T5,T7,T8 |
LINE 295
EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T10,T16,T60 |
LINE 295
EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T10,T17,T47 |
LINE 295
EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T10,T47,T60 |
LINE 295
EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T10,T16,T17 |
FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
8 |
8 |
100.00 |
(Not included in score) |
Transitions |
14 |
14 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
FsmErrorSt |
284 |
Covered |
T5,T7,T8 |
IdleSt |
181 |
Covered |
T1,T2,T3 |
Phase0St |
152 |
Covered |
T10,T16,T17 |
Phase1St |
198 |
Covered |
T10,T16,T17 |
Phase2St |
215 |
Covered |
T10,T16,T17 |
Phase3St |
233 |
Covered |
T10,T16,T17 |
TerminalSt |
249 |
Covered |
T10,T16,T17 |
TimeoutSt |
159 |
Covered |
T17,T77,T32 |
transitions | Line No. | Covered | Tests | Exclude Annotation |
IdleSt->FsmErrorSt |
284 |
Covered |
T5,T7,T8 |
|
IdleSt->Phase0St |
152 |
Covered |
T10,T16,T47 |
|
IdleSt->TimeoutSt |
159 |
Covered |
T17,T77,T32 |
|
Phase0St->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase0St->IdleSt |
194 |
Covered |
T37,T35,T127 |
|
Phase0St->Phase1St |
198 |
Covered |
T10,T16,T17 |
|
Phase1St->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase1St->IdleSt |
211 |
Covered |
T44,T129,T75 |
|
Phase1St->Phase2St |
215 |
Covered |
T10,T16,T17 |
|
Phase2St->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase2St->IdleSt |
229 |
Covered |
T39,T40,T131 |
|
Phase2St->Phase3St |
233 |
Covered |
T10,T16,T17 |
|
Phase3St->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase3St->IdleSt |
245 |
Covered |
T42,T44,T40 |
|
Phase3St->TerminalSt |
249 |
Covered |
T10,T16,T17 |
|
TerminalSt->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
TerminalSt->IdleSt |
261 |
Covered |
T47,T55,T39 |
|
TimeoutSt->FsmErrorSt |
284 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
TimeoutSt->IdleSt |
181 |
Covered |
T77,T32,T63 |
|
TimeoutSt->Phase0St |
172 |
Covered |
T17,T90,T67 |
|
Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer
| Line No. | Total | Covered | Percent |
Branches |
|
26 |
26 |
100.00 |
CASE |
144 |
22 |
22 |
100.00 |
IF |
283 |
2 |
2 |
100.00 |
IF |
305 |
2 |
2 |
100.00 |
144 unique case (state_q)
-1-
145 // wait for an escalation trigger or an alert trigger
146 // the latter will trigger an interrupt timeout
147 IdleSt: begin
148 cnt_clr = 1'b1;
149 esc_state_o = Idle;
150
151 if (accu_trig_i && en_i && !clr_i) begin
-2-
152 state_d = Phase0St;
==>
153 cnt_en = 1'b1;
154 esc_trig_o = 1'b1;
155 // the counter is zero in this state. so if the
156 // timeout count is zero (==disabled), cnt_ge will be true.
157 end else if (timeout_en_i && !cnt_ge && en_i) begin
-3-
158 cnt_en = 1'b1;
==>
159 state_d = TimeoutSt;
160 end
MISSING_ELSE
==>
161 end
162 // we are in interrupt timeout state
163 // in case an escalation comes in, we immediately have to
164 // switch over to the first escalation phase.
165 // in case the interrupt timeout hits it's cycle count, we
166 // also enter escalation phase0.
167 // ongoing timeouts can always be cleared.
168 TimeoutSt: begin
169 esc_state_o = Timeout;
170
171 if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
-4-
172 state_d = Phase0St;
==>
173 cnt_en = 1'b1;
174 cnt_clr = 1'b1;
175 esc_trig_o = 1'b1;
176 // the timeout enable is connected to the irq state
177 // if that is cleared, stop the timeout counter
178 end else if (timeout_en_i) begin
-5-
179 cnt_en = 1'b1;
==>
180 end else begin
181 state_d = IdleSt;
==>
182 cnt_clr = 1'b1;
183 end
184 end
185 // note: autolocking the clear signal is done in the regfile
186 Phase0St: begin
187 cnt_en = 1'b1;
188 phase_oh[0] = 1'b1;
189 thresh = phase_cyc_i[0];
190 esc_state_o = Phase0;
191 latch_crashdump_o = (crashdump_phase_i == 2'b00);
192
193 if (clr_i) begin
-6-
194 state_d = IdleSt;
==>
195 cnt_clr = 1'b1;
196 cnt_en = 1'b0;
197 end else if (cnt_ge) begin
-7-
198 state_d = Phase1St;
==>
199 cnt_clr = 1'b1;
200 cnt_en = 1'b1;
201 end
MISSING_ELSE
==>
202 end
203 Phase1St: begin
204 cnt_en = 1'b1;
205 phase_oh[1] = 1'b1;
206 thresh = phase_cyc_i[1];
207 esc_state_o = Phase1;
208 latch_crashdump_o = (crashdump_phase_i == 2'b01);
209
210 if (clr_i) begin
-8-
211 state_d = IdleSt;
==>
212 cnt_clr = 1'b1;
213 cnt_en = 1'b0;
214 end else if (cnt_ge) begin
-9-
215 state_d = Phase2St;
==>
216 cnt_clr = 1'b1;
217 cnt_en = 1'b1;
218 end
MISSING_ELSE
==>
219 end
220 Phase2St: begin
221 cnt_en = 1'b1;
222 phase_oh[2] = 1'b1;
223 thresh = phase_cyc_i[2];
224 esc_state_o = Phase2;
225 latch_crashdump_o = (crashdump_phase_i == 2'b10);
226
227
228 if (clr_i) begin
-10-
229 state_d = IdleSt;
==>
230 cnt_clr = 1'b1;
231 cnt_en = 1'b0;
232 end else if (cnt_ge) begin
-11-
233 state_d = Phase3St;
==>
234 cnt_clr = 1'b1;
235 end
MISSING_ELSE
==>
236 end
237 Phase3St: begin
238 cnt_en = 1'b1;
239 phase_oh[3] = 1'b1;
240 thresh = phase_cyc_i[3];
241 esc_state_o = Phase3;
242 latch_crashdump_o = (crashdump_phase_i == 2'b11);
243
244 if (clr_i) begin
-12-
245 state_d = IdleSt;
==>
246 cnt_clr = 1'b1;
247 cnt_en = 1'b0;
248 end else if (cnt_ge) begin
-13-
249 state_d = TerminalSt;
==>
250 cnt_clr = 1'b1;
251 cnt_en = 1'b0;
252 end
MISSING_ELSE
==>
253 end
254 // final, terminal state after escalation.
255 // if clr is locked down, only a system reset
256 // will get us out of this state
257 TerminalSt: begin
258 cnt_clr = 1'b1;
259 esc_state_o = Terminal;
260 if (clr_i) begin
-14-
261 state_d = IdleSt;
==>
262 end
MISSING_ELSE
==>
263 end
264 // error state, only reached if the FSM has been
265 // glitched. in this state, we trigger all escalation
266 // actions at once.
267 FsmErrorSt: begin
268 esc_state_o = FsmError;
==>
269 fsm_error = 1'b1;
270 end
271 // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272 // catch glitches.
273 default: begin
274 state_d = FsmErrorSt;
==>
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T16,T47 |
IdleSt |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T17,T77,T32 |
IdleSt |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
TimeoutSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T17,T90,T67 |
TimeoutSt |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T17,T77,T32 |
TimeoutSt |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T77,T32,T63 |
Phase0St |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T35,T127,T128 |
Phase0St |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T16,T17 |
Phase0St |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T16,T17,T47 |
Phase1St |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T129,T75,T130 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
Covered |
T10,T16,T17 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T16,T17,T47 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T39,T40,T131 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
Covered |
T10,T16,T17 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
Covered |
T16,T17,T47 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T42,T44,T40 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T10,T16,T17 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T16,T17,T47 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T47,T55,T39 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T10,T16,T17 |
FsmErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T7,T8 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T7,T8 |
283 if (accu_fail_i || cnt_error) begin
-1-
284 state_d = FsmErrorSt;
==>
285 fsm_error = 1'b1;
286 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T8 |
0 |
Covered |
T1,T2,T3 |
305 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer
Assertion Details
AccuFailToFsmError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
305 |
0 |
0 |
T5 |
19444 |
32 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
48 |
0 |
0 |
T8 |
0 |
77 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T57 |
0 |
74 |
0 |
0 |
T58 |
0 |
74 |
0 |
0 |
CheckAccumTrig0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
464 |
0 |
0 |
T4 |
22526 |
0 |
0 |
0 |
T5 |
19444 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T10 |
6357 |
1 |
0 |
0 |
T11 |
4919 |
0 |
0 |
0 |
T12 |
2856 |
0 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T42 |
0 |
2 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T61 |
0 |
2 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T86 |
0 |
2 |
0 |
0 |
CheckAccumTrig1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
31 |
0 |
0 |
T22 |
164940 |
0 |
0 |
0 |
T23 |
384507 |
0 |
0 |
0 |
T30 |
50589 |
0 |
0 |
0 |
T37 |
0 |
1 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T67 |
94473 |
1 |
0 |
0 |
T80 |
77680 |
0 |
0 |
0 |
T81 |
6034 |
0 |
0 |
0 |
T89 |
22539 |
0 |
0 |
0 |
T92 |
0 |
1 |
0 |
0 |
T100 |
0 |
1 |
0 |
0 |
T107 |
0 |
1 |
0 |
0 |
T118 |
0 |
1 |
0 |
0 |
T132 |
0 |
1 |
0 |
0 |
T133 |
0 |
1 |
0 |
0 |
T134 |
0 |
1 |
0 |
0 |
T135 |
118855 |
0 |
0 |
0 |
T136 |
3103 |
0 |
0 |
0 |
T137 |
2756 |
0 |
0 |
0 |
CheckClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
242 |
0 |
0 |
T32 |
31996 |
0 |
0 |
0 |
T33 |
29367 |
0 |
0 |
0 |
T34 |
33710 |
0 |
0 |
0 |
T39 |
0 |
2 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T47 |
15520 |
1 |
0 |
0 |
T53 |
69336 |
0 |
0 |
0 |
T54 |
16857 |
0 |
0 |
0 |
T55 |
67727 |
1 |
0 |
0 |
T60 |
1256 |
0 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T62 |
0 |
2 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
2 |
0 |
0 |
T77 |
10813 |
0 |
0 |
0 |
T78 |
5395 |
0 |
0 |
0 |
T86 |
0 |
1 |
0 |
0 |
T94 |
0 |
4 |
0 |
0 |
CheckEn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
555884031 |
268682201 |
0 |
0 |
T1 |
2974 |
2891 |
0 |
0 |
T2 |
7562 |
7468 |
0 |
0 |
T3 |
18600 |
18436 |
0 |
0 |
T4 |
22526 |
691 |
0 |
0 |
T5 |
327 |
248 |
0 |
0 |
T9 |
21304 |
21224 |
0 |
0 |
T10 |
6357 |
4435 |
0 |
0 |
T11 |
4919 |
3120 |
0 |
0 |
T12 |
2856 |
2191 |
0 |
0 |
T18 |
1665 |
963 |
0 |
0 |
CheckPhase0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
548 |
0 |
0 |
T4 |
22526 |
0 |
0 |
0 |
T5 |
19444 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T10 |
6357 |
1 |
0 |
0 |
T11 |
4919 |
0 |
0 |
0 |
T12 |
2856 |
0 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T42 |
0 |
2 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T61 |
0 |
2 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
CheckPhase1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
538 |
0 |
0 |
T4 |
22526 |
0 |
0 |
0 |
T5 |
19444 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T10 |
6357 |
1 |
0 |
0 |
T11 |
4919 |
0 |
0 |
0 |
T12 |
2856 |
0 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T42 |
0 |
2 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T61 |
0 |
2 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
CheckPhase2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
525 |
0 |
0 |
T4 |
22526 |
0 |
0 |
0 |
T5 |
19444 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T10 |
6357 |
1 |
0 |
0 |
T11 |
4919 |
0 |
0 |
0 |
T12 |
2856 |
0 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T39 |
0 |
2 |
0 |
0 |
T42 |
0 |
2 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T61 |
0 |
2 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
CheckPhase3_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
511 |
0 |
0 |
T4 |
22526 |
0 |
0 |
0 |
T5 |
19444 |
0 |
0 |
0 |
T7 |
38290 |
0 |
0 |
0 |
T10 |
6357 |
1 |
0 |
0 |
T11 |
4919 |
0 |
0 |
0 |
T12 |
2856 |
0 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T39 |
0 |
2 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T61 |
0 |
2 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
CheckTimeout0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
553 |
0 |
0 |
T17 |
5047 |
1 |
0 |
0 |
T32 |
31996 |
2 |
0 |
0 |
T33 |
29367 |
0 |
0 |
0 |
T34 |
33710 |
0 |
0 |
0 |
T47 |
15520 |
0 |
0 |
0 |
T53 |
69336 |
0 |
0 |
0 |
T59 |
20510 |
0 |
0 |
0 |
T60 |
1256 |
0 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
2 |
0 |
0 |
T77 |
10813 |
2 |
0 |
0 |
T78 |
5395 |
0 |
0 |
0 |
T83 |
0 |
8 |
0 |
0 |
T89 |
0 |
9 |
0 |
0 |
T90 |
0 |
1 |
0 |
0 |
T93 |
0 |
2 |
0 |
0 |
CheckTimeoutSt1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
77573 |
0 |
0 |
T17 |
5047 |
756 |
0 |
0 |
T32 |
31996 |
237 |
0 |
0 |
T33 |
29367 |
0 |
0 |
0 |
T34 |
33710 |
0 |
0 |
0 |
T47 |
15520 |
0 |
0 |
0 |
T53 |
69336 |
0 |
0 |
0 |
T59 |
20510 |
0 |
0 |
0 |
T60 |
1256 |
0 |
0 |
0 |
T63 |
0 |
68 |
0 |
0 |
T66 |
0 |
50 |
0 |
0 |
T67 |
0 |
49 |
0 |
0 |
T77 |
10813 |
123 |
0 |
0 |
T78 |
5395 |
0 |
0 |
0 |
T83 |
0 |
1368 |
0 |
0 |
T89 |
0 |
1277 |
0 |
0 |
T90 |
0 |
200 |
0 |
0 |
T93 |
0 |
422 |
0 |
0 |
CheckTimeoutSt2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
457 |
0 |
0 |
T32 |
31996 |
2 |
0 |
0 |
T33 |
29367 |
0 |
0 |
0 |
T34 |
33710 |
0 |
0 |
0 |
T39 |
15465 |
0 |
0 |
0 |
T42 |
29110 |
0 |
0 |
0 |
T54 |
16857 |
0 |
0 |
0 |
T55 |
67727 |
0 |
0 |
0 |
T60 |
1256 |
0 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T77 |
10813 |
2 |
0 |
0 |
T78 |
5395 |
0 |
0 |
0 |
T83 |
0 |
8 |
0 |
0 |
T89 |
0 |
9 |
0 |
0 |
T91 |
0 |
2 |
0 |
0 |
T93 |
0 |
2 |
0 |
0 |
T94 |
0 |
1 |
0 |
0 |
CheckTimeoutStTrig_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
64 |
0 |
0 |
T17 |
5047 |
1 |
0 |
0 |
T32 |
31996 |
0 |
0 |
0 |
T33 |
29367 |
0 |
0 |
0 |
T34 |
33710 |
0 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T47 |
15520 |
0 |
0 |
0 |
T53 |
69336 |
0 |
0 |
0 |
T59 |
20510 |
0 |
0 |
0 |
T60 |
1256 |
0 |
0 |
0 |
T77 |
10813 |
0 |
0 |
0 |
T78 |
5395 |
0 |
0 |
0 |
T90 |
0 |
1 |
0 |
0 |
T91 |
0 |
2 |
0 |
0 |
T95 |
0 |
1 |
0 |
0 |
T117 |
0 |
2 |
0 |
0 |
T138 |
0 |
1 |
0 |
0 |
T139 |
0 |
1 |
0 |
0 |
T140 |
0 |
1 |
0 |
0 |
ErrorStAllEscAsserted_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
1468 |
0 |
0 |
T5 |
19444 |
166 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
281 |
0 |
0 |
T8 |
0 |
340 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T57 |
0 |
343 |
0 |
0 |
T58 |
0 |
338 |
0 |
0 |
ErrorStIsTerminal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
1198 |
0 |
0 |
T5 |
19444 |
136 |
0 |
0 |
T6 |
10766 |
0 |
0 |
0 |
T7 |
38290 |
221 |
0 |
0 |
T8 |
0 |
280 |
0 |
0 |
T13 |
1315 |
0 |
0 |
0 |
T14 |
19226 |
0 |
0 |
0 |
T15 |
31550 |
0 |
0 |
0 |
T20 |
26691 |
0 |
0 |
0 |
T21 |
30081 |
0 |
0 |
0 |
T31 |
32198 |
0 |
0 |
0 |
T45 |
46054 |
0 |
0 |
0 |
T57 |
0 |
283 |
0 |
0 |
T58 |
0 |
278 |
0 |
0 |
EscStateOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
555881378 |
555813301 |
0 |
0 |
T1 |
2974 |
2892 |
0 |
0 |
T2 |
7562 |
7469 |
0 |
0 |
T3 |
18600 |
18438 |
0 |
0 |
T4 |
22526 |
22391 |
0 |
0 |
T5 |
78 |
0 |
0 |
0 |
T9 |
21304 |
21225 |
0 |
0 |
T10 |
6357 |
6292 |
0 |
0 |
T11 |
4919 |
4869 |
0 |
0 |
T12 |
2856 |
2799 |
0 |
0 |
T18 |
1665 |
1594 |
0 |
0 |
T20 |
0 |
26619 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
556159680 |
555976364 |
0 |
0 |
T1 |
2974 |
2892 |
0 |
0 |
T2 |
7562 |
7469 |
0 |
0 |
T3 |
18600 |
18438 |
0 |
0 |
T4 |
22526 |
22391 |
0 |
0 |
T5 |
19444 |
6561 |
0 |
0 |
T9 |
21304 |
21225 |
0 |
0 |
T10 |
6357 |
6292 |
0 |
0 |
T11 |
4919 |
4869 |
0 |
0 |
T12 |
2856 |
2799 |
0 |
0 |
T18 |
1665 |
1594 |
0 |
0 |