Unified Coverage Report :: Module :: alert_handler_class

Module : alert_handler_class

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_class.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_class	100.00	100.00

---

Module Instance : tb.dut.u_class

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : alert_handler_class

	Line No.	Total	Covered	Percent
TOTAL		12	12	100.00
CONT_ASSIGN	24	1	1	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	33	6	6	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	45	1	1	100.00

23                        // assign alert cause
24         1/1            assign alert_cause_o     = alert_en_i     & alert_trig_i;
           Tests:       T1 T2 T3 
25         1/1            assign loc_alert_cause_o = loc_alert_en_i & loc_alert_trig_i;
           Tests:       T1 T2 T3 
26                      
27                        // classification mapping
28                        logic [N_CLASSES-1:0][NAlerts-1:0]     class_masks;
29                        logic [N_CLASSES-1:0][N_LOC_ALERT-1:0] loc_class_masks;
30                      
31                        // this is basically an address to onehot0 decoder
32                        always_comb begin : p_class_mask
33         1/1              class_masks = '0;
           Tests:       T1 T2 T3 
34         1/1              loc_class_masks = '0;
           Tests:       T1 T2 T3 
35         1/1              for (int unsigned kk = 0; kk < NAlerts; kk++) begin
           Tests:       T1 T2 T3 
36         1/1                class_masks[alert_class_i[kk]][kk] = 1'b1;
           Tests:       T1 T2 T3 
37                          end
38         1/1              for (int unsigned kk = 0; kk < N_LOC_ALERT; kk++) begin
           Tests:       T1 T2 T3 
39         1/1                loc_class_masks[loc_alert_class_i[kk]][kk] = 1'b1;
           Tests:       T1 T2 T3 
40                          end
41                        end
42                      
43                        // mask and OR reduction, followed by class enable gating
44                        for (genvar k = 0; k < N_CLASSES; k++) begin : gen_classifier
45         4/4              assign class_trig_o[k] = (|{ alert_cause_o     & class_masks[k],
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3