Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	50687198	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24000134

1

T1

334

T2

837

T3

775

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	11719240	1			T1	125		T2	756		T3	290
values[0x0]	31422988	1			T1	434		T2	861		T3	1085
values[0x1]	31545104	1			T1	450		T2	831		T3	1091

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44139845	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

30547487

1

T1

416

T2

1060

T3

991

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	225135	1			T15	2		T10	6		T11	12
valid_sources[0x01]	223805	1			T15	2		T10	19		T11	5
valid_sources[0x02]	226523	1			T15	1		T10	10		T11	3
valid_sources[0x03]	226737	1			T15	1		T10	11		T11	2
valid_sources[0x04]	448799	1			T10	23		T5	4		T16	8
valid_sources[0x05]	245152	1			T15	1		T10	7		T11	4
valid_sources[0x06]	224768	1			T15	1		T10	32		T11	3
valid_sources[0x07]	268942	1			T15	2		T10	14		T11	1
valid_sources[0x08]	224807	1			T15	1		T10	14		T11	7
valid_sources[0x09]	230018	1			T10	11		T11	1		T12	2
valid_sources[0x0a]	223829	1			T15	1		T10	14		T11	6
valid_sources[0x0b]	225310	1			T15	2		T10	27		T11	8
valid_sources[0x0c]	226479	1			T15	1		T10	35		T11	1
valid_sources[0x0d]	225686	1			T15	1		T10	17		T12	3
valid_sources[0x0e]	225363	1			T15	1		T10	22		T11	12
valid_sources[0x0f]	225273	1			T15	1		T10	35		T12	1
valid_sources[0x10]	229494	1			T15	1		T10	19		T12	1
valid_sources[0x11]	225929	1			T15	1		T10	3		T12	1
valid_sources[0x12]	233289	1			T15	2		T10	7		T11	5
valid_sources[0x13]	225462	1			T15	2		T10	9		T12	2
valid_sources[0x14]	226697	1			T15	1		T10	14		T11	8
valid_sources[0x15]	228159	1			T15	3		T10	16		T11	3
valid_sources[0x16]	223166	1			T10	15		T11	1		T12	4
valid_sources[0x17]	225528	1			T15	1		T10	25		T11	2
valid_sources[0x18]	225304	1			T15	1		T10	19		T12	3
valid_sources[0x19]	224799	1			T15	1		T10	10		T11	12
valid_sources[0x1a]	224854	1			T15	4		T10	13		T11	2
valid_sources[0x1b]	223807	1			T15	1		T10	14		T12	1
valid_sources[0x1c]	227298	1			T15	2		T10	9		T12	1
valid_sources[0x1d]	232636	1			T15	1		T10	19		T11	8
valid_sources[0x1e]	230647	1			T15	1		T10	8		T5	1
valid_sources[0x1f]	669190	1			T10	11		T11	3		T5	1
valid_sources[0x20]	226657	1			T15	1		T10	23		T11	7
valid_sources[0x21]	584577	1			T10	27		T11	11		T5	4
valid_sources[0x22]	428569	1			T15	1		T10	14		T12	1
valid_sources[0x23]	251039	1			T15	3		T10	19		T11	2
valid_sources[0x24]	226200	1			T15	6		T10	16		T11	2
valid_sources[0x25]	226457	1			T15	1		T10	15		T11	3
valid_sources[0x26]	228307	1			T15	3		T10	33		T11	1
valid_sources[0x27]	234529	1			T15	4		T10	25		T11	1
valid_sources[0x28]	225223	1			T10	19		T11	2		T12	1
valid_sources[0x29]	228655	1			T10	13		T11	6		T12	2
valid_sources[0x2a]	226520	1			T3	2466		T15	3		T10	21
valid_sources[0x2b]	228016	1			T10	15		T11	20		T12	1
valid_sources[0x2c]	224633	1			T15	1		T10	14		T11	7
valid_sources[0x2d]	225946	1			T10	52		T11	4		T12	2
valid_sources[0x2e]	226595	1			T15	1		T10	5		T11	4
valid_sources[0x2f]	440857	1			T15	2		T10	15		T11	1
valid_sources[0x30]	225006	1			T10	14		T12	1		T16	8
valid_sources[0x31]	227450	1			T10	27		T11	3		T12	1
valid_sources[0x32]	223506	1			T15	1		T10	21		T11	8
valid_sources[0x33]	938980	1			T15	3		T10	8		T12	1
valid_sources[0x34]	226287	1			T15	1		T10	15		T11	4
valid_sources[0x35]	225773	1			T15	2		T10	13		T11	1
valid_sources[0x36]	225957	1			T10	23		T11	1		T12	1
valid_sources[0x37]	225537	1			T15	1		T10	30		T11	9
valid_sources[0x38]	227913	1			T15	1		T10	31		T11	2
valid_sources[0x39]	225990	1			T15	1		T10	21		T11	1
valid_sources[0x3a]	228144	1			T10	18		T11	5		T12	1
valid_sources[0x3b]	225731	1			T15	1		T10	14		T11	9
valid_sources[0x3c]	224532	1			T10	16		T11	3		T16	2
valid_sources[0x3d]	951380	1			T10	27		T11	9		T12	1
valid_sources[0x3e]	228296	1			T2	2448		T10	15		T5	1
valid_sources[0x3f]	238455	1			T10	22		T11	2		T5	2
valid_sources[0x40]	228642	1			T15	1		T10	28		T11	2
valid_sources[0x41]	225901	1			T15	1		T10	27		T11	6
valid_sources[0x42]	230935	1			T15	3		T10	25		T11	5
valid_sources[0x43]	442795	1			T10	8		T5	2		T6	3
valid_sources[0x44]	228542	1			T10	19		T11	2		T12	3
valid_sources[0x45]	517980	1			T15	1		T10	21		T12	1
valid_sources[0x46]	227363	1			T10	35		T11	10		T12	1
valid_sources[0x47]	227773	1			T15	1		T10	25		T11	3
valid_sources[0x48]	226011	1			T10	12		T11	1		T5	3
valid_sources[0x49]	227453	1			T15	5		T10	21		T11	17
valid_sources[0x4a]	228748	1			T15	1		T10	21		T11	1
valid_sources[0x4b]	228076	1			T10	18		T11	7		T12	1
valid_sources[0x4c]	230576	1			T15	3		T10	12		T11	1
valid_sources[0x4d]	228433	1			T15	4		T10	12		T11	5
valid_sources[0x4e]	225862	1			T15	1		T10	19		T12	1
valid_sources[0x4f]	235610	1			T15	1		T10	15		T11	2
valid_sources[0x50]	225331	1			T15	1		T10	29		T12	4
valid_sources[0x51]	233113	1			T15	1		T10	18		T11	1
valid_sources[0x52]	493624	1			T15	1		T10	12		T11	2
valid_sources[0x53]	229835	1			T10	15		T11	1		T12	3
valid_sources[0x54]	234018	1			T15	1		T10	21		T12	1
valid_sources[0x55]	227706	1			T15	1		T10	26		T11	13
valid_sources[0x56]	270274	1			T15	2		T10	38		T12	2
valid_sources[0x57]	503155	1			T15	2		T10	21		T5	3
valid_sources[0x58]	226157	1			T15	1		T10	26		T11	6
valid_sources[0x59]	514101	1			T15	1		T10	12		T11	5
valid_sources[0x5a]	224617	1			T15	3		T10	24		T5	1
valid_sources[0x5b]	231100	1			T15	1		T10	18		T11	1
valid_sources[0x5c]	227082	1			T15	1		T10	11		T12	1
valid_sources[0x5d]	236732	1			T10	10		T11	1		T12	1
valid_sources[0x5e]	226958	1			T10	3		T11	5		T12	1
valid_sources[0x5f]	224622	1			T15	4		T10	15		T11	3
valid_sources[0x60]	230175	1			T15	2		T10	13		T11	1
valid_sources[0x61]	228314	1			T15	1		T10	17		T12	2
valid_sources[0x62]	224046	1			T15	2		T10	8		T11	3
valid_sources[0x63]	223266	1			T15	1		T10	17		T11	5
valid_sources[0x64]	223774	1			T10	16		T11	14		T12	1
valid_sources[0x65]	226878	1			T15	3		T10	26		T11	3
valid_sources[0x66]	227800	1			T15	1		T10	22		T11	10
valid_sources[0x67]	225925	1			T15	4		T10	23		T11	2
valid_sources[0x68]	230534	1			T15	2		T10	22		T11	11
valid_sources[0x69]	227025	1			T15	2		T10	17		T11	3
valid_sources[0x6a]	544519	1			T10	12		T12	2		T5	3
valid_sources[0x6b]	444077	1			T10	9		T11	6		T12	1
valid_sources[0x6c]	225769	1			T15	3		T10	16		T11	8
valid_sources[0x6d]	232083	1			T15	3		T10	9		T11	6
valid_sources[0x6e]	223872	1			T15	2		T10	19		T11	8
valid_sources[0x6f]	226730	1			T15	2		T10	16		T11	7
valid_sources[0x70]	237324	1			T10	1		T12	1		T16	16
valid_sources[0x71]	311087	1			T15	2		T10	22		T11	3
valid_sources[0x72]	225640	1			T15	4		T10	16		T11	5
valid_sources[0x73]	265198	1			T15	2		T10	27		T11	5
valid_sources[0x74]	227628	1			T15	2		T10	8		T11	4
valid_sources[0x75]	226585	1			T15	4		T10	35		T11	2
valid_sources[0x76]	228056	1			T10	19		T12	2		T5	7
valid_sources[0x77]	231015	1			T15	1		T10	27		T11	6
valid_sources[0x78]	543107	1			T15	2		T10	37		T12	1
valid_sources[0x79]	224063	1			T15	1		T10	22		T12	2
valid_sources[0x7a]	228021	1			T15	3		T10	19		T12	2
valid_sources[0x7b]	228206	1			T15	3		T10	26		T11	2
valid_sources[0x7c]	223961	1			T15	4		T10	24		T11	2
valid_sources[0x7d]	225111	1			T15	2		T10	14		T11	4
valid_sources[0x7e]	680565	1			T15	6		T10	32		T12	1
valid_sources[0x7f]	225859	1			T15	4		T10	15		T11	2
valid_sources[0x80]	226137	1			T15	3		T10	14		T11	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5647245

1

T1

58

T2

370

T3

140

values[0x0]

all_enables

biggest_size

11714506

1

T1

172

T2

299

T3

415

values[0x1]

all_enables

biggest_size

6638383

1

T1

104

T2

168

T3

220