Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T12,T28
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	11712	0	0
DisabledNoTrigBkwd_A	2147483647	596691	0	0
DisabledNoTrigFwd_A	2147483647	1279760255	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11712	0	0
T5	30356	0	0	0
T6	113821	0	0	0
T8	15511	0	0	0
T12	8002	609	0	0
T13	186260	0	0	0
T14	28693	0	0	0
T15	3996	639	0	0
T16	45494	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T28	4979	681	0	0
T36	124474	0	0	0
T37	70547	0	0	0
T68	0	723	0	0
T71	0	580	0	0
T82	0	635	0	0
T85	8059	0	0	0
T199	0	931	0	0
T220	268711	0	0	0
T223	0	461	0	0
T224	1344	586	0	0
T225	0	702	0	0
T226	0	339	0	0
T227	0	338	0	0
T228	0	368	0	0
T229	0	823	0	0
T230	0	631	0	0
T231	0	883	0	0
T232	0	709	0	0
T233	0	408	0	0
T234	0	345	0	0
T235	0	321	0	0
T236	94499	0	0	0
T237	4298	0	0	0
T238	675527	0	0	0
T239	777066	0	0	0
T240	658248	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	596691	0	0
T2	8902	4	0	0
T3	20245	1	0	0
T4	31878	0	0	0
T5	45534	0	0	0
T6	227642	0	0	0
T7	46256	0	0	0
T8	31022	0	0	0
T10	33194	0	0	0
T11	20834	9	0	0
T12	12003	9	0	0
T13	279390	27	0	0
T14	57386	14	0	0
T15	7992	6	0	0
T16	68241	9	0	0
T17	15876	0	0	0
T26	17226	2	0	0
T27	36552	4	0	0
T28	9958	2	0	0
T29	95773	25	0	0
T30	50646	0	0	0
T31	0	140	0	0
T33	0	23	0	0
T38	0	82	0	0
T39	0	2	0	0
T41	0	11	0	0
T44	0	86	0	0
T45	0	246	0	0
T46	0	8	0	0
T82	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1279760255	0	0
T1	18920	11623	0	0
T2	35608	32436	0	0
T3	80980	62505	0	0
T4	63756	11560	0	0
T10	66388	40920	0	0
T11	41668	34095	0	0
T12	16004	12777	0	0
T15	15984	12784	0	0
T17	31752	23512	0	0
T30	101292	77743	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T224,T227,T229
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T11

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	557183493	1747	0	0
DisabledNoTrigBkwd_A	557183493	150963	0	0
DisabledNoTrigFwd_A	557183493	302752195	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	1747	0	0
T36	124474	0	0	0
T37	70547	0	0	0
T85	8059	0	0	0
T220	268711	0	0	0
T224	1344	586	0	0
T227	0	338	0	0
T229	0	823	0	0
T236	94499	0	0	0
T237	4298	0	0	0
T238	675527	0	0	0
T239	777066	0	0	0
T240	658248	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	150963	0	0
T2	8902	4	0	0
T3	20245	1	0	0
T4	15939	0	0	0
T5	15178	0	0	0
T10	16597	0	0	0
T11	10417	9	0	0
T12	4001	0	0	0
T13	0	6	0	0
T14	0	2	0	0
T15	3996	0	0	0
T17	7938	0	0	0
T26	0	2	0	0
T29	0	8	0	0
T30	25323	0	0	0
T31	0	23	0	0
T38	0	82	0	0
T41	0	6	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	302752195	0	0
T1	4730	1769	0	0
T2	8902	5976	0	0
T3	20245	2064	0	0
T4	15939	2890	0	0
T10	16597	12794	0	0
T11	10417	3015	0	0
T12	4001	3162	0	0
T15	3996	3169	0	0
T17	7938	5781	0	0
T30	25323	2023	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T12
1	0	Covered	T1,T10,T17
1	1	Covered	T1,T12,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T226,T228
1	1	Covered	T1,T12,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T5,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	557183493	3151	0	0
DisabledNoTrigBkwd_A	557183493	123764	0	0
DisabledNoTrigFwd_A	557183493	342788293	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	3151	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	0	0	0
T12	4001	609	0	0
T13	93130	0	0	0
T14	28693	0	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T28	4979	0	0	0
T226	0	339	0	0
T228	0	368	0	0
T230	0	631	0	0
T231	0	883	0	0
T235	0	321	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	123764	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	0	0	0
T12	4001	9	0	0
T13	93130	1	0	0
T14	28693	1	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T28	4979	0	0	0
T29	0	8	0	0
T31	0	37	0	0
T33	0	23	0	0
T39	0	2	0	0
T41	0	2	0	0
T45	0	86	0	0
T46	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	342788293	0	0
T1	4730	1773	0	0
T2	8902	8820	0	0
T3	20245	20147	0	0
T4	15939	2890	0	0
T10	16597	16545	0	0
T11	10417	10360	0	0
T12	4001	3187	0	0
T15	3996	3186	0	0
T17	7938	7858	0	0
T30	25323	25240	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T15,T10,T12
1	0	Covered	T1,T17,T16
1	1	Covered	T15,T10,T16

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T71,T232
1	1	Covered	T15,T10,T16

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T15,T10,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T16,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	557183493	2681	0	0
DisabledNoTrigBkwd_A	557183493	181775	0	0
DisabledNoTrigFwd_A	557183493	315148740	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	2681	0	0
T4	15939	0	0	0
T5	15178	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T13	93130	0	0	0
T15	3996	639	0	0
T16	22747	0	0	0
T17	7938	0	0	0
T30	25323	0	0	0
T71	0	580	0	0
T232	0	709	0	0
T233	0	408	0	0
T234	0	345	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	181775	0	0
T4	15939	0	0	0
T5	15178	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T13	93130	18	0	0
T14	0	2	0	0
T15	3996	6	0	0
T16	22747	1	0	0
T17	7938	0	0	0
T27	0	3	0	0
T29	0	9	0	0
T30	25323	0	0	0
T31	0	23	0	0
T44	0	16	0	0
T45	0	80	0	0
T46	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	315148740	0	0
T1	4730	4634	0	0
T2	8902	8820	0	0
T3	20245	20147	0	0
T4	15939	2890	0	0
T10	16597	640	0	0
T11	10417	10360	0	0
T12	4001	3202	0	0
T15	3996	3206	0	0
T17	7938	7858	0	0
T30	25323	25240	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T10
1	0	Covered	T10,T16,T13
1	1	Covered	T1,T10,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T28,T82,T68
1	1	Covered	T1,T10,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T13,T27

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	557183493	4133	0	0
DisabledNoTrigBkwd_A	557183493	140189	0	0
DisabledNoTrigFwd_A	557183493	319071027	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	4133	0	0
T7	46256	0	0	0
T9	44675	0	0	0
T28	4979	681	0	0
T29	95773	0	0	0
T31	69603	0	0	0
T38	106873	0	0	0
T41	24135	0	0	0
T44	75098	0	0	0
T68	0	723	0	0
T78	53350	0	0	0
T82	3193	635	0	0
T199	0	931	0	0
T223	0	461	0	0
T225	0	702	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	140189	0	0
T6	113821	0	0	0
T7	46256	0	0	0
T8	15511	0	0	0
T13	93130	2	0	0
T14	28693	9	0	0
T16	22747	8	0	0
T26	8613	0	0	0
T27	18276	1	0	0
T28	4979	2	0	0
T29	95773	0	0	0
T31	0	57	0	0
T41	0	3	0	0
T44	0	70	0	0
T45	0	80	0	0
T82	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	319071027	0	0
T1	4730	3447	0	0
T2	8902	8820	0	0
T3	20245	20147	0	0
T4	15939	2890	0	0
T10	16597	10941	0	0
T11	10417	10360	0	0
T12	4001	3226	0	0
T15	3996	3223	0	0
T17	7938	2015	0	0
T30	25323	25240	0	0