Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	100.00	89.36		70.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T3 T15 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T3 T15 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T3 T15 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T17 T13 
159        1/1                    state_d = TimeoutSt;
           Tests:       T1 T17 T13 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T1 T17 T13 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T1 T17 T13 
172        1/1                    state_d    = Phase0St;
           Tests:       T29 T31 T32 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T29 T31 T32 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T29 T31 T32 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T29 T31 T32 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T1 T17 T13 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T17 T13 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T1 T17 T13 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T17 T13 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T15 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T2 T3 T15 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T2 T3 T15 
190        1/1                  esc_state_o = Phase0;
           Tests:       T2 T3 T15 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T2 T3 T15 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T2 T3 T15 
194        1/1                    state_d = IdleSt;
           Tests:       T13 T33 T34 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T33 T34 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T13 T33 T34 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T15 
198        1/1                    state_d = Phase1St;
           Tests:       T2 T3 T15 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T15 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T3 T15 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T15 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T2 T3 T15 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T2 T3 T15 
207        1/1                  esc_state_o = Phase1;
           Tests:       T2 T3 T15 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T2 T3 T15 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T2 T3 T15 
211        1/1                    state_d = IdleSt;
           Tests:       T35 T36 T37 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T36 T37 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T36 T37 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T15 
215        1/1                    state_d = Phase2St;
           Tests:       T2 T3 T15 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T15 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T3 T15 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T15 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T2 T3 T15 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T2 T3 T15 
224        1/1                  esc_state_o = Phase2;
           Tests:       T2 T3 T15 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T2 T3 T15 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T2 T3 T15 
229        1/1                    state_d = IdleSt;
           Tests:       T13 T29 T38 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T29 T38 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T13 T29 T38 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T15 
233        1/1                    state_d = Phase3St;
           Tests:       T2 T3 T15 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T15 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T15 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T2 T3 T15 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T2 T3 T15 
241        1/1                  esc_state_o = Phase3;
           Tests:       T2 T3 T15 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T2 T3 T15 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T2 T3 T15 
245        1/1                    state_d = IdleSt;
           Tests:       T13 T39 T35 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T39 T35 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T13 T39 T35 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T15 
249        1/1                    state_d = TerminalSt;
           Tests:       T2 T3 T15 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T15 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T3 T15 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T2 T3 T15 
259        1/1                  esc_state_o = Terminal;
           Tests:       T2 T3 T15 
260        1/1                  if (clr_i) begin
           Tests:       T2 T3 T15 
261        1/1                    state_d = IdleSt;
           Tests:       T3 T13 T26 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T15,T10
1	1	0	Covered	T1,T10,T17
1	1	1	Covered	T1,T17,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T13
0	1	Covered	T29,T31,T32
1	0	Covered	T29,T40,T34

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T17,T13
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T29,T40,T34

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T13
1	0	Not Covered
1	1	Covered	T29,T31,T32

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T15,T11,T12

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T15,T11
1	Covered	T3,T16,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T13,T31,T41

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T15,T11
1	Covered	T2,T13,T27

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T4,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T15,T12,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T2,T15,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T2,T15,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T2,T3,T15

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T15
Phase1St	198	Covered	T2,T3,T15
Phase2St	215	Covered	T2,T3,T15
Phase3St	233	Covered	T2,T3,T15
TerminalSt	249	Covered	T2,T3,T15
TimeoutSt	159	Covered	T1,T17,T13

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T4,T8,T9
IdleSt->Phase0St	152	Covered	T2,T3,T15
IdleSt->TimeoutSt	159	Covered	T1,T17,T13
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T13,T33,T34
Phase0St->Phase1St	198	Covered	T2,T3,T15
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T35,T36,T37
Phase1St->Phase2St	215	Covered	T2,T3,T15
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T13,T29,T38
Phase2St->Phase3St	233	Covered	T2,T3,T15
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T13,T39,T35
Phase3St->TerminalSt	249	Covered	T2,T3,T15
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T3,T13,T26
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T17,T13
TimeoutSt->Phase0St	172	Covered	T29,T31,T32

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T29,T31,T32
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T13
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T13,T33,T34
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T35,T36,T37
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T13,T29,T38
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T13,T39,T35
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T13,T26
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	802	0	0
CheckAccumTrig0_A	2147483647	2170	0	0
CheckAccumTrig1_A	2147483647	103	0	0
CheckClr_A	2147483647	1031	0	0
CheckEn_A	2147483647	981885812	0	0
CheckPhase0_A	2147483647	2398	0	0
CheckPhase1_A	2147483647	2341	0	0
CheckPhase2_A	2147483647	2308	0	0
CheckPhase3_A	2147483647	2258	0	0
CheckTimeout0_A	2147483647	3314	0	0
CheckTimeoutSt1_A	2147483647	329815	0	0
CheckTimeoutSt2_A	2147483647	2996	0	0
CheckTimeoutStTrig_A	2147483647	199	0	0
ErrorStAllEscAsserted_A	2147483647	4418	0	0
ErrorStIsTerminal_A	2147483647	3578	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	802	0	0
T4	63756	137	0	0
T5	60712	0	0	0
T6	455284	0	0	0
T8	62044	103	0	0
T9	0	244	0	0
T12	16004	0	0	0
T13	372520	0	0	0
T16	90988	0	0	0
T26	34452	0	0	0
T27	73104	0	0	0
T30	101292	0	0	0
T42	0	229	0	0
T43	0	89	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2170	0	0
T2	8902	1	0	0
T3	20245	1	0	0
T4	31878	0	0	0
T5	45534	0	0	0
T6	227642	0	0	0
T7	46256	0	0	0
T8	31022	0	0	0
T10	33194	0	0	0
T11	20834	1	0	0
T12	12003	1	0	0
T13	279390	11	0	0
T14	57386	4	0	0
T15	7992	1	0	0
T16	68241	2	0	0
T17	15876	0	0	0
T18	0	1	0	0
T26	17226	2	0	0
T27	36552	2	0	0
T28	9958	1	0	0
T29	95773	6	0	0
T30	50646	0	0	0
T31	0	8	0	0
T33	0	2	0	0
T38	0	7	0	0
T39	0	2	0	0
T41	0	3	0	0
T44	0	2	0	0
T45	0	4	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	103	0	0
T22	14846	0	0	0
T29	95773	1	0	0
T33	111353	0	0	0
T34	0	2	0	0
T39	55982	0	0	0
T40	22733	1	0	0
T42	44852	0	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	864761	1	0	0
T51	158865	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	3	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	24163	0	0	0
T66	180688	0	0	0
T67	56553	0	0	0
T68	3081	0	0	0
T69	4826	0	0	0
T70	758900	0	0	0
T71	1289	0	0	0
T72	921066	0	0	0
T73	9805	0	0	0
T74	20981	0	0	0
T75	28080	0	0	0
T76	21209	0	0	0
T77	17226	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1031	0	0
T3	20245	1	0	0
T4	15939	0	0	0
T5	15178	0	0	0
T7	92512	0	0	0
T9	44675	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T13	93130	7	0	0
T14	0	1	0	0
T15	3996	0	0	0
T16	22747	0	0	0
T17	7938	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T29	191546	7	0	0
T30	25323	0	0	0
T31	139206	4	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	3	0	0
T36	0	5	0	0
T37	0	3	0	0
T38	106873	6	0	0
T39	0	3	0	0
T41	24135	0	0	0
T44	75098	0	0	0
T45	182537	3	0	0
T46	0	1	0	0
T65	0	2	0	0
T78	53350	3	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	3	0	0
T82	3193	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	981885812	0	0
T1	18920	11621	0	0
T2	35608	32433	0	0
T3	80980	62502	0	0
T4	1316	968	0	0
T10	66388	40917	0	0
T11	41668	34092	0	0
T12	16004	12777	0	0
T15	15984	12784	0	0
T17	31752	23510	0	0
T30	101292	77740	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2398	0	0
T2	8902	1	0	0
T3	20245	1	0	0
T4	31878	0	0	0
T5	45534	0	0	0
T6	227642	0	0	0
T7	46256	0	0	0
T8	31022	0	0	0
T10	33194	0	0	0
T11	20834	1	0	0
T12	12003	1	0	0
T13	279390	9	0	0
T14	57386	4	0	0
T15	7992	1	0	0
T16	68241	2	0	0
T17	15876	0	0	0
T26	17226	2	0	0
T27	36552	2	0	0
T28	9958	1	0	0
T29	95773	9	0	0
T30	50646	0	0	0
T31	0	9	0	0
T33	0	1	0	0
T38	0	7	0	0
T39	0	2	0	0
T41	0	3	0	0
T44	0	2	0	0
T45	0	5	0	0
T46	0	2	0	0
T82	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2341	0	0
T2	8902	1	0	0
T3	20245	1	0	0
T4	31878	0	0	0
T5	45534	0	0	0
T6	227642	0	0	0
T7	46256	0	0	0
T8	31022	0	0	0
T10	33194	0	0	0
T11	20834	1	0	0
T12	12003	1	0	0
T13	279390	9	0	0
T14	57386	4	0	0
T15	7992	1	0	0
T16	68241	2	0	0
T17	15876	0	0	0
T26	17226	2	0	0
T27	36552	2	0	0
T28	9958	1	0	0
T29	95773	9	0	0
T30	50646	0	0	0
T31	0	9	0	0
T33	0	1	0	0
T38	0	7	0	0
T39	0	2	0	0
T41	0	3	0	0
T44	0	2	0	0
T45	0	5	0	0
T46	0	2	0	0
T82	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2308	0	0
T2	8902	1	0	0
T3	20245	1	0	0
T4	31878	0	0	0
T5	45534	0	0	0
T6	227642	0	0	0
T7	46256	0	0	0
T8	31022	0	0	0
T10	33194	0	0	0
T11	20834	1	0	0
T12	12003	1	0	0
T13	279390	8	0	0
T14	57386	4	0	0
T15	7992	1	0	0
T16	68241	2	0	0
T17	15876	0	0	0
T26	17226	2	0	0
T27	36552	2	0	0
T28	9958	1	0	0
T29	95773	8	0	0
T30	50646	0	0	0
T31	0	9	0	0
T33	0	1	0	0
T38	0	5	0	0
T39	0	1	0	0
T41	0	3	0	0
T44	0	2	0	0
T45	0	5	0	0
T46	0	2	0	0
T82	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2258	0	0
T2	8902	1	0	0
T3	20245	1	0	0
T4	31878	0	0	0
T5	45534	0	0	0
T6	227642	0	0	0
T7	46256	0	0	0
T8	31022	0	0	0
T10	33194	0	0	0
T11	20834	1	0	0
T12	12003	1	0	0
T13	279390	7	0	0
T14	57386	4	0	0
T15	7992	1	0	0
T16	68241	2	0	0
T17	15876	0	0	0
T26	17226	2	0	0
T27	36552	2	0	0
T28	9958	1	0	0
T29	95773	8	0	0
T30	50646	0	0	0
T31	0	9	0	0
T33	0	1	0	0
T38	0	5	0	0
T39	0	1	0	0
T41	0	3	0	0
T44	0	2	0	0
T45	0	5	0	0
T46	0	2	0	0
T82	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3314	0	0
T1	4730	1	0	0
T2	8902	0	0	0
T3	20245	0	0	0
T4	15939	0	0	0
T7	92512	0	0	0
T9	44675	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T13	93130	2	0	0
T14	0	2	0	0
T15	3996	0	0	0
T17	7938	1	0	0
T27	0	1	0	0
T29	191546	9	0	0
T30	25323	0	0	0
T31	139206	3	0	0
T32	0	14	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	106873	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	24135	0	0	0
T44	75098	0	0	0
T45	182537	2	0	0
T46	0	3	0	0
T48	0	1	0	0
T65	0	4	0	0
T78	53350	4	0	0
T79	0	4	0	0
T81	0	9	0	0
T82	3193	0	0	0
T83	0	20	0	0
T84	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	329815	0	0
T1	4730	83	0	0
T2	8902	0	0	0
T3	20245	0	0	0
T4	15939	0	0	0
T7	92512	0	0	0
T9	44675	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T13	93130	165	0	0
T14	0	358	0	0
T15	3996	0	0	0
T17	7938	125	0	0
T27	0	7	0	0
T29	191546	1614	0	0
T30	25323	0	0	0
T31	139206	742	0	0
T32	0	2807	0	0
T34	0	53	0	0
T35	0	97	0	0
T36	0	52	0	0
T38	106873	0	0	0
T39	0	299	0	0
T41	24135	0	0	0
T44	75098	0	0	0
T45	182537	312	0	0
T46	0	434	0	0
T48	0	61	0	0
T65	0	336	0	0
T78	53350	458	0	0
T79	0	660	0	0
T81	0	1959	0	0
T82	3193	0	0	0
T83	0	3477	0	0
T84	0	153	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2996	0	0
T1	4730	1	0	0
T2	8902	0	0	0
T3	20245	0	0	0
T4	15939	0	0	0
T7	92512	0	0	0
T9	44675	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T13	93130	2	0	0
T14	0	2	0	0
T15	3996	0	0	0
T17	7938	1	0	0
T27	0	1	0	0
T29	191546	6	0	0
T30	25323	0	0	0
T31	139206	2	0	0
T32	0	13	0	0
T34	0	2	0	0
T35	0	1	0	0
T38	106873	0	0	0
T39	0	2	0	0
T41	24135	0	0	0
T44	75098	0	0	0
T45	182537	2	0	0
T46	0	1	0	0
T49	0	2	0	0
T78	53350	4	0	0
T79	0	3	0	0
T81	0	8	0	0
T82	3193	0	0	0
T83	0	20	0	0
T84	0	4	0	0
T85	0	1	0	0
T86	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	199	0	0
T7	46256	0	0	0
T9	89350	0	0	0
T21	36711	0	0	0
T29	95773	2	0	0
T31	139206	1	0	0
T32	269514	1	0	0
T33	111353	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	213746	0	0	0
T40	22733	0	0	0
T41	48270	0	0	0
T42	44852	0	0	0
T44	150196	0	0	0
T45	365074	0	0	0
T46	20406	2	0	0
T48	0	1	0	0
T51	0	2	0	0
T53	0	3	0	0
T65	48326	4	0	0
T66	180688	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	106700	0	0	0
T79	0	2	0	0
T81	0	1	0	0
T82	6386	0	0	0
T83	89583	0	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	6	0	0
T92	147442	0	0	0
T93	6031	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4418	0	0
T4	63756	621	0	0
T5	60712	0	0	0
T6	455284	0	0	0
T8	62044	599	0	0
T9	0	1284	0	0
T12	16004	0	0	0
T13	372520	0	0	0
T16	90988	0	0	0
T26	34452	0	0	0
T27	73104	0	0	0
T30	101292	0	0	0
T42	0	1228	0	0
T43	0	686	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3578	0	0
T4	63756	501	0	0
T5	60712	0	0	0
T6	455284	0	0	0
T8	62044	479	0	0
T9	0	1044	0	0
T12	16004	0	0	0
T13	372520	0	0	0
T16	90988	0	0	0
T26	34452	0	0	0
T27	73104	0	0	0
T30	101292	0	0	0
T42	0	988	0	0
T43	0	566	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18920	18536	0	0
T2	35608	35280	0	0
T3	80980	80588	0	0
T4	344	0	0	0
T5	0	60208	0	0
T10	66388	66180	0	0
T11	41668	41440	0	0
T12	16004	15636	0	0
T15	15984	15704	0	0
T17	31752	31432	0	0
T30	101292	100960	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18920	18536	0	0
T2	35608	35280	0	0
T3	80980	80588	0	0
T4	63756	11560	0	0
T10	66388	66180	0	0
T11	41668	41440	0	0
T12	16004	15636	0	0
T15	15984	15704	0	0
T17	31752	31432	0	0
T30	101292	100960	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T3 T11 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T3 T11 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T3 T11 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T17 T14 
159        1/1                    state_d = TimeoutSt;
           Tests:       T1 T17 T14 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T1 T17 T14 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T1 T17 T14 
172        1/1                    state_d    = Phase0St;
           Tests:       T32 T46 T40 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T32 T46 T40 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T32 T46 T40 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T32 T46 T40 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T1 T17 T14 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T17 T14 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T1 T17 T14 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T17 T14 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T11 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T2 T3 T11 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T2 T3 T11 
190        1/1                  esc_state_o = Phase0;
           Tests:       T2 T3 T11 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T2 T3 T11 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T2 T3 T11 
194        1/1                    state_d = IdleSt;
           Tests:       T34 T94 T95 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T94 T95 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T34 T94 T95 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T11 
198        1/1                    state_d = Phase1St;
           Tests:       T2 T3 T11 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T11 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T3 T11 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T11 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T2 T3 T11 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T2 T3 T11 
207        1/1                  esc_state_o = Phase1;
           Tests:       T2 T3 T11 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T2 T3 T11 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T2 T3 T11 
211        1/1                    state_d = IdleSt;
           Tests:       T96 T97 T98 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T96 T97 T98 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T96 T97 T98 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T11 
215        1/1                    state_d = Phase2St;
           Tests:       T2 T3 T11 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T11 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T3 T11 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T11 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T2 T3 T11 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T2 T3 T11 
224        1/1                  esc_state_o = Phase2;
           Tests:       T2 T3 T11 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T2 T3 T11 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T2 T3 T11 
229        1/1                    state_d = IdleSt;
           Tests:       T38 T45 T51 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T38 T45 T51 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T38 T45 T51 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T11 
233        1/1                    state_d = Phase3St;
           Tests:       T2 T3 T11 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T11 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T11 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T2 T3 T11 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T2 T3 T11 
241        1/1                  esc_state_o = Phase3;
           Tests:       T2 T3 T11 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T2 T3 T11 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T2 T3 T11 
245        1/1                    state_d = IdleSt;
           Tests:       T99 T48 T100 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T99 T48 T100 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T99 T48 T100 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T11 
249        1/1                    state_d = TerminalSt;
           Tests:       T2 T3 T11 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T11 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T3 T11 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T2 T3 T11 
259        1/1                  esc_state_o = Terminal;
           Tests:       T2 T3 T11 
260        1/1                  if (clr_i) begin
           Tests:       T2 T3 T11 
261        1/1                    state_d = IdleSt;
           Tests:       T3 T26 T14 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T11

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T30,T26
1	1	0	Covered	T1,T10,T13
1	1	1	Covered	T1,T17,T14

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T14
0	1	Covered	T32,T46,T65
1	0	Covered	T40,T47,T48

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T17,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T40,T47,T48

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T14
1	0	Not Covered
1	1	Covered	T32,T46,T65

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T13
1	Covered	T11,T26,T38

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T13
1	Covered	T3,T29,T78

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T13,T31,T45

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T11,T13
1	Covered	T2,T14,T31

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T4,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T26,T31,T78

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T2,T11,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T2,T11,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T2,T3,T11

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T11
Phase1St	198	Covered	T2,T3,T11
Phase2St	215	Covered	T2,T3,T11
Phase3St	233	Covered	T2,T3,T11
TerminalSt	249	Covered	T2,T3,T11
TimeoutSt	159	Covered	T1,T17,T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T8,T9
IdleSt->Phase0St	152	Covered	T2,T3,T11
IdleSt->TimeoutSt	159	Covered	T1,T17,T14
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T34,T35,T49
Phase0St->Phase1St	198	Covered	T2,T3,T11
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T49,T96,T97
Phase1St->Phase2St	215	Covered	T2,T3,T11
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T38,T45,T51
Phase2St->Phase3St	233	Covered	T2,T3,T11
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T99,T48,T100
Phase3St->TerminalSt	249	Covered	T2,T3,T11
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T26,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T17,T14
TimeoutSt->Phase0St	172	Covered	T32,T46,T40

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T14
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T32,T46,T40
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T14
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T34,T94,T95
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T96,T97,T98
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T38,T45,T51
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T99,T48,T100
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T26,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	557183493	174	0	0
CheckAccumTrig0_A	557183493	786	0	0
CheckAccumTrig1_A	557183493	38	0	0
CheckClr_A	557183493	391	0	0
CheckEn_A	557042185	224541545	0	0
CheckPhase0_A	557183493	856	0	0
CheckPhase1_A	557183493	835	0	0
CheckPhase2_A	557183493	824	0	0
CheckPhase3_A	557183493	800	0	0
CheckTimeout0_A	557183493	1109	0	0
CheckTimeoutSt1_A	557183493	104864	0	0
CheckTimeoutSt2_A	557183493	1006	0	0
CheckTimeoutStTrig_A	557183493	59	0	0
ErrorStAllEscAsserted_A	557183493	1118	0	0
ErrorStIsTerminal_A	557183493	908	0	0
EscStateOut_A	557041145	556972099	0	0
u_state_regs_A	557183493	557025290	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	174	0	0
T4	15939	38	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	27	0	0
T9	0	58	0	0
T12	4001	0	0	0
T13	93130	0	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T30	25323	0	0	0
T42	0	35	0	0
T43	0	16	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	786	0	0
T2	8902	1	0	0
T3	20245	1	0	0
T4	15939	0	0	0
T5	15178	0	0	0
T10	16597	0	0	0
T11	10417	1	0	0
T12	4001	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	3996	0	0	0
T17	7938	0	0	0
T26	0	2	0	0
T29	0	2	0	0
T30	25323	0	0	0
T31	0	2	0	0
T38	0	7	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	38	0	0
T22	14846	0	0	0
T33	111353	0	0	0
T39	55982	0	0	0
T40	22733	1	0	0
T42	44852	0	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T65	24163	0	0	0
T66	180688	0	0	0
T67	56553	0	0	0
T68	3081	0	0	0
T69	4826	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	391	0	0
T3	20245	1	0	0
T4	15939	0	0	0
T5	15178	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T14	0	1	0	0
T15	3996	0	0	0
T16	22747	0	0	0
T17	7938	0	0	0
T26	0	1	0	0
T29	0	1	0	0
T30	25323	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T38	0	6	0	0
T45	0	2	0	0
T46	0	1	0	0
T78	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557042185	224541545	0	0
T1	4730	1769	0	0
T2	8902	5976	0	0
T3	20245	2064	0	0
T4	329	242	0	0
T10	16597	12793	0	0
T11	10417	3015	0	0
T12	4001	3162	0	0
T15	3996	3169	0	0
T17	7938	5781	0	0
T30	25323	2023	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	856	0	0
T2	8902	1	0	0
T3	20245	1	0	0
T4	15939	0	0	0
T5	15178	0	0	0
T10	16597	0	0	0
T11	10417	1	0	0
T12	4001	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	3996	0	0	0
T17	7938	0	0	0
T26	0	2	0	0
T29	0	2	0	0
T30	25323	0	0	0
T31	0	2	0	0
T38	0	7	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	835	0	0
T2	8902	1	0	0
T3	20245	1	0	0
T4	15939	0	0	0
T5	15178	0	0	0
T10	16597	0	0	0
T11	10417	1	0	0
T12	4001	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	3996	0	0	0
T17	7938	0	0	0
T26	0	2	0	0
T29	0	2	0	0
T30	25323	0	0	0
T31	0	2	0	0
T38	0	7	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	824	0	0
T2	8902	1	0	0
T3	20245	1	0	0
T4	15939	0	0	0
T5	15178	0	0	0
T10	16597	0	0	0
T11	10417	1	0	0
T12	4001	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	3996	0	0	0
T17	7938	0	0	0
T26	0	2	0	0
T29	0	2	0	0
T30	25323	0	0	0
T31	0	2	0	0
T38	0	5	0	0
T41	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	800	0	0
T2	8902	1	0	0
T3	20245	1	0	0
T4	15939	0	0	0
T5	15178	0	0	0
T10	16597	0	0	0
T11	10417	1	0	0
T12	4001	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	3996	0	0	0
T17	7938	0	0	0
T26	0	2	0	0
T29	0	2	0	0
T30	25323	0	0	0
T31	0	2	0	0
T38	0	5	0	0
T41	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	1109	0	0
T1	4730	1	0	0
T2	8902	0	0	0
T3	20245	0	0	0
T4	15939	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T14	0	2	0	0
T15	3996	0	0	0
T17	7938	1	0	0
T29	0	1	0	0
T30	25323	0	0	0
T32	0	2	0	0
T40	0	1	0	0
T46	0	2	0	0
T65	0	2	0	0
T78	0	4	0	0
T83	0	11	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	104864	0	0
T1	4730	83	0	0
T2	8902	0	0	0
T3	20245	0	0	0
T4	15939	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T14	0	358	0	0
T15	3996	0	0	0
T17	7938	125	0	0
T29	0	221	0	0
T30	25323	0	0	0
T32	0	204	0	0
T39	0	160	0	0
T46	0	143	0	0
T65	0	154	0	0
T78	0	458	0	0
T83	0	1897	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	1006	0	0
T1	4730	1	0	0
T2	8902	0	0	0
T3	20245	0	0	0
T4	15939	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T14	0	2	0	0
T15	3996	0	0	0
T17	7938	1	0	0
T29	0	1	0	0
T30	25323	0	0	0
T32	0	1	0	0
T39	0	1	0	0
T46	0	1	0	0
T78	0	4	0	0
T83	0	11	0	0
T84	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	59	0	0
T21	36711	0	0	0
T32	134757	1	0	0
T33	111353	0	0	0
T40	22733	0	0	0
T42	44852	0	0	0
T46	20406	1	0	0
T65	24163	2	0	0
T75	0	1	0	0
T77	0	1	0	0
T83	89583	0	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	5	0	0
T92	73721	0	0	0
T93	6031	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	1118	0	0
T4	15939	146	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	155	0	0
T9	0	336	0	0
T12	4001	0	0	0
T13	93130	0	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T30	25323	0	0	0
T42	0	283	0	0
T43	0	198	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	908	0	0
T4	15939	116	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	125	0	0
T9	0	276	0	0
T12	4001	0	0	0
T13	93130	0	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T30	25323	0	0	0
T42	0	223	0	0
T43	0	168	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557041145	556972099	0	0
T1	4730	4634	0	0
T2	8902	8820	0	0
T3	20245	20147	0	0
T4	86	0	0	0
T5	0	15052	0	0
T10	16597	16545	0	0
T11	10417	10360	0	0
T12	4001	3909	0	0
T15	3996	3926	0	0
T17	7938	7858	0	0
T30	25323	25240	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	557025290	0	0
T1	4730	4634	0	0
T2	8902	8820	0	0
T3	20245	20147	0	0
T4	15939	2890	0	0
T10	16597	16545	0	0
T11	10417	10360	0	0
T12	4001	3909	0	0
T15	3996	3926	0	0
T17	7938	7858	0	0
T30	25323	25240	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T12 T5 T13 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T12 T5 T13 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T12 T5 T13 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T29 T31 T32 
159        1/1                    state_d = TimeoutSt;
           Tests:       T29 T31 T32 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T29 T31 T32 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T29 T31 T32 
172        1/1                    state_d    = Phase0St;
           Tests:       T29 T46 T79 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T29 T46 T79 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T29 T46 T79 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T29 T46 T79 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T29 T31 T32 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T29 T31 T32 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T29 T31 T32 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T31 T32 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T12 T13 T14 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T12 T13 T14 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T12 T13 T14 
190        1/1                  esc_state_o = Phase0;
           Tests:       T12 T13 T14 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T12 T13 T14 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T12 T13 T14 
194        1/1                    state_d = IdleSt;
           Tests:       T33 T36 T53 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T36 T53 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T33 T36 T53 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T12 T13 T14 
198        1/1                    state_d = Phase1St;
           Tests:       T12 T13 T14 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T13 T14 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T13 T14 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T12 T13 T14 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T12 T13 T14 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T12 T13 T14 
207        1/1                  esc_state_o = Phase1;
           Tests:       T12 T13 T14 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T12 T13 T14 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T12 T13 T14 
211        1/1                    state_d = IdleSt;
           Tests:       T36 T37 T101 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T36 T37 T101 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T36 T37 T101 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T12 T13 T14 
215        1/1                    state_d = Phase2St;
           Tests:       T12 T13 T14 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T13 T14 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T13 T14 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T12 T13 T14 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T12 T13 T14 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T12 T13 T14 
224        1/1                  esc_state_o = Phase2;
           Tests:       T12 T13 T14 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T12 T13 T14 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T12 T13 T14 
229        1/1                    state_d = IdleSt;
           Tests:       T29 T39 T58 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T39 T58 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T29 T39 T58 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T12 T13 T14 
233        1/1                    state_d = Phase3St;
           Tests:       T12 T13 T14 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T13 T14 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T12 T13 T14 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T12 T13 T14 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T12 T13 T14 
241        1/1                  esc_state_o = Phase3;
           Tests:       T12 T13 T14 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T12 T13 T14 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T12 T13 T14 
245        1/1                    state_d = IdleSt;
           Tests:       T102 T103 T104 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T102 T103 T104 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T102 T103 T104 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T12 T13 T14 
249        1/1                    state_d = TerminalSt;
           Tests:       T12 T13 T14 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T13 T14 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T12 T13 T14 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T12 T13 T14 
259        1/1                  esc_state_o = Terminal;
           Tests:       T12 T13 T14 
260        1/1                  if (clr_i) begin
           Tests:       T12 T13 T14 
261        1/1                    state_d = IdleSt;
           Tests:       T29 T31 T45 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T12,T5,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T5,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T15,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T12,T5,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T13,T29
1	0	1	Covered	T12,T44,T33
1	1	0	Covered	T10,T17,T29
1	1	1	Covered	T29,T31,T32

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T31,T32
0	1	Covered	T29,T46,T79
1	0	Covered	T50,T51,T53

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T29,T31,T32
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T50,T51,T53

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T31,T32
1	0	Not Covered
1	1	Covered	T29,T46,T79

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T13,T14,T29
1	Covered	T12,T45,T81

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T12,T13,T29
1	Covered	T14,T34,T80

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T41,T18,T105

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12,T14,T41
1	Covered	T13,T29,T31

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T4,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T12,T13,T29

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T12,T14,T41

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T12,T14,T29

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T12,T13,T14

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T12,T13,T14
Phase1St	198	Covered	T12,T13,T14
Phase2St	215	Covered	T12,T13,T14
Phase3St	233	Covered	T12,T13,T14
TerminalSt	249	Covered	T12,T13,T14
TimeoutSt	159	Covered	T29,T31,T32

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T8,T9
IdleSt->Phase0St	152	Covered	T12,T13,T14
IdleSt->TimeoutSt	159	Covered	T29,T31,T32
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T33,T36,T53
Phase0St->Phase1St	198	Covered	T12,T13,T14
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T36,T37,T49
Phase1St->Phase2St	215	Covered	T12,T13,T14
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T29,T39,T58
Phase2St->Phase3St	233	Covered	T12,T13,T14
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T102,T103,T104
Phase3St->TerminalSt	249	Covered	T12,T13,T14
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T29,T31,T45
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T29,T31,T32
TimeoutSt->Phase0St	172	Covered	T29,T46,T79

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T5,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T31,T32
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T29,T46,T79
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T29,T31,T32
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T29,T31,T32
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T36,T53
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T12,T13,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T13,T14,T29
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T36,T37,T101
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T12,T13,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T13,T14,T29
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T39,T58
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T12,T13,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T13,T14,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T102,T103,T104
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T12,T13,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T13,T14,T29
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T29,T31,T45
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T12,T13,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	557183493	227	0	0
CheckAccumTrig0_A	557183493	454	0	0
CheckAccumTrig1_A	557183493	21	0	0
CheckClr_A	557183493	215	0	0
CheckEn_A	557042185	263655584	0	0
CheckPhase0_A	557183493	513	0	0
CheckPhase1_A	557183493	500	0	0
CheckPhase2_A	557183493	491	0	0
CheckPhase3_A	557183493	487	0	0
CheckTimeout0_A	557183493	930	0	0
CheckTimeoutSt1_A	557183493	95714	0	0
CheckTimeoutSt2_A	557183493	855	0	0
CheckTimeoutStTrig_A	557183493	52	0	0
ErrorStAllEscAsserted_A	557183493	1103	0	0
ErrorStIsTerminal_A	557183493	893	0	0
EscStateOut_A	557041145	556972099	0	0
u_state_regs_A	557183493	557025290	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	227	0	0
T4	15939	40	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	35	0	0
T9	0	67	0	0
T12	4001	0	0	0
T13	93130	0	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T30	25323	0	0	0
T42	0	56	0	0
T43	0	29	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	454	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	0	0	0
T12	4001	1	0	0
T13	93130	1	0	0
T14	28693	1	0	0
T16	22747	0	0	0
T18	0	1	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T28	4979	0	0	0
T29	0	1	0	0
T31	0	3	0	0
T33	0	2	0	0
T39	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	21	0	0
T50	864761	1	0	0
T51	158865	1	0	0
T53	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T70	758900	0	0	0
T71	1289	0	0	0
T72	921066	0	0	0
T73	9805	0	0	0
T74	20981	0	0	0
T75	28080	0	0	0
T76	21209	0	0	0
T77	17226	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	215	0	0
T7	46256	0	0	0
T9	44675	0	0	0
T29	95773	2	0	0
T31	69603	2	0	0
T33	0	1	0	0
T36	0	5	0	0
T37	0	3	0	0
T38	106873	0	0	0
T39	0	2	0	0
T41	24135	0	0	0
T44	75098	0	0	0
T45	182537	1	0	0
T78	53350	0	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	3	0	0
T82	3193	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557042185	263655584	0	0
T1	4730	1773	0	0
T2	8902	8819	0	0
T3	20245	20146	0	0
T4	329	242	0	0
T10	16597	16544	0	0
T11	10417	10359	0	0
T12	4001	3187	0	0
T15	3996	3186	0	0
T17	7938	7857	0	0
T30	25323	25239	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	513	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	0	0	0
T12	4001	1	0	0
T13	93130	1	0	0
T14	28693	1	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T28	4979	0	0	0
T29	0	3	0	0
T31	0	3	0	0
T33	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	500	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	0	0	0
T12	4001	1	0	0
T13	93130	1	0	0
T14	28693	1	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T28	4979	0	0	0
T29	0	3	0	0
T31	0	3	0	0
T33	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	491	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	0	0	0
T12	4001	1	0	0
T13	93130	1	0	0
T14	28693	1	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T28	4979	0	0	0
T29	0	2	0	0
T31	0	3	0	0
T33	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	487	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	0	0	0
T12	4001	1	0	0
T13	93130	1	0	0
T14	28693	1	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T28	4979	0	0	0
T29	0	2	0	0
T31	0	3	0	0
T33	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	930	0	0
T7	46256	0	0	0
T9	44675	0	0	0
T29	95773	3	0	0
T31	69603	1	0	0
T32	0	10	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	106873	0	0	0
T39	0	1	0	0
T41	24135	0	0	0
T44	75098	0	0	0
T45	182537	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T78	53350	0	0	0
T79	0	4	0	0
T81	0	9	0	0
T82	3193	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	95714	0	0
T7	46256	0	0	0
T9	44675	0	0	0
T29	95773	500	0	0
T31	69603	33	0	0
T32	0	2194	0	0
T35	0	97	0	0
T36	0	52	0	0
T38	106873	0	0	0
T39	0	139	0	0
T41	24135	0	0	0
T44	75098	0	0	0
T45	182537	0	0	0
T46	0	291	0	0
T48	0	61	0	0
T78	53350	0	0	0
T79	0	660	0	0
T81	0	1959	0	0
T82	3193	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	855	0	0
T7	46256	0	0	0
T9	44675	0	0	0
T29	95773	1	0	0
T31	69603	1	0	0
T32	0	10	0	0
T35	0	1	0	0
T38	106873	0	0	0
T39	0	1	0	0
T41	24135	0	0	0
T44	75098	0	0	0
T45	182537	0	0	0
T49	0	2	0	0
T78	53350	0	0	0
T79	0	2	0	0
T81	0	8	0	0
T82	3193	0	0	0
T85	0	1	0	0
T86	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	52	0	0
T7	46256	0	0	0
T9	44675	0	0	0
T29	95773	2	0	0
T31	69603	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	106873	0	0	0
T41	24135	0	0	0
T44	75098	0	0	0
T45	182537	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T76	0	1	0	0
T78	53350	0	0	0
T79	0	2	0	0
T81	0	1	0	0
T82	3193	0	0	0
T86	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	1103	0	0
T4	15939	156	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	167	0	0
T9	0	312	0	0
T12	4001	0	0	0
T13	93130	0	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T30	25323	0	0	0
T42	0	316	0	0
T43	0	152	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	893	0	0
T4	15939	126	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	137	0	0
T9	0	252	0	0
T12	4001	0	0	0
T13	93130	0	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T30	25323	0	0	0
T42	0	256	0	0
T43	0	122	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557041145	556972099	0	0
T1	4730	4634	0	0
T2	8902	8820	0	0
T3	20245	20147	0	0
T4	86	0	0	0
T5	0	15052	0	0
T10	16597	16545	0	0
T11	10417	10360	0	0
T12	4001	3909	0	0
T15	3996	3926	0	0
T17	7938	7858	0	0
T30	25323	25240	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	557025290	0	0
T1	4730	4634	0	0
T2	8902	8820	0	0
T3	20245	20147	0	0
T4	15939	2890	0	0
T10	16597	16545	0	0
T11	10417	10360	0	0
T12	4001	3909	0	0
T15	3996	3926	0	0
T17	7938	7858	0	0
T30	25323	25240	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T15 T16 T13 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T15 T16 T13 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T15 T16 T13 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T27 T29 
159        1/1                    state_d = TimeoutSt;
           Tests:       T13 T27 T29 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T13 T27 T29 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T13 T27 T29 
172        1/1                    state_d    = Phase0St;
           Tests:       T29 T31 T65 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T29 T31 T65 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T29 T31 T65 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T29 T31 T65 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T13 T27 T29 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T27 T29 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T13 T27 T29 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T27 T29 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T15 T16 T13 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T15 T16 T13 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T15 T16 T13 
190        1/1                  esc_state_o = Phase0;
           Tests:       T15 T16 T13 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T15 T16 T13 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T15 T16 T13 
194        1/1                    state_d = IdleSt;
           Tests:       T13 T106 T50 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T106 T50 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T13 T106 T50 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T15 T16 T13 
198        1/1                    state_d = Phase1St;
           Tests:       T15 T16 T13 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T15 T16 T13 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T15 T16 T13 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T15 T16 T13 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T15 T16 T13 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T15 T16 T13 
207        1/1                  esc_state_o = Phase1;
           Tests:       T15 T16 T13 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T15 T16 T13 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T15 T16 T13 
211        1/1                    state_d = IdleSt;
           Tests:       T35 T96 T107 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T96 T107 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T96 T107 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T15 T16 T13 
215        1/1                    state_d = Phase2St;
           Tests:       T15 T16 T13 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T15 T16 T13 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T15 T16 T13 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T15 T16 T13 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T15 T16 T13 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T15 T16 T13 
224        1/1                  esc_state_o = Phase2;
           Tests:       T15 T16 T13 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T15 T16 T13 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T15 T16 T13 
229        1/1                    state_d = IdleSt;
           Tests:       T13 T35 T108 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T35 T108 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T13 T35 T108 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T15 T16 T13 
233        1/1                    state_d = Phase3St;
           Tests:       T15 T16 T13 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T15 T16 T13 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T15 T16 T13 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T15 T16 T13 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T15 T16 T13 
241        1/1                  esc_state_o = Phase3;
           Tests:       T15 T16 T13 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T15 T16 T13 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T15 T16 T13 
245        1/1                    state_d = IdleSt;
           Tests:       T13 T39 T35 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T39 T35 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T13 T39 T35 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T15 T16 T13 
249        1/1                    state_d = TerminalSt;
           Tests:       T15 T16 T13 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T15 T16 T13 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T15 T16 T13 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T15 T16 T13 
259        1/1                  esc_state_o = Terminal;
           Tests:       T15 T16 T13 
260        1/1                  if (clr_i) begin
           Tests:       T15 T16 T13 
261        1/1                    state_d = IdleSt;
           Tests:       T13 T27 T29 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T15,T16,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T16,T13,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T16,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T15,T10,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T16,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T13,T27
1	0	1	Covered	T15,T10,T27
1	1	0	Covered	T17,T27,T45
1	1	1	Covered	T13,T27,T29

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T27,T29
0	1	Covered	T31,T65,T51
1	0	Covered	T29,T34,T35

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T13,T27,T29
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T29,T34,T35

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T27,T29
1	0	Not Covered
1	1	Covered	T31,T65,T51

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T16,T13,T27
1	Covered	T15,T14,T29

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T13,T27
1	Covered	T16,T31,T44

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15,T16,T13
1	Covered	T31,T23,T109

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15,T16,T14
1	Covered	T13,T27,T65

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T4,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T15,T16,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T15,T16,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T15,T13,T27

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T15,T27,T14

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T15,T16,T13
Phase1St	198	Covered	T15,T16,T13
Phase2St	215	Covered	T15,T16,T13
Phase3St	233	Covered	T15,T16,T13
TerminalSt	249	Covered	T15,T16,T13
TimeoutSt	159	Covered	T13,T27,T29

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T8,T9
IdleSt->Phase0St	152	Covered	T15,T16,T13
IdleSt->TimeoutSt	159	Covered	T13,T27,T29
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T13,T81,T48
Phase0St->Phase1St	198	Covered	T15,T16,T13
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T35,T96,T107
Phase1St->Phase2St	215	Covered	T15,T16,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T13,T35,T108
Phase2St->Phase3St	233	Covered	T15,T16,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T13,T39,T35
Phase3St->TerminalSt	249	Covered	T15,T16,T13
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T13,T27,T29
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T13,T27,T29
TimeoutSt->Phase0St	172	Covered	T29,T31,T65

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T27,T29
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T29,T31,T65
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T13,T27,T29
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T27,T29
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T13,T106,T50
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T15,T16,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T16,T13,T27
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T35,T96,T107
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T15,T16,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T16,T27,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T13,T35,T108
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T15,T16,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T16,T13,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T13,T39,T35
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T15,T16,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T16,T13,T27
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T27,T29
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T15,T16,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	557183493	190	0	0
CheckAccumTrig0_A	557183493	494	0	0
CheckAccumTrig1_A	557183493	26	0	0
CheckClr_A	557183493	238	0	0
CheckEn_A	557042185	249527955	0	0
CheckPhase0_A	557183493	538	0	0
CheckPhase1_A	557183493	527	0	0
CheckPhase2_A	557183493	516	0	0
CheckPhase3_A	557183493	507	0	0
CheckTimeout0_A	557183493	786	0	0
CheckTimeoutSt1_A	557183493	74908	0	0
CheckTimeoutSt2_A	557183493	717	0	0
CheckTimeoutStTrig_A	557183493	40	0	0
ErrorStAllEscAsserted_A	557183493	1110	0	0
ErrorStIsTerminal_A	557183493	900	0	0
EscStateOut_A	557041145	556972099	0	0
u_state_regs_A	557183493	557025290	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	190	0	0
T4	15939	18	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	16	0	0
T9	0	59	0	0
T12	4001	0	0	0
T13	93130	0	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T30	25323	0	0	0
T42	0	66	0	0
T43	0	31	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	494	0	0
T4	15939	0	0	0
T5	15178	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T13	93130	8	0	0
T14	0	1	0	0
T15	3996	1	0	0
T16	22747	1	0	0
T17	7938	0	0	0
T27	0	1	0	0
T29	0	3	0	0
T30	25323	0	0	0
T31	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	26	0	0
T7	46256	0	0	0
T9	44675	0	0	0
T29	95773	1	0	0
T31	69603	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T38	106873	0	0	0
T41	24135	0	0	0
T44	75098	0	0	0
T45	182537	0	0	0
T52	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T78	53350	0	0	0
T82	3193	0	0	0
T90	0	1	0	0
T98	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	238	0	0
T6	113821	0	0	0
T7	46256	0	0	0
T8	15511	0	0	0
T13	93130	7	0	0
T14	28693	0	0	0
T26	8613	0	0	0
T27	18276	1	0	0
T28	4979	0	0	0
T29	95773	4	0	0
T31	69603	1	0	0
T33	0	1	0	0
T34	0	3	0	0
T35	0	11	0	0
T39	0	1	0	0
T65	0	2	0	0
T112	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557042185	249527955	0	0
T1	4730	4633	0	0
T2	8902	8819	0	0
T3	20245	20146	0	0
T4	329	242	0	0
T10	16597	640	0	0
T11	10417	10359	0	0
T12	4001	3202	0	0
T15	3996	3206	0	0
T17	7938	7857	0	0
T30	25323	25239	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	538	0	0
T4	15939	0	0	0
T5	15178	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T13	93130	6	0	0
T14	0	1	0	0
T15	3996	1	0	0
T16	22747	1	0	0
T17	7938	0	0	0
T27	0	1	0	0
T29	0	4	0	0
T30	25323	0	0	0
T31	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	527	0	0
T4	15939	0	0	0
T5	15178	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T13	93130	6	0	0
T14	0	1	0	0
T15	3996	1	0	0
T16	22747	1	0	0
T17	7938	0	0	0
T27	0	1	0	0
T29	0	4	0	0
T30	25323	0	0	0
T31	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	516	0	0
T4	15939	0	0	0
T5	15178	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T13	93130	5	0	0
T14	0	1	0	0
T15	3996	1	0	0
T16	22747	1	0	0
T17	7938	0	0	0
T27	0	1	0	0
T29	0	4	0	0
T30	25323	0	0	0
T31	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	507	0	0
T4	15939	0	0	0
T5	15178	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T13	93130	4	0	0
T14	0	1	0	0
T15	3996	1	0	0
T16	22747	1	0	0
T17	7938	0	0	0
T27	0	1	0	0
T29	0	4	0	0
T30	25323	0	0	0
T31	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	786	0	0
T6	113821	0	0	0
T7	46256	0	0	0
T8	15511	0	0	0
T13	93130	2	0	0
T14	28693	0	0	0
T26	8613	0	0	0
T27	18276	1	0	0
T28	4979	0	0	0
T29	95773	5	0	0
T31	69603	2	0	0
T32	0	2	0	0
T34	0	4	0	0
T45	0	2	0	0
T65	0	2	0	0
T83	0	9	0	0
T84	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	74908	0	0
T6	113821	0	0	0
T7	46256	0	0	0
T8	15511	0	0	0
T13	93130	165	0	0
T14	28693	0	0	0
T26	8613	0	0	0
T27	18276	7	0	0
T28	4979	0	0	0
T29	95773	893	0	0
T31	69603	709	0	0
T32	0	409	0	0
T34	0	53	0	0
T45	0	312	0	0
T65	0	182	0	0
T83	0	1580	0	0
T84	0	153	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	717	0	0
T6	113821	0	0	0
T7	46256	0	0	0
T8	15511	0	0	0
T13	93130	2	0	0
T14	28693	0	0	0
T26	8613	0	0	0
T27	18276	1	0	0
T28	4979	0	0	0
T29	95773	4	0	0
T31	69603	1	0	0
T32	0	2	0	0
T34	0	2	0	0
T45	0	2	0	0
T79	0	1	0	0
T83	0	9	0	0
T84	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	40	0	0
T9	44675	0	0	0
T31	69603	1	0	0
T32	134757	0	0	0
T38	106873	0	0	0
T41	24135	0	0	0
T44	75098	0	0	0
T45	182537	0	0	0
T51	0	1	0	0
T53	0	3	0	0
T59	0	2	0	0
T65	0	2	0	0
T78	53350	0	0	0
T82	3193	0	0	0
T91	0	1	0	0
T92	73721	0	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	2	0	0
T116	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	1110	0	0
T4	15939	149	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	134	0	0
T9	0	327	0	0
T12	4001	0	0	0
T13	93130	0	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T30	25323	0	0	0
T42	0	331	0	0
T43	0	169	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	900	0	0
T4	15939	119	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	104	0	0
T9	0	267	0	0
T12	4001	0	0	0
T13	93130	0	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T30	25323	0	0	0
T42	0	271	0	0
T43	0	139	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557041145	556972099	0	0
T1	4730	4634	0	0
T2	8902	8820	0	0
T3	20245	20147	0	0
T4	86	0	0	0
T5	0	15052	0	0
T10	16597	16545	0	0
T11	10417	10360	0	0
T12	4001	3909	0	0
T15	3996	3926	0	0
T17	7938	7858	0	0
T30	25323	25240	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	557025290	0	0
T1	4730	4634	0	0
T2	8902	8820	0	0
T3	20245	20147	0	0
T4	15939	2890	0	0
T10	16597	16545	0	0
T11	10417	10360	0	0
T12	4001	3909	0	0
T15	3996	3926	0	0
T17	7938	7858	0	0
T30	25323	25240	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T16 T13 T27 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T16 T13 T27 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T16 T13 T27 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T14 T31 
159        1/1                    state_d = TimeoutSt;
           Tests:       T1 T14 T31 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T1 T14 T31 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T1 T14 T31 
172        1/1                    state_d    = Phase0St;
           Tests:       T45 T65 T79 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T45 T65 T79 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T45 T65 T79 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T45 T65 T79 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T1 T14 T31 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T14 T31 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T1 T14 T31 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T14 T31 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T16 T13 T27 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T16 T13 T27 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T16 T13 T27 
190        1/1                  esc_state_o = Phase0;
           Tests:       T16 T13 T27 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T16 T13 T27 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T16 T13 T27 
194        1/1                    state_d = IdleSt;
           Tests:       T117 T118 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T117 T118 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T117 T118 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T16 T13 T27 
198        1/1                    state_d = Phase1St;
           Tests:       T16 T13 T27 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T16 T13 T27 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T16 T13 T27 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T16 T13 T27 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T16 T13 T27 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T16 T13 T27 
207        1/1                  esc_state_o = Phase1;
           Tests:       T16 T13 T27 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T16 T13 T27 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T16 T13 T27 
211        1/1                    state_d = IdleSt;
           Tests:       T33 T37 T119 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T37 T119 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T33 T37 T119 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T16 T13 T27 
215        1/1                    state_d = Phase2St;
           Tests:       T16 T13 T27 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T16 T13 T27 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T16 T13 T27 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T16 T13 T27 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T16 T13 T27 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T16 T13 T27 
224        1/1                  esc_state_o = Phase2;
           Tests:       T16 T13 T27 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T16 T13 T27 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T16 T13 T27 
229        1/1                    state_d = IdleSt;
           Tests:       T101 T120 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T101 T120 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T101 T120 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T16 T13 T27 
233        1/1                    state_d = Phase3St;
           Tests:       T16 T13 T27 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T16 T13 T27 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T16 T13 T27 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T16 T13 T27 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T16 T13 T27 
241        1/1                  esc_state_o = Phase3;
           Tests:       T16 T13 T27 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T16 T13 T27 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T16 T13 T27 
245        1/1                    state_d = IdleSt;
           Tests:       T35 T121 T120 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T121 T120 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T121 T120 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T16 T13 T27 
249        1/1                    state_d = TerminalSt;
           Tests:       T16 T13 T27 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T16 T13 T27 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T16 T13 T27 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T16 T13 T27 
259        1/1                  esc_state_o = Terminal;
           Tests:       T16 T13 T27 
260        1/1                  if (clr_i) begin
           Tests:       T16 T13 T27 
261        1/1                    state_d = IdleSt;
           Tests:       T31 T45 T93 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T1,T16,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T16,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T15,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T16,T13,T27

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T10,T17
1	0	1	Covered	T28,T44,T82
1	1	0	Covered	T10,T29,T31
1	1	1	Covered	T1,T14,T31

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T31
0	1	Covered	T65,T79,T76
1	0	Covered	T45,T35,T36

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T14,T31
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T45,T35,T36

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T31
1	0	Not Covered
1	1	Covered	T65,T79,T76

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T16,T13,T31
1	Covered	T27,T14,T28

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T16,T13,T27
1	Covered	T33,T35,T99

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T27,T14,T28
1	Covered	T16,T13,T41

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T16,T13,T27
1	Covered	T31,T93,T39

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T4,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T16,T13,T27

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T14,T28,T31

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T16,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T16,T14,T28

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T16,T13,T27
Phase1St	198	Covered	T16,T13,T27
Phase2St	215	Covered	T16,T13,T27
Phase3St	233	Covered	T16,T13,T27
TerminalSt	249	Covered	T16,T13,T27
TimeoutSt	159	Covered	T1,T14,T31

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T8,T9
IdleSt->Phase0St	152	Covered	T16,T13,T27
IdleSt->TimeoutSt	159	Covered	T1,T14,T31
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T91,T122,T59
Phase0St->Phase1St	198	Covered	T16,T13,T27
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T33,T36,T37
Phase1St->Phase2St	215	Covered	T16,T13,T27
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T101,T120
Phase2St->Phase3St	233	Covered	T16,T13,T27
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T35,T121,T123
Phase3St->TerminalSt	249	Covered	T16,T13,T27
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T31,T45,T93
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T14,T31
TimeoutSt->Phase0St	172	Covered	T45,T65,T79

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T13,T27
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T14,T31
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T45,T65,T79
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T14,T31
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T14,T31
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T117,T118
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T16,T13,T27
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T16,T13,T27
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T33,T37,T119
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T16,T13,T27
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T16,T13,T27
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T101,T120
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T16,T13,T27
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T16,T13,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T35,T121,T120
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T16,T13,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T16,T13,T27
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T31,T45,T93
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T16,T13,T27
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	557183493	211	0	0
CheckAccumTrig0_A	557183493	436	0	0
CheckAccumTrig1_A	557183493	18	0	0
CheckClr_A	557183493	187	0	0
CheckEn_A	557042185	244160728	0	0
CheckPhase0_A	557183493	491	0	0
CheckPhase1_A	557183493	479	0	0
CheckPhase2_A	557183493	477	0	0
CheckPhase3_A	557183493	464	0	0
CheckTimeout0_A	557183493	489	0	0
CheckTimeoutSt1_A	557183493	54329	0	0
CheckTimeoutSt2_A	557183493	418	0	0
CheckTimeoutStTrig_A	557183493	48	0	0
ErrorStAllEscAsserted_A	557183493	1087	0	0
ErrorStIsTerminal_A	557183493	877	0	0
EscStateOut_A	557041145	556972099	0	0
u_state_regs_A	557183493	557025290	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	211	0	0
T4	15939	41	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	25	0	0
T9	0	60	0	0
T12	4001	0	0	0
T13	93130	0	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T30	25323	0	0	0
T42	0	72	0	0
T43	0	13	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	436	0	0
T6	113821	0	0	0
T7	46256	0	0	0
T8	15511	0	0	0
T13	93130	1	0	0
T14	28693	1	0	0
T16	22747	1	0	0
T26	8613	0	0	0
T27	18276	1	0	0
T28	4979	1	0	0
T29	95773	0	0	0
T31	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T82	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	18	0	0
T21	36711	0	0	0
T32	134757	0	0	0
T33	111353	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	22733	0	0	0
T42	44852	0	0	0
T45	182537	1	0	0
T46	20406	0	0	0
T50	0	1	0	0
T83	89583	0	0	0
T89	0	1	0	0
T92	73721	0	0	0
T93	6031	0	0	0
T94	0	1	0	0
T102	0	1	0	0
T115	0	1	0	0
T124	0	1	0	0
T125	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	187	0	0
T9	44675	0	0	0
T31	69603	1	0	0
T32	134757	0	0	0
T33	0	3	0	0
T34	0	1	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	106873	0	0	0
T41	24135	0	0	0
T44	75098	0	0	0
T45	182537	1	0	0
T48	0	1	0	0
T65	0	1	0	0
T78	53350	0	0	0
T82	3193	0	0	0
T92	73721	0	0	0
T93	0	1	0	0
T99	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557042185	244160728	0	0
T1	4730	3446	0	0
T2	8902	8819	0	0
T3	20245	20146	0	0
T4	329	242	0	0
T10	16597	10940	0	0
T11	10417	10359	0	0
T12	4001	3226	0	0
T15	3996	3223	0	0
T17	7938	2015	0	0
T30	25323	25239	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	491	0	0
T6	113821	0	0	0
T7	46256	0	0	0
T8	15511	0	0	0
T13	93130	1	0	0
T14	28693	1	0	0
T16	22747	1	0	0
T26	8613	0	0	0
T27	18276	1	0	0
T28	4979	1	0	0
T29	95773	0	0	0
T31	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T82	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	479	0	0
T6	113821	0	0	0
T7	46256	0	0	0
T8	15511	0	0	0
T13	93130	1	0	0
T14	28693	1	0	0
T16	22747	1	0	0
T26	8613	0	0	0
T27	18276	1	0	0
T28	4979	1	0	0
T29	95773	0	0	0
T31	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T82	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	477	0	0
T6	113821	0	0	0
T7	46256	0	0	0
T8	15511	0	0	0
T13	93130	1	0	0
T14	28693	1	0	0
T16	22747	1	0	0
T26	8613	0	0	0
T27	18276	1	0	0
T28	4979	1	0	0
T29	95773	0	0	0
T31	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T82	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	464	0	0
T6	113821	0	0	0
T7	46256	0	0	0
T8	15511	0	0	0
T13	93130	1	0	0
T14	28693	1	0	0
T16	22747	1	0	0
T26	8613	0	0	0
T27	18276	1	0	0
T28	4979	1	0	0
T29	95773	0	0	0
T31	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T82	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	489	0	0
T1	4730	1	0	0
T2	8902	0	0	0
T3	20245	0	0	0
T4	15939	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T14	0	2	0	0
T15	3996	0	0	0
T17	7938	0	0	0
T30	25323	0	0	0
T31	0	1	0	0
T32	0	11	0	0
T35	0	1	0	0
T45	0	1	0	0
T65	0	3	0	0
T79	0	1	0	0
T84	0	3	0	0
T126	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	54329	0	0
T1	4730	204	0	0
T2	8902	0	0	0
T3	20245	0	0	0
T4	15939	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T14	0	398	0	0
T15	3996	0	0	0
T17	7938	0	0	0
T30	25323	0	0	0
T31	0	20	0	0
T32	0	2342	0	0
T48	0	1003	0	0
T65	0	718	0	0
T79	0	26	0	0
T81	0	130	0	0
T84	0	458	0	0
T126	0	328	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	418	0	0
T1	4730	1	0	0
T2	8902	0	0	0
T3	20245	0	0	0
T4	15939	0	0	0
T10	16597	0	0	0
T11	10417	0	0	0
T12	4001	0	0	0
T14	0	2	0	0
T15	3996	0	0	0
T17	7938	0	0	0
T30	25323	0	0	0
T31	0	1	0	0
T32	0	11	0	0
T36	0	1	0	0
T48	0	11	0	0
T65	0	2	0	0
T81	0	1	0	0
T84	0	3	0	0
T126	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	48	0	0
T18	345209	0	0	0
T22	14846	0	0	0
T23	60289	0	0	0
T39	55982	0	0	0
T43	21802	0	0	0
T65	24163	1	0	0
T66	180688	0	0	0
T67	56553	0	0	0
T68	3081	0	0	0
T69	4826	0	0	0
T76	0	1	0	0
T79	0	1	0	0
T89	0	2	0	0
T90	0	2	0	0
T102	0	1	0	0
T119	0	3	0	0
T127	0	1	0	0
T128	0	3	0	0
T129	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	1087	0	0
T4	15939	170	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	143	0	0
T9	0	309	0	0
T12	4001	0	0	0
T13	93130	0	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T30	25323	0	0	0
T42	0	298	0	0
T43	0	167	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	877	0	0
T4	15939	140	0	0
T5	15178	0	0	0
T6	113821	0	0	0
T8	15511	113	0	0
T9	0	249	0	0
T12	4001	0	0	0
T13	93130	0	0	0
T16	22747	0	0	0
T26	8613	0	0	0
T27	18276	0	0	0
T30	25323	0	0	0
T42	0	238	0	0
T43	0	137	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557041145	556972099	0	0
T1	4730	4634	0	0
T2	8902	8820	0	0
T3	20245	20147	0	0
T4	86	0	0	0
T5	0	15052	0	0
T10	16597	16545	0	0
T11	10417	10360	0	0
T12	4001	3909	0	0
T15	3996	3926	0	0
T17	7938	7858	0	0
T30	25323	25240	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	557183493	557025290	0	0
T1	4730	4634	0	0
T2	8902	8820	0	0
T3	20245	20147	0	0
T4	15939	2890	0	0
T10	16597	16545	0	0
T11	10417	10360	0	0
T12	4001	3909	0	0
T15	3996	3926	0	0
T17	7938	7858	0	0
T30	25323	25240	0	0