SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
cip_base_pkg.dut_and_edn_rsts | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
resets_trans | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
rst1_start_last_end_first | 1394 | 1 | T6 | 94 | T7 | 52 | T8 | 73 | ||||
rst1_start_first_end_last | 1168 | 1 | T6 | 70 | T8 | 92 | T24 | 1 | ||||
rst1_start_last_end_last | 2426 | 1 | T3 | 1 | T4 | 1 | T5 | 1 | ||||
rst1_start_first_end_first | 3547 | 1 | T20 | 1 | T6 | 115 | T7 | 288 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |