Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52031358	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24665612

1

T1

172

T2

117

T3

121

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12245048	1			T1	61		T2	61		T3	73
values[0x0]	32153965	1			T1	225		T2	174		T3	203
values[0x1]	32297957	1			T1	221		T2	171		T3	177

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45273407	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

31423563

1

T1

220

T2

147

T3

161

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	219515	1			T1	1		T2	3		T9	11
valid_sources[0x01]	657955	1			T2	2		T9	16		T10	41
valid_sources[0x02]	216351	1			T1	11		T2	1		T9	29
valid_sources[0x03]	490616	1			T2	3		T9	8		T10	2
valid_sources[0x04]	220049	1			T1	3		T9	15		T25	21
valid_sources[0x05]	214229	1			T2	1		T9	20		T25	44
valid_sources[0x06]	217238	1			T1	1		T9	6		T25	51
valid_sources[0x07]	891313	1			T9	11		T10	317		T25	30
valid_sources[0x08]	787728	1			T9	15		T25	38		T12	2
valid_sources[0x09]	232444	1			T1	3		T9	14		T15	3969
valid_sources[0x0a]	216665	1			T1	2		T9	15		T25	39
valid_sources[0x0b]	212697	1			T1	1		T2	3		T9	6
valid_sources[0x0c]	705955	1			T1	1		T2	2		T9	10
valid_sources[0x0d]	213232	1			T1	6		T9	19		T25	46
valid_sources[0x0e]	647989	1			T1	1		T9	24		T25	22
valid_sources[0x0f]	216116	1			T2	1		T9	24		T10	30
valid_sources[0x10]	220349	1			T1	1		T2	6		T9	10
valid_sources[0x11]	216563	1			T2	2		T9	21		T25	52
valid_sources[0x12]	583479	1			T2	1		T9	13		T10	42
valid_sources[0x13]	214098	1			T2	1		T9	19		T10	2
valid_sources[0x14]	222802	1			T9	20		T25	37		T12	3
valid_sources[0x15]	215402	1			T1	2		T9	13		T25	28
valid_sources[0x16]	217531	1			T2	2		T9	13		T25	38
valid_sources[0x17]	557313	1			T1	13		T2	5		T9	5
valid_sources[0x18]	210725	1			T1	1		T2	2		T9	9
valid_sources[0x19]	214342	1			T1	3		T2	1		T9	17
valid_sources[0x1a]	592512	1			T2	1		T9	11		T10	28
valid_sources[0x1b]	220387	1			T1	5		T2	1		T9	11
valid_sources[0x1c]	577789	1			T2	2		T9	14		T25	40
valid_sources[0x1d]	217632	1			T1	3		T9	9		T10	140
valid_sources[0x1e]	217397	1			T1	1		T2	1		T9	13
valid_sources[0x1f]	869779	1			T1	3		T2	3		T9	18
valid_sources[0x20]	217081	1			T1	1		T2	3		T9	18
valid_sources[0x21]	443838	1			T9	16		T25	39		T12	4
valid_sources[0x22]	214669	1			T1	4		T2	1		T9	8
valid_sources[0x23]	216825	1			T9	13		T25	35		T12	2
valid_sources[0x24]	451277	1			T2	2		T9	20		T25	57
valid_sources[0x25]	219136	1			T2	2		T9	17		T10	20
valid_sources[0x26]	216497	1			T1	2		T2	2		T9	17
valid_sources[0x27]	215067	1			T1	1		T2	2		T9	22
valid_sources[0x28]	215273	1			T1	2		T2	2		T9	16
valid_sources[0x29]	217601	1			T1	1		T2	3		T9	28
valid_sources[0x2a]	216380	1			T1	1		T2	1		T9	21
valid_sources[0x2b]	214300	1			T1	1		T9	16		T25	53
valid_sources[0x2c]	221956	1			T1	1		T2	2		T9	22
valid_sources[0x2d]	215849	1			T2	3		T9	21		T10	4
valid_sources[0x2e]	221876	1			T1	2		T2	2		T9	15
valid_sources[0x2f]	444369	1			T9	13		T10	45		T25	56
valid_sources[0x30]	215446	1			T2	3		T9	18		T10	26
valid_sources[0x31]	224087	1			T1	4		T2	3		T9	25
valid_sources[0x32]	223190	1			T1	2		T2	1		T9	14
valid_sources[0x33]	218336	1			T1	3		T2	1		T9	15
valid_sources[0x34]	213562	1			T2	1		T9	17		T25	48
valid_sources[0x35]	747951	1			T1	7		T2	2		T9	13
valid_sources[0x36]	676216	1			T1	6		T2	1		T9	15
valid_sources[0x37]	214739	1			T1	1		T2	3		T9	18
valid_sources[0x38]	216135	1			T2	2		T9	9		T25	26
valid_sources[0x39]	216528	1			T2	2		T9	8		T10	23
valid_sources[0x3a]	533516	1			T2	4		T9	17		T10	5
valid_sources[0x3b]	229457	1			T1	3		T2	3		T9	15
valid_sources[0x3c]	219340	1			T2	1		T9	11		T10	56
valid_sources[0x3d]	215425	1			T1	7		T2	2		T9	14
valid_sources[0x3e]	685039	1			T2	1		T9	15		T10	1
valid_sources[0x3f]	573852	1			T1	2		T9	8		T25	55
valid_sources[0x40]	236870	1			T1	3		T9	22		T25	44
valid_sources[0x41]	221393	1			T2	1		T9	15		T25	39
valid_sources[0x42]	217116	1			T2	1		T9	13		T25	40
valid_sources[0x43]	222835	1			T2	3		T9	11		T25	23
valid_sources[0x44]	742454	1			T2	2		T9	20		T10	139
valid_sources[0x45]	225772	1			T1	4		T2	1		T9	8
valid_sources[0x46]	497036	1			T1	2		T2	1		T9	19
valid_sources[0x47]	215899	1			T9	20		T10	64		T25	44
valid_sources[0x48]	421691	1			T1	2		T2	2		T9	14
valid_sources[0x49]	214987	1			T2	3		T9	8		T25	41
valid_sources[0x4a]	214927	1			T1	6		T2	2		T9	19
valid_sources[0x4b]	224358	1			T2	2		T9	17		T25	55
valid_sources[0x4c]	225815	1			T2	2		T9	17		T10	104
valid_sources[0x4d]	217314	1			T1	2		T2	1		T9	12
valid_sources[0x4e]	219638	1			T1	2		T9	20		T25	44
valid_sources[0x4f]	221168	1			T1	6		T2	1		T9	14
valid_sources[0x50]	857163	1			T2	2		T9	14		T25	22
valid_sources[0x51]	215632	1			T2	3		T9	8		T25	32
valid_sources[0x52]	213192	1			T2	2		T9	12		T25	28
valid_sources[0x53]	212859	1			T1	7		T2	3		T9	12
valid_sources[0x54]	598376	1			T2	2		T9	22		T10	31
valid_sources[0x55]	215015	1			T1	6		T2	3		T9	20
valid_sources[0x56]	218441	1			T1	1		T2	1		T9	31
valid_sources[0x57]	223124	1			T2	1		T9	17		T25	34
valid_sources[0x58]	216552	1			T2	2		T9	16		T10	44
valid_sources[0x59]	443052	1			T2	2		T9	12		T10	39
valid_sources[0x5a]	215420	1			T1	2		T2	2		T9	9
valid_sources[0x5b]	215444	1			T1	1		T2	1		T9	19
valid_sources[0x5c]	214236	1			T1	1		T2	1		T9	14
valid_sources[0x5d]	214685	1			T1	4		T9	10		T25	29
valid_sources[0x5e]	215240	1			T1	1		T2	1		T9	19
valid_sources[0x5f]	218038	1			T2	2		T9	14		T10	6
valid_sources[0x60]	242819	1			T1	2		T2	2		T9	23
valid_sources[0x61]	875575	1			T2	3		T9	11		T25	30
valid_sources[0x62]	258137	1			T9	5		T10	74		T25	38
valid_sources[0x63]	221661	1			T2	2		T9	23		T25	27
valid_sources[0x64]	215341	1			T1	2		T2	3		T9	24
valid_sources[0x65]	213127	1			T1	3		T9	10		T25	22
valid_sources[0x66]	215545	1			T1	1		T9	9		T25	48
valid_sources[0x67]	663883	1			T1	6		T9	16		T10	19
valid_sources[0x68]	219120	1			T1	2		T2	1		T9	11
valid_sources[0x69]	221488	1			T1	11		T2	3		T9	11
valid_sources[0x6a]	237439	1			T2	1		T9	13		T25	36
valid_sources[0x6b]	214561	1			T1	1		T2	4		T9	16
valid_sources[0x6c]	414867	1			T1	2		T2	3		T9	23
valid_sources[0x6d]	215568	1			T1	10		T2	1		T9	13
valid_sources[0x6e]	214702	1			T1	1		T2	5		T9	14
valid_sources[0x6f]	227604	1			T1	4		T2	7		T9	12
valid_sources[0x70]	219931	1			T1	1		T2	3		T9	15
valid_sources[0x71]	216627	1			T2	2		T9	22		T10	197
valid_sources[0x72]	226498	1			T1	1		T2	1		T9	15
valid_sources[0x73]	219325	1			T1	2		T9	12		T25	28
valid_sources[0x74]	237581	1			T1	4		T2	3		T9	16
valid_sources[0x75]	216339	1			T2	2		T9	18		T10	166
valid_sources[0x76]	219700	1			T2	1		T9	16		T10	43
valid_sources[0x77]	214728	1			T1	5		T2	1		T9	17
valid_sources[0x78]	217128	1			T1	2		T2	1		T9	20
valid_sources[0x79]	230003	1			T2	5		T9	20		T10	30
valid_sources[0x7a]	228289	1			T2	1		T9	20		T10	149
valid_sources[0x7b]	215993	1			T1	7		T2	2		T9	9
valid_sources[0x7c]	215221	1			T2	2		T9	19		T10	101
valid_sources[0x7d]	215684	1			T1	3		T2	2		T9	15
valid_sources[0x7e]	219478	1			T1	2		T2	3		T9	13
valid_sources[0x7f]	213255	1			T9	17		T10	20		T25	18
valid_sources[0x80]	214237	1			T2	3		T9	25		T10	124

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5880575

1

T1

25

T2

31

T3

36

values[0x0]

all_enables

biggest_size

11991167

1

T1

97

T2

57

T3

66

values[0x1]

all_enables

biggest_size

6793870

1

T1

50

T2

29

T3

19