Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T15
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T50
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T15

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2090300600	14773	0	0
DisabledNoTrigBkwd_A	2090300600	615166	0	0
DisabledNoTrigFwd_A	2090300600	1165836336	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	14773	0	0
T2	6004	1750	0	0
T3	13615	0	0	0
T4	95721	0	0	0
T5	63586	0	0	0
T9	31608	0	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T13	14973	0	0	0
T14	138555	0	0	0
T15	10645	0	0	0
T25	119482	0	0	0
T27	1247	415	0	0
T38	85904	0	0	0
T47	0	174	0	0
T50	8468	945	0	0
T51	13734	1454	0	0
T52	19620	0	0	0
T53	49374	0	0	0
T54	105921	0	0	0
T55	5630	391	0	0
T56	12326	0	0	0
T74	0	365	0	0
T114	0	350	0	0
T198	0	396	0	0
T217	0	433	0	0
T218	0	719	0	0
T219	0	1366	0	0
T220	0	470	0	0
T221	0	669	0	0
T222	0	926	0	0
T223	0	771	0	0
T224	0	758	0	0
T225	0	333	0	0
T226	0	1312	0	0
T227	0	776	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	615166	0	0
T2	6004	0	0	0
T3	13615	0	0	0
T4	31907	0	0	0
T9	63216	2	0	0
T10	41610	0	0	0
T11	41103	3	0	0
T12	24372	0	0	0
T13	4991	0	0	0
T14	46185	6	0	0
T15	21290	1	0	0
T16	41088	199	0	0
T25	358446	10	0	0
T26	107232	53	0	0
T27	3741	10	0	0
T28	0	2	0	0
T33	0	42	0	0
T38	85904	27	0	0
T40	0	21	0	0
T47	0	2	0	0
T49	0	23	0	0
T50	12702	6	0	0
T51	9156	28	0	0
T52	13080	2	0	0
T53	0	12	0	0
T54	0	121	0	0
T55	0	10	0	0
T57	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	1165836336	0	0
T1	5232	3732	0	0
T2	24016	15869	0	0
T3	54460	12524	0	0
T9	126432	66539	0	0
T10	83220	63262	0	0
T11	54804	38372	0	0
T12	32496	14770	0	0
T15	42580	23502	0	0
T16	41088	3910	0	0
T25	477928	361345	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T3 T9 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T15,T10
1	1	Covered	T1,T9,T15

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T217,T74
1	1	Covered	T1,T9,T15

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T15,T25

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	522575150	4716	0	0
DisabledNoTrigBkwd_A	522575150	176281	0	0
DisabledNoTrigFwd_A	522575150	260715093	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	4716	0	0
T4	31907	0	0	0
T13	4991	0	0	0
T14	46185	0	0	0
T27	1247	415	0	0
T38	42952	0	0	0
T50	4234	0	0	0
T51	4578	0	0	0
T52	6540	0	0	0
T53	16458	0	0	0
T54	35307	0	0	0
T74	0	365	0	0
T217	0	433	0	0
T218	0	719	0	0
T220	0	470	0	0
T221	0	669	0	0
T225	0	333	0	0
T226	0	1312	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	176281	0	0
T9	31608	2	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T14	0	6	0	0
T15	10645	1	0	0
T16	10272	174	0	0
T25	119482	10	0	0
T26	26808	53	0	0
T27	1247	10	0	0
T38	0	14	0	0
T50	4234	0	0	0
T53	0	12	0	0
T54	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	260715093	0	0
T1	1308	604	0	0
T2	6004	3939	0	0
T3	13615	3099	0	0
T9	31608	13613	0	0
T10	20805	19556	0	0
T11	13701	8124	0	0
T12	8124	2216	0	0
T15	10645	1905	0	0
T16	10272	582	0	0
T25	119482	9651	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T3 T9 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T9,T15
1	1	Covered	T3,T9,T15

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T50,T47,T198
1	1	Covered	T3,T9,T15

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T15,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T16,T50

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	522575150	4170	0	0
DisabledNoTrigBkwd_A	522575150	140040	0	0
DisabledNoTrigFwd_A	522575150	303827954	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	4170	0	0
T4	31907	0	0	0
T13	4991	0	0	0
T14	46185	0	0	0
T38	42952	0	0	0
T47	0	174	0	0
T50	4234	945	0	0
T51	4578	0	0	0
T52	6540	0	0	0
T53	16458	0	0	0
T54	35307	0	0	0
T55	2815	0	0	0
T114	0	350	0	0
T198	0	396	0	0
T223	0	771	0	0
T224	0	758	0	0
T227	0	776	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	140040	0	0
T4	31907	0	0	0
T13	4991	0	0	0
T14	46185	0	0	0
T16	10272	9	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T28	0	1	0	0
T33	0	42	0	0
T38	42952	11	0	0
T40	0	21	0	0
T47	0	2	0	0
T49	0	2	0	0
T50	4234	6	0	0
T51	4578	0	0	0
T52	6540	1	0	0
T57	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	303827954	0	0
T1	1308	1256	0	0
T2	6004	3962	0	0
T3	13615	3112	0	0
T9	31608	20114	0	0
T10	20805	9597	0	0
T11	13701	13602	0	0
T12	8124	8040	0	0
T15	10645	5410	0	0
T16	10272	2144	0	0
T25	119482	119431	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T3 T9 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T9,T15
1	1	Covered	T9,T15,T10

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T51,T55,T219
1	1	Covered	T9,T15,T10

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T15,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T16,T38

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	522575150	3211	0	0
DisabledNoTrigBkwd_A	522575150	149071	0	0
DisabledNoTrigFwd_A	522575150	300327965	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	3211	0	0
T4	31907	0	0	0
T5	63586	0	0	0
T13	4991	0	0	0
T14	46185	0	0	0
T51	4578	1454	0	0
T52	6540	0	0	0
T53	16458	0	0	0
T54	35307	0	0	0
T55	2815	391	0	0
T56	12326	0	0	0
T219	0	1366	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	149071	0	0
T11	13701	3	0	0
T12	8124	0	0	0
T16	10272	16	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T28	0	1	0	0
T38	42952	2	0	0
T49	0	21	0	0
T50	4234	0	0	0
T51	4578	28	0	0
T52	6540	1	0	0
T54	0	119	0	0
T55	0	10	0	0
T81	0	6	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	300327965	0	0
T1	1308	1256	0	0
T2	6004	3973	0	0
T3	13615	3146	0	0
T9	31608	10197	0	0
T10	20805	19584	0	0
T11	13701	8507	0	0
T12	8124	2251	0	0
T15	10645	5635	0	0
T16	10272	590	0	0
T25	119482	112832	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T15,T10
1	1	Covered	T1,T2,T9

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T222
1	1	Covered	T1,T2,T9

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T16,T38

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	522575150	2676	0	0
DisabledNoTrigBkwd_A	522575150	149774	0	0
DisabledNoTrigFwd_A	522575150	300965324	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	2676	0	0
T2	6004	1750	0	0
T3	13615	0	0	0
T9	31608	0	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T15	10645	0	0	0
T16	10272	0	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T222	0	926	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	149774	0	0
T2	6004	32	0	0
T3	13615	0	0	0
T9	31608	0	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T14	0	15	0	0
T15	10645	0	0	0
T16	10272	11	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T33	0	2	0	0
T38	0	16	0	0
T40	0	4	0	0
T49	0	4	0	0
T54	0	31	0	0
T57	0	19	0	0
T81	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	300965324	0	0
T1	1308	616	0	0
T2	6004	3995	0	0
T3	13615	3167	0	0
T9	31608	22615	0	0
T10	20805	14525	0	0
T11	13701	8139	0	0
T12	8124	2263	0	0
T15	10645	10552	0	0
T16	10272	594	0	0
T25	119482	119431	0	0