Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_alert_receiver
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_alerts[0].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[1].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[2].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[3].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[4].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[5].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[6].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[7].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[8].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[9].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[10].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[11].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[12].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[13].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[14].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[15].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[16].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[17].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[18].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[19].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[20].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[21].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[22].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[23].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[24].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[25].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[26].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[27].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[28].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[29].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[30].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[31].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[32].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[33].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[34].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[35].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[36].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[37].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[38].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[39].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[40].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[41].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[42].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[43].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[44].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[45].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[46].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[47].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[48].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[49].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[50].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[51].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[52].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[53].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[54].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[55].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[56].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[57].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[58].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[59].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[60].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[61].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[62].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[63].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[64].u_alert_receiver 100.00 100.00



Module Instance : tb.dut.gen_alerts[0].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[1].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[2].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[3].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[4].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[5].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[6].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[7].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[8].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[9].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[10].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[11].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[12].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[13].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[14].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[15].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[16].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[17].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[18].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[19].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[20].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[21].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[22].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[23].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[24].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[25].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[26].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[27].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[28].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[29].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[30].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[31].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[32].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[33].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[34].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[35].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[36].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[37].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[38].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[39].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[40].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[41].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[42].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[43].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[44].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[45].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[46].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[47].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[48].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[49].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[50].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[51].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[52].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[53].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[54].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[55].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[56].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[57].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[58].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[59].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[60].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[61].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[62].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[63].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[64].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T15,T54,T57 Yes T15,T54,T57 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[0].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T15,T54,T61 Yes T15,T54,T61 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[1].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T36,T229,T230 Yes T36,T229,T230 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[2].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T15,T57,T75 Yes T15,T57,T75 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[3].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T36,T231,T41 Yes T36,T231,T41 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[4].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T54,T40,T104 Yes T54,T40,T104 OUTPUT
alert_o Yes Yes T2,T9,T15 Yes T2,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[5].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T15,T54,T57 Yes T15,T54,T57 OUTPUT
alert_o Yes Yes T2,T9,T15 Yes T2,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[6].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T16,T61,T41 Yes T16,T61,T41 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[7].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T29,T231,T136 Yes T29,T231,T136 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[8].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T54,T40,T36 Yes T54,T40,T36 OUTPUT
alert_o Yes Yes T9,T10,T25 Yes T9,T10,T25 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T3,T9,T10 Yes T3,T9,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T3,T9,T10 Yes T3,T9,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[9].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T16,T52,T54 Yes T16,T52,T54 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[10].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T104,T136,T67 Yes T104,T136,T67 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[11].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T15,T61,T41 Yes T15,T61,T41 OUTPUT
alert_o Yes Yes T9,T15,T10 Yes T9,T15,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T3,T9,T15 Yes T3,T9,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T3,T9,T15 Yes T3,T9,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[12].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T40,T29,T41 Yes T40,T29,T41 OUTPUT
alert_o Yes Yes T9,T15,T10 Yes T9,T15,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T3,T9,T15 Yes T3,T9,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T3,T9,T15 Yes T3,T9,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[13].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T15,T57,T36 Yes T15,T57,T36 OUTPUT
alert_o Yes Yes T2,T9,T15 Yes T2,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[14].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T16,T54,T36 Yes T16,T54,T36 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[15].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T29,T231,T63 Yes T29,T231,T63 OUTPUT
alert_o Yes Yes T2,T9,T10 Yes T2,T9,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[16].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T29,T63,T66 Yes T29,T63,T66 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[17].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T54,T40,T104 Yes T54,T40,T104 OUTPUT
alert_o Yes Yes T9,T15,T10 Yes T9,T15,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T3,T9,T15 Yes T3,T9,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T3,T9,T15 Yes T3,T9,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[18].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T11,T41,T229 Yes T11,T41,T229 OUTPUT
alert_o Yes Yes T9,T15,T10 Yes T9,T15,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T3,T9,T15 Yes T3,T9,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T3,T9,T15 Yes T3,T9,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[19].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T52,T57,T75 Yes T52,T57,T75 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[20].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T57,T110,T63 Yes T57,T110,T63 OUTPUT
alert_o Yes Yes T2,T9,T15 Yes T2,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[21].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T15,T11,T61 Yes T15,T11,T61 OUTPUT
alert_o Yes Yes T1,T9,T10 Yes T1,T9,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[22].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T61,T231,T229 Yes T61,T231,T229 OUTPUT
alert_o Yes Yes T2,T9,T15 Yes T2,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[23].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T57,T61,T29 Yes T57,T61,T29 OUTPUT
alert_o Yes Yes T2,T9,T15 Yes T2,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[24].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T54,T29,T41 Yes T54,T29,T41 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[25].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T75,T104,T110 Yes T75,T104,T110 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[26].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T16,T54,T40 Yes T16,T54,T40 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[27].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T54,T57,T36 Yes T54,T57,T36 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[28].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T57,T75,T64 Yes T57,T75,T64 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[29].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T16,T36,T110 Yes T16,T36,T110 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[30].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T15,T61,T41 Yes T15,T61,T41 OUTPUT
alert_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T3,T9,T10 Yes T3,T9,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T3,T9,T15 Yes T3,T9,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[31].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T15,T57,T75 Yes T15,T57,T75 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[32].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T40,T75,T136 Yes T40,T75,T136 OUTPUT
alert_o Yes Yes T9,T15,T10 Yes T9,T15,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T3,T9,T15 Yes T3,T9,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T3,T9,T15 Yes T3,T9,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[33].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T229,T66,T232 Yes T229,T66,T232 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[34].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T16,T29,T64 Yes T16,T29,T64 OUTPUT
alert_o Yes Yes T9,T15,T10 Yes T9,T15,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T3,T9,T15 Yes T3,T9,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T3,T9,T15 Yes T3,T9,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[35].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T15,T54,T75 Yes T15,T54,T75 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[36].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T15,T16,T110 Yes T15,T16,T110 OUTPUT
alert_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T3,T9,T10 Yes T3,T9,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T3,T9,T15 Yes T3,T9,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[37].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T40,T41,T64 Yes T40,T41,T64 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[38].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T54,T29,T136 Yes T54,T29,T136 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[39].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T61,T37,T63 Yes T61,T37,T63 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[40].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T52,T36,T110 Yes T52,T36,T110 OUTPUT
alert_o Yes Yes T2,T9,T10 Yes T2,T9,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[41].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T54,T57,T36 Yes T54,T57,T36 OUTPUT
alert_o Yes Yes T2,T9,T15 Yes T2,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[42].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T54,T40,T61 Yes T54,T40,T61 OUTPUT
alert_o Yes Yes T2,T9,T15 Yes T2,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[43].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T52,T75,T231 Yes T52,T75,T231 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[44].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T40,T75,T64 Yes T40,T75,T64 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[45].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T29,T89,T41 Yes T29,T89,T41 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[46].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T16,T61,T231 Yes T16,T61,T231 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[47].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T54,T61,T29 Yes T54,T61,T29 OUTPUT
alert_o Yes Yes T2,T9,T15 Yes T2,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[48].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T54,T57,T75 Yes T54,T57,T75 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[49].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T16,T54,T41 Yes T16,T54,T41 OUTPUT
alert_o Yes Yes T9,T15,T10 Yes T9,T15,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T3,T9,T15 Yes T3,T9,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T3,T9,T15 Yes T3,T9,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[50].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T29,T231,T64 Yes T29,T231,T64 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[51].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T11,T40,T29 Yes T11,T40,T29 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[52].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T57,T231,T37 Yes T57,T231,T37 OUTPUT
alert_o Yes Yes T9,T15,T10 Yes T9,T15,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T3,T9,T15 Yes T3,T9,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T3,T9,T15 Yes T3,T9,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[53].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T57,T110,T29 Yes T57,T110,T29 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[54].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T15,T52,T54 Yes T15,T52,T54 OUTPUT
alert_o Yes Yes T2,T9,T15 Yes T2,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[55].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T104,T63,T136 Yes T104,T63,T136 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[56].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T110,T231,T89 Yes T110,T231,T89 OUTPUT
alert_o Yes Yes T9,T15,T10 Yes T9,T15,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T3,T9,T15 Yes T3,T9,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T3,T9,T15 Yes T3,T9,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[57].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T54,T75,T61 Yes T54,T75,T61 OUTPUT
alert_o Yes Yes T9,T15,T10 Yes T9,T15,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T3,T9,T15 Yes T3,T9,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T3,T9,T15 Yes T3,T9,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[58].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T11,T52,T57 Yes T11,T52,T57 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[59].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T61,T29,T41 Yes T61,T29,T41 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[60].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T15,T229,T66 Yes T15,T229,T66 OUTPUT
alert_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T3,T9,T10 Yes T3,T9,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T3,T9,T15 Yes T3,T9,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[61].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T11,T54,T57 Yes T11,T54,T57 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[62].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T57,T75,T29 Yes T57,T75,T29 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[63].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T15,T40,T136 Yes T15,T40,T136 OUTPUT
alert_o Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[64].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T3,T4,T5 Yes T2,T3,T9 INPUT
ping_req_i Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
ping_ok_o Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
integ_fail_o Yes Yes T63,T232,T130 Yes T63,T232,T130 OUTPUT
alert_o Yes Yes T1,T9,T15 Yes T1,T9,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T9 Yes T1,T3,T9 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%