Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T3 T9 T11 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T3 T9 T11 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T3 T9 T11 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T15 T10 
159        1/1                    state_d = TimeoutSt;
           Tests:       T1 T15 T10 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T1 T15 T10 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T1 T15 T10 
172        1/1                    state_d    = Phase0St;
           Tests:       T15 T10 T16 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T15 T10 T16 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T15 T10 T16 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T15 T10 T16 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T1 T15 T10 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T15 T10 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T1 T15 T10 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T15 T10 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T9 T15 T10 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T9 T15 T10 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T9 T15 T10 
190        1/1                  esc_state_o = Phase0;
           Tests:       T9 T15 T10 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T9 T15 T10 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T9 T15 T10 
194        1/1                    state_d = IdleSt;
           Tests:       T16 T26 T28 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T16 T26 T28 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T16 T26 T28 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T9 T15 T10 
198        1/1                    state_d = Phase1St;
           Tests:       T9 T15 T10 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T9 T15 T10 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T9 T15 T10 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T9 T15 T10 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T9 T15 T10 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T9 T15 T10 
207        1/1                  esc_state_o = Phase1;
           Tests:       T9 T15 T10 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T9 T15 T10 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T9 T15 T10 
211        1/1                    state_d = IdleSt;
           Tests:       T29 T30 T31 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T30 T31 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T29 T30 T31 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T9 T15 T10 
215        1/1                    state_d = Phase2St;
           Tests:       T9 T15 T10 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T9 T15 T10 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T9 T15 T10 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T9 T15 T10 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T9 T15 T10 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T9 T15 T10 
224        1/1                  esc_state_o = Phase2;
           Tests:       T9 T15 T10 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T9 T15 T10 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T9 T15 T10 
229        1/1                    state_d = IdleSt;
           Tests:       T32 T33 T34 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T34 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T32 T33 T34 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T9 T15 T10 
233        1/1                    state_d = Phase3St;
           Tests:       T9 T15 T10 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T9 T15 T10 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T9 T15 T10 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T9 T15 T10 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T9 T15 T10 
241        1/1                  esc_state_o = Phase3;
           Tests:       T9 T15 T10 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T9 T15 T10 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T9 T15 T10 
245        1/1                    state_d = IdleSt;
           Tests:       T35 T36 T37 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T36 T37 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T36 T37 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T9 T15 T10 
249        1/1                    state_d = TerminalSt;
           Tests:       T9 T15 T10 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T9 T15 T10 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T9 T15 T10 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T9 T15 T10 
259        1/1                  esc_state_o = Terminal;
           Tests:       T9 T15 T10 
260        1/1                  if (clr_i) begin
           Tests:       T9 T15 T10 
261        1/1                    state_d = IdleSt;
           Tests:       T9 T26 T38 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T39
1	1	1	Covered	T3,T9,T11

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T15,T10
1	0	1	Covered	T9,T15,T27
1	1	0	Covered	T1,T15,T10
1	1	1	Covered	T1,T15,T10

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T10
0	1	Covered	T15,T10,T16
1	0	Covered	T28,T40,T32

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T15,T10
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T28,T40,T32

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T10
1	0	Not Covered
1	1	Covered	T15,T10,T16

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T9,T15,T11
1	Covered	T10,T26,T27

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T10,T11
1	Covered	T9,T25,T16

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T9,T15,T10
1	Covered	T11,T26,T38

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T9,T10,T11
1	Covered	T15,T26,T38

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T9,T10,T25

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T15,T25,T26

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T15,T10,T11

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T9,T15,T10
Phase1St	198	Covered	T9,T15,T10
Phase2St	215	Covered	T9,T15,T10
Phase3St	233	Covered	T9,T15,T10
TerminalSt	249	Covered	T9,T15,T10
TimeoutSt	159	Covered	T1,T15,T10

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T6,T7,T8
IdleSt->Phase0St	152	Covered	T9,T11,T25
IdleSt->TimeoutSt	159	Covered	T1,T15,T10
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T16,T26,T28
Phase0St->Phase1St	198	Covered	T9,T15,T10
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T29,T41,T30
Phase1St->Phase2St	215	Covered	T9,T15,T10
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T32,T33,T36
Phase2St->Phase3St	233	Covered	T9,T15,T10
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T35,T36,T37
Phase3St->TerminalSt	249	Covered	T9,T15,T10
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T9,T16,T26
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T15,T10
TimeoutSt->Phase0St	172	Covered	T15,T10,T16

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T11
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T15,T10
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T10,T16
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T15,T10
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T15,T10
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T16,T26,T28
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T9,T15,T10
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T9,T15,T10
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T30,T31
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T9,T15,T10
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T9,T15,T10
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T33,T34
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T9,T15,T10
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T9,T15,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T35,T36,T37
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T9,T15,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T9,T15,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T26,T38
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T9,T15,T10
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2090300600	1158	0	0
CheckAccumTrig0_A	2090300600	2216	0	0
CheckAccumTrig1_A	2090300600	107	0	0
CheckClr_A	2090300600	997	0	0
CheckEn_A	2089038584	924968062	0	0
CheckPhase0_A	2090300600	2446	0	0
CheckPhase1_A	2090300600	2378	0	0
CheckPhase2_A	2090300600	2326	0	0
CheckPhase3_A	2090300600	2284	0	0
CheckTimeout0_A	2090300600	4796	0	0
CheckTimeoutSt1_A	2090300600	450335	0	0
CheckTimeoutSt2_A	2090300600	4469	0	0
CheckTimeoutStTrig_A	2090300600	198	0	0
ErrorStAllEscAsserted_A	2090300600	5862	0	0
ErrorStIsTerminal_A	2090300600	4782	0	0
EscStateOut_A	2089029156	2088753740	0	0
u_state_regs_A	2090300600	2089567948	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	1158	0	0
T6	140244	237	0	0
T7	461088	273	0	0
T8	168344	269	0	0
T42	237256	122	0	0
T43	0	257	0	0
T44	190152	0	0	0
T45	224924	0	0	0
T46	313520	0	0	0
T47	3612	0	0	0
T48	332484	0	0	0
T49	238312	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	2216	0	0
T2	6004	0	0	0
T3	13615	0	0	0
T4	31907	0	0	0
T9	63216	1	0	0
T10	41610	0	0	0
T11	41103	1	0	0
T12	24372	0	0	0
T13	4991	0	0	0
T14	46185	1	0	0
T15	21290	0	0	0
T16	41088	3	0	0
T25	358446	1	0	0
T26	107232	5	0	0
T27	3741	1	0	0
T33	0	1	0	0
T38	85904	6	0	0
T40	0	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	12702	1	0	0
T51	9156	1	0	0
T52	13080	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	107	0	0
T6	35061	0	0	0
T7	115272	0	0	0
T8	42086	0	0	0
T20	24518	0	0	0
T24	21101	0	0	0
T28	3325	1	0	0
T29	0	1	0	0
T32	38827	4	0	0
T33	49817	1	0	0
T35	108876	0	0	0
T36	218327	4	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	47538	0	0	0
T45	56231	0	0	0
T46	78380	0	0	0
T47	903	0	0	0
T48	83121	0	0	0
T57	13248	0	0	0
T58	25946	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	11610	0	0	0
T74	1061	0	0	0
T75	43467	0	0	0
T76	2523	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	997	0	0
T4	95721	0	0	0
T9	31608	1	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T13	14973	0	0	0
T14	138555	0	0	0
T15	10645	0	0	0
T16	30816	1	0	0
T25	119482	0	0	0
T26	80424	4	0	0
T27	3741	0	0	0
T28	0	1	0	0
T32	0	4	0	0
T33	0	4	0	0
T35	0	2	0	0
T36	0	3	0	0
T38	128856	5	0	0
T40	0	8	0	0
T50	12702	0	0	0
T51	13734	0	0	0
T52	19620	1	0	0
T53	16458	1	0	0
T54	35307	0	0	0
T55	2815	0	0	0
T56	12326	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	6	0	0
T61	0	1	0	0
T76	0	2	0	0
T77	0	5	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2089038584	924968062	0	0
T1	5232	3730	0	0
T2	24016	15869	0	0
T3	54460	12520	0	0
T9	126432	65581	0	0
T10	83220	56368	0	0
T11	54804	38369	0	0
T12	32496	14769	0	0
T15	42580	23500	0	0
T16	41088	3910	0	0
T25	477928	361342	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	2446	0	0
T2	6004	0	0	0
T3	13615	0	0	0
T9	63216	1	0	0
T10	62415	1	0	0
T11	54804	1	0	0
T12	32496	0	0	0
T14	0	1	0	0
T15	21290	1	0	0
T16	41088	3	0	0
T25	477928	1	0	0
T26	107232	4	0	0
T27	3741	1	0	0
T28	0	1	0	0
T38	85904	7	0	0
T40	0	3	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	12702	1	0	0
T51	9156	1	0	0
T52	6540	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	1	0	0
T57	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	2378	0	0
T2	6004	0	0	0
T3	13615	0	0	0
T9	63216	1	0	0
T10	62415	1	0	0
T11	54804	1	0	0
T12	32496	0	0	0
T14	0	1	0	0
T15	21290	1	0	0
T16	41088	3	0	0
T25	477928	1	0	0
T26	107232	4	0	0
T27	3741	1	0	0
T28	0	1	0	0
T38	85904	7	0	0
T40	0	3	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	12702	1	0	0
T51	9156	1	0	0
T52	6540	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	1	0	0
T57	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	2326	0	0
T2	6004	0	0	0
T3	13615	0	0	0
T9	63216	1	0	0
T10	62415	1	0	0
T11	54804	1	0	0
T12	32496	0	0	0
T14	0	1	0	0
T15	21290	1	0	0
T16	41088	3	0	0
T25	477928	1	0	0
T26	107232	4	0	0
T27	3741	1	0	0
T28	0	1	0	0
T38	85904	7	0	0
T40	0	3	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	12702	1	0	0
T51	9156	1	0	0
T52	6540	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	1	0	0
T57	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	2284	0	0
T2	6004	0	0	0
T3	13615	0	0	0
T9	63216	1	0	0
T10	62415	1	0	0
T11	54804	1	0	0
T12	32496	0	0	0
T14	0	1	0	0
T15	21290	1	0	0
T16	41088	3	0	0
T25	477928	1	0	0
T26	107232	4	0	0
T27	3741	1	0	0
T28	0	1	0	0
T38	85904	7	0	0
T40	0	3	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	12702	1	0	0
T51	9156	1	0	0
T52	6540	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	1	0	0
T57	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	4796	0	0
T1	1308	1	0	0
T2	6004	0	0	0
T3	13615	0	0	0
T9	31608	0	0	0
T10	83220	5	0	0
T11	54804	0	0	0
T12	32496	4	0	0
T14	0	3	0	0
T15	31935	3	0	0
T16	41088	3	0	0
T25	477928	0	0	0
T26	80424	0	0	0
T27	3741	0	0	0
T28	0	1	0	0
T38	128856	3	0	0
T40	0	4	0	0
T49	0	1	0	0
T50	12702	0	0	0
T51	4578	0	0	0
T52	0	1	0	0
T57	0	4	0	0
T58	0	1	0	0
T75	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	12	0	0
T84	0	10	0	0
T85	0	1	0	0
T86	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	450335	0	0
T1	1308	45	0	0
T2	6004	0	0	0
T3	13615	0	0	0
T9	31608	0	0	0
T10	83220	472	0	0
T11	54804	0	0	0
T12	32496	664	0	0
T14	0	158	0	0
T15	31935	1299	0	0
T16	41088	388	0	0
T25	477928	0	0	0
T26	80424	0	0	0
T27	3741	0	0	0
T28	0	8	0	0
T38	128856	680	0	0
T40	0	982	0	0
T49	0	264	0	0
T50	12702	0	0	0
T51	4578	0	0	0
T52	0	475	0	0
T57	0	259	0	0
T58	0	28	0	0
T75	0	156	0	0
T81	0	17	0	0
T82	0	69	0	0
T83	0	616	0	0
T84	0	709	0	0
T85	0	170	0	0
T86	0	650	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	4469	0	0
T1	1308	1	0	0
T2	6004	0	0	0
T3	13615	0	0	0
T9	31608	0	0	0
T10	83220	4	0	0
T11	54804	0	0	0
T12	32496	4	0	0
T14	0	3	0	0
T15	31935	2	0	0
T16	41088	2	0	0
T25	477928	0	0	0
T26	80424	0	0	0
T27	3741	0	0	0
T38	128856	2	0	0
T40	0	2	0	0
T49	0	1	0	0
T50	12702	0	0	0
T51	4578	0	0	0
T52	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	4	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	12	0	0
T84	0	9	0	0
T85	0	1	0	0
T86	0	4	0	0
T87	0	7	0	0
T88	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	198	0	0
T10	41610	1	0	0
T11	27402	0	0	0
T12	16248	0	0	0
T15	10645	1	0	0
T16	20544	1	0	0
T25	238964	0	0	0
T26	53616	0	0	0
T27	2494	0	0	0
T32	38827	0	0	0
T33	49817	0	0	0
T35	108876	0	0	0
T36	0	1	0	0
T38	85904	1	0	0
T40	26647	1	0	0
T41	0	1	0	0
T50	8468	0	0	0
T51	4578	0	0	0
T57	13248	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T73	11610	0	0	0
T74	1061	0	0	0
T75	43467	1	0	0
T77	62047	0	0	0
T78	0	1	0	0
T84	0	1	0	0
T86	90485	0	0	0
T87	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	2	0	0
T92	0	3	0	0
T93	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	5862	0	0
T6	140244	1278	0	0
T7	461088	1219	0	0
T8	168344	1309	0	0
T42	237256	720	0	0
T43	0	1336	0	0
T44	190152	0	0	0
T45	224924	0	0	0
T46	313520	0	0	0
T47	3612	0	0	0
T48	332484	0	0	0
T49	238312	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	4782	0	0
T6	140244	1038	0	0
T7	461088	979	0	0
T8	168344	1069	0	0
T42	237256	600	0	0
T43	0	1096	0	0
T44	190152	0	0	0
T45	224924	0	0	0
T46	313520	0	0	0
T47	3612	0	0	0
T48	332484	0	0	0
T49	238312	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2089029156	2088753740	0	0
T1	5232	5024	0	0
T2	24016	23796	0	0
T3	54460	53844	0	0
T9	126432	126172	0	0
T10	83220	82828	0	0
T11	54804	54408	0	0
T12	32496	32160	0	0
T15	42580	42208	0	0
T16	41088	40764	0	0
T25	477928	477724	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090300600	2089567948	0	0
T1	5232	5024	0	0
T2	24016	23796	0	0
T3	54460	53844	0	0
T9	126432	126172	0	0
T10	83220	82828	0	0
T11	54804	54408	0	0
T12	32496	32160	0	0
T15	42580	42208	0	0
T16	41088	40764	0	0
T25	477928	477724	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T3 T16 T50 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T3 T16 T50 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T3 T16 T50 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T15 T10 T16 
159        1/1                    state_d = TimeoutSt;
           Tests:       T15 T10 T16 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T15 T10 T16 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T15 T10 T16 
172        1/1                    state_d    = Phase0St;
           Tests:       T10 T16 T28 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T10 T16 T28 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T10 T16 T28 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T10 T16 T28 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T15 T10 T16 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T15 T10 T16 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T15 T16 T38 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T15 T16 T38 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T16 T50 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T10 T16 T50 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T10 T16 T50 
190        1/1                  esc_state_o = Phase0;
           Tests:       T10 T16 T50 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T10 T16 T50 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T10 T16 T50 
194        1/1                    state_d = IdleSt;
           Tests:       T16 T94 T95 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T16 T94 T95 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T16 T94 T95 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T16 T50 
198        1/1                    state_d = Phase1St;
           Tests:       T10 T16 T50 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T16 T50 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T16 T50 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T16 T50 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T10 T16 T50 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T10 T16 T50 
207        1/1                  esc_state_o = Phase1;
           Tests:       T10 T16 T50 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T10 T16 T50 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T10 T16 T50 
211        1/1                    state_d = IdleSt;
           Tests:       T64 T69 T94 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T64 T69 T94 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T64 T69 T94 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T16 T50 
215        1/1                    state_d = Phase2St;
           Tests:       T10 T16 T50 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T16 T50 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T16 T50 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T16 T50 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T10 T16 T50 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T10 T16 T50 
224        1/1                  esc_state_o = Phase2;
           Tests:       T10 T16 T50 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T10 T16 T50 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T10 T16 T50 
229        1/1                    state_d = IdleSt;
           Tests:       T79 T96 T97 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T79 T96 T97 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T79 T96 T97 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T16 T50 
233        1/1                    state_d = Phase3St;
           Tests:       T10 T16 T50 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T16 T50 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T16 T50 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T10 T16 T50 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T10 T16 T50 
241        1/1                  esc_state_o = Phase3;
           Tests:       T10 T16 T50 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T10 T16 T50 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T10 T16 T50 
245        1/1                    state_d = IdleSt;
           Tests:       T36 T95 T98 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T36 T95 T98 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T36 T95 T98 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T16 T50 
249        1/1                    state_d = TerminalSt;
           Tests:       T10 T16 T50 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T16 T50 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T10 T16 T50 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T10 T16 T50 
259        1/1                  esc_state_o = Terminal;
           Tests:       T10 T16 T50 
260        1/1                  if (clr_i) begin
           Tests:       T10 T16 T50 
261        1/1                    state_d = IdleSt;
           Tests:       T38 T40 T57 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T3,T15,T10
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T15,T10,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T15,T10

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T9
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T16,T50

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T10,T16
1	0	1	Covered	T9,T15,T50
1	1	0	Covered	T10,T11,T14
1	1	1	Covered	T15,T10,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T15,T10,T16
0	1	Covered	T10,T16,T75
1	0	Covered	T28,T40,T33

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T15,T10,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T28,T40,T33

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T10,T16
1	0	Not Covered
1	1	Covered	T10,T16,T75

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T16,T38,T49
1	Covered	T10,T50,T38

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T50,T38
1	Covered	T16,T38,T40

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T16,T50
1	Covered	T38,T58,T36

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T16,T50
1	Covered	T49,T40,T57

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T10,T16,T50

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T10,T16,T50

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T50,T38,T47

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T10,T50,T38

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T10,T16,T50
Phase1St	198	Covered	T10,T16,T50
Phase2St	215	Covered	T10,T16,T50
Phase3St	233	Covered	T10,T16,T50
TerminalSt	249	Covered	T10,T16,T50
TimeoutSt	159	Covered	T15,T10,T16

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T6,T7,T8
IdleSt->Phase0St	152	Covered	T16,T50,T38
IdleSt->TimeoutSt	159	Covered	T15,T10,T16
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T16,T41,T63
Phase0St->Phase1St	198	Covered	T10,T16,T50
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T64,T69,T94
Phase1St->Phase2St	215	Covered	T10,T16,T50
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T79,T96,T97
Phase2St->Phase3St	233	Covered	T10,T16,T50
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T36,T95,T98
Phase3St->TerminalSt	249	Covered	T10,T16,T50
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T38,T40,T57
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T15,T16,T38
TimeoutSt->Phase0St	172	Covered	T10,T16,T28

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T16,T50
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T10,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T10,T16,T28
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T15,T10,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T38
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T16,T94,T95
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T10,T16,T50
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T16,T38
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T64,T69,T94
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T10,T16,T50
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T10,T16,T38
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T79,T96,T97
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T10,T16,T50
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T16,T38
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T36,T95,T98
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T10,T16,T50
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T16,T38
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T38,T40,T57
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T16,T50
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	522575150	290	0	0
CheckAccumTrig0_A	522575150	474	0	0
CheckAccumTrig1_A	522575150	24	0	0
CheckClr_A	522575150	201	0	0
CheckEn_A	522259646	228054582	0	0
CheckPhase0_A	522575150	533	0	0
CheckPhase1_A	522575150	523	0	0
CheckPhase2_A	522575150	514	0	0
CheckPhase3_A	522575150	505	0	0
CheckTimeout0_A	522575150	926	0	0
CheckTimeoutSt1_A	522575150	89038	0	0
CheckTimeoutSt2_A	522575150	839	0	0
CheckTimeoutStTrig_A	522575150	53	0	0
ErrorStAllEscAsserted_A	522575150	1475	0	0
ErrorStIsTerminal_A	522575150	1205	0	0
EscStateOut_A	522257289	522188435	0	0
u_state_regs_A	522575150	522391987	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	290	0	0
T6	35061	59	0	0
T7	115272	75	0	0
T8	42086	55	0	0
T42	59314	29	0	0
T43	0	72	0	0
T44	47538	0	0	0
T45	56231	0	0	0
T46	78380	0	0	0
T47	903	0	0	0
T48	83121	0	0	0
T49	59578	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	474	0	0
T4	31907	0	0	0
T13	4991	0	0	0
T14	46185	0	0	0
T16	10272	1	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T33	0	1	0	0
T38	42952	3	0	0
T40	0	2	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	4234	1	0	0
T51	4578	0	0	0
T52	6540	1	0	0
T57	0	1	0	0
T58	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	24	0	0
T6	35061	0	0	0
T7	115272	0	0	0
T8	42086	0	0	0
T20	24518	0	0	0
T28	3325	1	0	0
T33	0	1	0	0
T36	0	2	0	0
T40	0	1	0	0
T44	47538	0	0	0
T45	56231	0	0	0
T46	78380	0	0	0
T47	903	0	0	0
T48	83121	0	0	0
T64	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T69	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	201	0	0
T4	31907	0	0	0
T13	4991	0	0	0
T14	46185	0	0	0
T16	10272	1	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T33	0	1	0	0
T36	0	2	0	0
T38	42952	2	0	0
T40	0	2	0	0
T50	4234	0	0	0
T51	4578	0	0	0
T52	6540	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T61	0	1	0	0
T76	0	1	0	0
T79	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522259646	228054582	0	0
T1	1308	1255	0	0
T2	6004	3962	0	0
T3	13615	3111	0	0
T9	31608	20113	0	0
T10	20805	2706	0	0
T11	13701	13601	0	0
T12	8124	8039	0	0
T15	10645	5410	0	0
T16	10272	2144	0	0
T25	119482	119430	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	533	0	0
T10	20805	1	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T16	10272	1	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T28	0	1	0	0
T38	42952	3	0	0
T40	0	3	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	4234	1	0	0
T51	4578	0	0	0
T52	0	1	0	0
T57	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	523	0	0
T10	20805	1	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T16	10272	1	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T28	0	1	0	0
T38	42952	3	0	0
T40	0	3	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	4234	1	0	0
T51	4578	0	0	0
T52	0	1	0	0
T57	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	514	0	0
T10	20805	1	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T16	10272	1	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T28	0	1	0	0
T38	42952	3	0	0
T40	0	3	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	4234	1	0	0
T51	4578	0	0	0
T52	0	1	0	0
T57	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	505	0	0
T10	20805	1	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T16	10272	1	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T28	0	1	0	0
T38	42952	3	0	0
T40	0	3	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	4234	1	0	0
T51	4578	0	0	0
T52	0	1	0	0
T57	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	926	0	0
T10	20805	1	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T15	10645	1	0	0
T16	10272	2	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T28	0	1	0	0
T38	42952	1	0	0
T40	0	1	0	0
T50	4234	0	0	0
T57	0	1	0	0
T83	0	6	0	0
T84	0	1	0	0
T86	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	89038	0	0
T10	20805	10	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T15	10645	529	0	0
T16	10272	385	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T28	0	8	0	0
T38	42952	177	0	0
T40	0	8	0	0
T50	4234	0	0	0
T57	0	11	0	0
T83	0	361	0	0
T84	0	76	0	0
T86	0	164	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	839	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T15	10645	1	0	0
T16	10272	1	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T38	42952	1	0	0
T50	4234	0	0	0
T57	0	1	0	0
T59	0	2	0	0
T83	0	6	0	0
T84	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	53	0	0
T10	20805	1	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T16	10272	1	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T36	0	1	0	0
T38	42952	0	0	0
T41	0	1	0	0
T50	4234	0	0	0
T51	4578	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T75	0	1	0	0
T87	0	1	0	0
T89	0	1	0	0
T91	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	1475	0	0
T6	35061	317	0	0
T7	115272	326	0	0
T8	42086	317	0	0
T42	59314	174	0	0
T43	0	341	0	0
T44	47538	0	0	0
T45	56231	0	0	0
T46	78380	0	0	0
T47	903	0	0	0
T48	83121	0	0	0
T49	59578	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	1205	0	0
T6	35061	257	0	0
T7	115272	266	0	0
T8	42086	257	0	0
T42	59314	144	0	0
T43	0	281	0	0
T44	47538	0	0	0
T45	56231	0	0	0
T46	78380	0	0	0
T47	903	0	0	0
T48	83121	0	0	0
T49	59578	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522257289	522188435	0	0
T1	1308	1256	0	0
T2	6004	5949	0	0
T3	13615	13461	0	0
T9	31608	31543	0	0
T10	20805	20707	0	0
T11	13701	13602	0	0
T12	8124	8040	0	0
T15	10645	10552	0	0
T16	10272	10191	0	0
T25	119482	119431	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	522391987	0	0
T1	1308	1256	0	0
T2	6004	5949	0	0
T3	13615	13461	0	0
T9	31608	31543	0	0
T10	20805	20707	0	0
T11	13701	13602	0	0
T12	8124	8040	0	0
T15	10645	10552	0	0
T16	10272	10191	0	0
T25	119482	119431	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T11 T16 T38 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T11 T16 T38 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T11 T16 T38 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T15 T10 T12 
159        1/1                    state_d = TimeoutSt;
           Tests:       T15 T10 T12 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T15 T10 T12 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T15 T10 T12 
172        1/1                    state_d    = Phase0St;
           Tests:       T40 T36 T61 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T40 T36 T61 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T40 T36 T61 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T40 T36 T61 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T15 T10 T12 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T15 T10 T12 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T15 T10 T12 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T15 T10 T12 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T11 T16 T38 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T11 T16 T38 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T11 T16 T38 
190        1/1                  esc_state_o = Phase0;
           Tests:       T11 T16 T38 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T11 T16 T38 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T11 T16 T38 
194        1/1                    state_d = IdleSt;
           Tests:       T28 T71 T99 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T71 T99 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T28 T71 T99 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T11 T16 T38 
198        1/1                    state_d = Phase1St;
           Tests:       T11 T16 T38 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T16 T38 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T11 T16 T38 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T11 T16 T38 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T11 T16 T38 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T11 T16 T38 
207        1/1                  esc_state_o = Phase1;
           Tests:       T11 T16 T38 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T11 T16 T38 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T11 T16 T38 
211        1/1                    state_d = IdleSt;
           Tests:       T31 T65 T100 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T65 T100 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T31 T65 T100 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T11 T16 T38 
215        1/1                    state_d = Phase2St;
           Tests:       T11 T16 T38 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T16 T38 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T11 T16 T38 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T11 T16 T38 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T11 T16 T38 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T11 T16 T38 
224        1/1                  esc_state_o = Phase2;
           Tests:       T11 T16 T38 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T11 T16 T38 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T11 T16 T38 
229        1/1                    state_d = IdleSt;
           Tests:       T33 T91 T101 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T91 T101 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T33 T91 T101 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T11 T16 T38 
233        1/1                    state_d = Phase3St;
           Tests:       T11 T16 T38 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T16 T38 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T11 T16 T38 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T11 T16 T38 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T11 T16 T38 
241        1/1                  esc_state_o = Phase3;
           Tests:       T11 T16 T38 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T11 T16 T38 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T11 T16 T38 
245        1/1                    state_d = IdleSt;
           Tests:       T102 T72 T103 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T102 T72 T103 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T102 T72 T103 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T11 T16 T38 
249        1/1                    state_d = TerminalSt;
           Tests:       T11 T16 T38 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T16 T38 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T11 T16 T38 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T11 T16 T38 
259        1/1                  esc_state_o = Terminal;
           Tests:       T11 T16 T38 
260        1/1                  if (clr_i) begin
           Tests:       T11 T16 T38 
261        1/1                    state_d = IdleSt;
           Tests:       T38 T52 T40 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T15,T10,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T15,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T10,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T9
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T11,T16,T38

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T10,T11
1	0	1	Covered	T9,T51,T54
1	1	0	Covered	T1,T15,T10
1	1	1	Covered	T15,T10,T12

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T15,T10,T12
0	1	Covered	T40,T91,T93
1	0	Covered	T36,T61,T41

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T15,T10,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T36,T61,T41

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T10,T12
1	0	Not Covered
1	1	Covered	T40,T91,T93

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T11,T16,T38
1	Covered	T51,T55,T40

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T11,T38,T51
1	Covered	T16,T58,T104

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T16,T51,T54
1	Covered	T11,T38,T52

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T16,T38
1	Covered	T54,T81,T49

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T38,T51,T54

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T11,T16,T51

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T51,T55,T81

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T11,T16,T38

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T11,T16,T38
Phase1St	198	Covered	T11,T16,T38
Phase2St	215	Covered	T11,T16,T38
Phase3St	233	Covered	T11,T16,T38
TerminalSt	249	Covered	T11,T16,T38
TimeoutSt	159	Covered	T15,T10,T12

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T6,T7,T8
IdleSt->Phase0St	152	Covered	T11,T16,T38
IdleSt->TimeoutSt	159	Covered	T15,T10,T12
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T28,T59,T36
Phase0St->Phase1St	198	Covered	T11,T16,T38
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T31,T65,T100
Phase1St->Phase2St	215	Covered	T11,T16,T38
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T33,T91,T101
Phase2St->Phase3St	233	Covered	T11,T16,T38
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T102,T72,T103
Phase3St->TerminalSt	249	Covered	T11,T16,T38
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T38,T52,T40
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T15,T10,T12
TimeoutSt->Phase0St	172	Covered	T40,T36,T61

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T16,T38
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T10,T12
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T40,T36,T61
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T15,T10,T12
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T15,T10,T12
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T71,T99
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T11,T16,T38
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T11,T16,T38
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T65,T100
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T11,T16,T38
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T11,T16,T38
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T33,T91,T101
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T11,T16,T38
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T11,T16,T38
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T102,T72,T103
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T11,T16,T38
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T11,T16,T38
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T38,T52,T40
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T11,T16,T38
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	522575150	273	0	0
CheckAccumTrig0_A	522575150	486	0	0
CheckAccumTrig1_A	522575150	18	0	0
CheckClr_A	522575150	202	0	0
CheckEn_A	522259646	236059736	0	0
CheckPhase0_A	522575150	525	0	0
CheckPhase1_A	522575150	514	0	0
CheckPhase2_A	522575150	508	0	0
CheckPhase3_A	522575150	499	0	0
CheckTimeout0_A	522575150	1198	0	0
CheckTimeoutSt1_A	522575150	103150	0	0
CheckTimeoutSt2_A	522575150	1143	0	0
CheckTimeoutStTrig_A	522575150	35	0	0
ErrorStAllEscAsserted_A	522575150	1488	0	0
ErrorStIsTerminal_A	522575150	1218	0	0
EscStateOut_A	522257289	522188435	0	0
u_state_regs_A	522575150	522391987	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	273	0	0
T6	35061	53	0	0
T7	115272	64	0	0
T8	42086	68	0	0
T42	59314	32	0	0
T43	0	56	0	0
T44	47538	0	0	0
T45	56231	0	0	0
T46	78380	0	0	0
T47	903	0	0	0
T48	83121	0	0	0
T49	59578	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	486	0	0
T11	13701	1	0	0
T12	8124	0	0	0
T16	10272	1	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T28	0	1	0	0
T38	42952	1	0	0
T49	0	1	0	0
T50	4234	0	0	0
T51	4578	1	0	0
T52	6540	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T81	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	18	0	0
T36	218327	1	0	0
T41	0	1	0	0
T61	177004	1	0	0
T65	0	1	0	0
T72	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	2	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	6180	0	0	0
T111	65511	0	0	0
T112	38631	0	0	0
T113	211741	0	0	0
T114	1105	0	0	0
T115	76525	0	0	0
T116	433001	0	0	0
T117	50707	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	202	0	0
T4	31907	0	0	0
T13	4991	0	0	0
T14	46185	0	0	0
T28	0	1	0	0
T33	0	2	0	0
T36	0	1	0	0
T38	42952	1	0	0
T40	0	4	0	0
T41	0	1	0	0
T51	4578	0	0	0
T52	6540	1	0	0
T53	16458	0	0	0
T54	35307	0	0	0
T55	2815	0	0	0
T56	12326	0	0	0
T59	0	6	0	0
T78	0	1	0	0
T80	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522259646	236059736	0	0
T1	1308	1255	0	0
T2	6004	3973	0	0
T3	13615	3145	0	0
T9	31608	10197	0	0
T10	20805	19583	0	0
T11	13701	8507	0	0
T12	8124	2251	0	0
T15	10645	5634	0	0
T16	10272	590	0	0
T25	119482	112831	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	525	0	0
T11	13701	1	0	0
T12	8124	0	0	0
T16	10272	1	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T38	42952	1	0	0
T49	0	1	0	0
T50	4234	0	0	0
T51	4578	1	0	0
T52	6540	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T81	0	1	0	0
T85	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	514	0	0
T11	13701	1	0	0
T12	8124	0	0	0
T16	10272	1	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T38	42952	1	0	0
T49	0	1	0	0
T50	4234	0	0	0
T51	4578	1	0	0
T52	6540	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T81	0	1	0	0
T85	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	508	0	0
T11	13701	1	0	0
T12	8124	0	0	0
T16	10272	1	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T38	42952	1	0	0
T49	0	1	0	0
T50	4234	0	0	0
T51	4578	1	0	0
T52	6540	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T81	0	1	0	0
T85	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	499	0	0
T11	13701	1	0	0
T12	8124	0	0	0
T16	10272	1	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T38	42952	1	0	0
T49	0	1	0	0
T50	4234	0	0	0
T51	4578	1	0	0
T52	6540	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T81	0	1	0	0
T85	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	1198	0	0
T10	20805	1	0	0
T11	13701	0	0	0
T12	8124	2	0	0
T15	10645	1	0	0
T16	10272	0	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T38	42952	0	0	0
T40	0	3	0	0
T49	0	1	0	0
T50	4234	0	0	0
T58	0	1	0	0
T81	0	1	0	0
T83	0	1	0	0
T84	0	8	0	0
T86	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	103150	0	0
T10	20805	146	0	0
T11	13701	0	0	0
T12	8124	332	0	0
T15	10645	572	0	0
T16	10272	0	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T38	42952	0	0	0
T40	0	974	0	0
T49	0	264	0	0
T50	4234	0	0	0
T58	0	28	0	0
T81	0	17	0	0
T83	0	42	0	0
T84	0	614	0	0
T86	0	164	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	1143	0	0
T10	20805	1	0	0
T11	13701	0	0	0
T12	8124	2	0	0
T15	10645	1	0	0
T16	10272	0	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T38	42952	0	0	0
T40	0	2	0	0
T49	0	1	0	0
T50	4234	0	0	0
T58	0	1	0	0
T81	0	1	0	0
T83	0	1	0	0
T84	0	8	0	0
T86	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	35	0	0
T32	38827	0	0	0
T33	49817	0	0	0
T35	108876	0	0	0
T40	26647	1	0	0
T57	13248	0	0	0
T71	0	1	0	0
T73	11610	0	0	0
T74	1061	0	0	0
T75	43467	0	0	0
T77	62047	0	0	0
T86	90485	0	0	0
T91	0	1	0	0
T93	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	1488	0	0
T6	35061	327	0	0
T7	115272	289	0	0
T8	42086	331	0	0
T42	59314	177	0	0
T43	0	364	0	0
T44	47538	0	0	0
T45	56231	0	0	0
T46	78380	0	0	0
T47	903	0	0	0
T48	83121	0	0	0
T49	59578	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	1218	0	0
T6	35061	267	0	0
T7	115272	229	0	0
T8	42086	271	0	0
T42	59314	147	0	0
T43	0	304	0	0
T44	47538	0	0	0
T45	56231	0	0	0
T46	78380	0	0	0
T47	903	0	0	0
T48	83121	0	0	0
T49	59578	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522257289	522188435	0	0
T1	1308	1256	0	0
T2	6004	5949	0	0
T3	13615	13461	0	0
T9	31608	31543	0	0
T10	20805	20707	0	0
T11	13701	13602	0	0
T12	8124	8040	0	0
T15	10645	10552	0	0
T16	10272	10191	0	0
T25	119482	119431	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	522391987	0	0
T1	1308	1256	0	0
T2	6004	5949	0	0
T3	13615	13461	0	0
T9	31608	31543	0	0
T10	20805	20707	0	0
T11	13701	13602	0	0
T12	8124	8040	0	0
T15	10645	10552	0	0
T16	10272	10191	0	0
T25	119482	119431	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T16 T38 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T16 T38 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T16 T38 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T12 T16 
159        1/1                    state_d = TimeoutSt;
           Tests:       T10 T12 T16 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T10 T12 T16 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T10 T12 T16 
172        1/1                    state_d    = Phase0St;
           Tests:       T57 T75 T87 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T57 T75 T87 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T57 T75 T87 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T57 T75 T87 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T10 T12 T16 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T12 T16 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T10 T12 T16 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T12 T16 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T16 T38 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T2 T16 T38 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T2 T16 T38 
190        1/1                  esc_state_o = Phase0;
           Tests:       T2 T16 T38 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T2 T16 T38 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T2 T16 T38 
194        1/1                    state_d = IdleSt;
           Tests:       T65 T124 T71 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T65 T124 T71 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T65 T124 T71 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T16 T38 
198        1/1                    state_d = Phase1St;
           Tests:       T2 T16 T38 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T16 T38 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T16 T38 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T16 T38 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T2 T16 T38 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T2 T16 T38 
207        1/1                  esc_state_o = Phase1;
           Tests:       T2 T16 T38 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T2 T16 T38 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T2 T16 T38 
211        1/1                    state_d = IdleSt;
           Tests:       T124 T122 T95 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T124 T122 T95 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T124 T122 T95 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T16 T38 
215        1/1                    state_d = Phase2St;
           Tests:       T2 T16 T38 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T16 T38 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T16 T38 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T16 T38 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T2 T16 T38 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T2 T16 T38 
224        1/1                  esc_state_o = Phase2;
           Tests:       T2 T16 T38 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T2 T16 T38 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T2 T16 T38 
229        1/1                    state_d = IdleSt;
           Tests:       T124 T125 T126 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T124 T125 T126 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T124 T125 T126 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T16 T38 
233        1/1                    state_d = Phase3St;
           Tests:       T2 T16 T38 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T16 T38 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T16 T38 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T2 T16 T38 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T2 T16 T38 
241        1/1                  esc_state_o = Phase3;
           Tests:       T2 T16 T38 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T2 T16 T38 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T2 T16 T38 
245        1/1                    state_d = IdleSt;
           Tests:       T124 T127 T128 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T124 T127 T128 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T124 T127 T128 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T16 T38 
249        1/1                    state_d = TerminalSt;
           Tests:       T2 T16 T38 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T16 T38 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T16 T38 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T2 T16 T38 
259        1/1                  esc_state_o = Terminal;
           Tests:       T2 T16 T38 
260        1/1                  if (clr_i) begin
           Tests:       T2 T16 T38 
261        1/1                    state_d = IdleSt;
           Tests:       T16 T40 T57 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T2,T10,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T16,T38

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T10,T11
1	0	1	Covered	T2,T9,T129
1	1	0	Covered	T10,T11,T52
1	1	1	Covered	T10,T12,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T16
0	1	Covered	T57,T75,T87
1	0	Covered	T57,T36,T41

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T10,T12,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T57,T36,T41

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T16
1	0	Not Covered
1	1	Covered	T57,T75,T87

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T14,T54,T81
1	Covered	T2,T16,T38

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T16,T38
1	Covered	T81,T33,T75

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T16,T38
1	Covered	T14,T54,T40

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T16,T38
1	Covered	T49,T58,T18

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T2,T40,T57

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T2,T38,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T2,T16,T38

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T2,T16,T14

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T16,T38
Phase1St	198	Covered	T2,T16,T38
Phase2St	215	Covered	T2,T16,T38
Phase3St	233	Covered	T2,T16,T38
TerminalSt	249	Covered	T2,T16,T38
TimeoutSt	159	Covered	T10,T12,T16

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T6,T7,T8
IdleSt->Phase0St	152	Covered	T2,T16,T38
IdleSt->TimeoutSt	159	Covered	T10,T12,T16
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T37,T41,T65
Phase0St->Phase1St	198	Covered	T2,T16,T38
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T59,T124,T122
Phase1St->Phase2St	215	Covered	T2,T16,T38
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T124,T109,T125
Phase2St->Phase3St	233	Covered	T2,T16,T38
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T124,T127,T128
Phase3St->TerminalSt	249	Covered	T2,T16,T38
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T16,T40,T57
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T10,T12,T16
TimeoutSt->Phase0St	172	Covered	T57,T75,T87

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T16,T38
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T57,T75,T87
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T16
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T65,T124,T71
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T16,T38
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T16,T38,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T124,T122,T95
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T16,T38
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T16,T38,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T124,T125,T126
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T16,T38
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T16,T38,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T124,T127,T128
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T16,T38
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T16,T38,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T16,T40,T57
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T16,T38
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	522575150	284	0	0
CheckAccumTrig0_A	522575150	458	0	0
CheckAccumTrig1_A	522575150	26	0	0
CheckClr_A	522575150	211	0	0
CheckEn_A	522259646	239973324	0	0
CheckPhase0_A	522575150	512	0	0
CheckPhase1_A	522575150	500	0	0
CheckPhase2_A	522575150	487	0	0
CheckPhase3_A	522575150	479	0	0
CheckTimeout0_A	522575150	1082	0	0
CheckTimeoutSt1_A	522575150	112582	0	0
CheckTimeoutSt2_A	522575150	1005	0	0
CheckTimeoutStTrig_A	522575150	45	0	0
ErrorStAllEscAsserted_A	522575150	1472	0	0
ErrorStIsTerminal_A	522575150	1202	0	0
EscStateOut_A	522257289	522188435	0	0
u_state_regs_A	522575150	522391987	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	284	0	0
T6	35061	67	0	0
T7	115272	59	0	0
T8	42086	78	0	0
T42	59314	21	0	0
T43	0	59	0	0
T44	47538	0	0	0
T45	56231	0	0	0
T46	78380	0	0	0
T47	903	0	0	0
T48	83121	0	0	0
T49	59578	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	458	0	0
T2	6004	1	0	0
T3	13615	0	0	0
T9	31608	0	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T14	0	1	0	0
T15	10645	0	0	0
T16	10272	2	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T49	0	1	0	0
T54	0	1	0	0
T58	0	1	0	0
T81	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	26	0	0
T24	21101	0	0	0
T33	49817	0	0	0
T36	0	2	0	0
T57	13248	1	0	0
T58	25946	0	0	0
T65	0	1	0	0
T70	0	1	0	0
T74	1061	0	0	0
T75	43467	0	0	0
T76	2523	0	0	0
T87	22379	0	0	0
T104	6335	0	0	0
T109	0	1	0	0
T125	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	200924	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	211	0	0
T4	31907	0	0	0
T13	4991	0	0	0
T14	46185	0	0	0
T16	10272	1	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T36	0	1	0	0
T38	42952	0	0	0
T40	0	1	0	0
T50	4234	0	0	0
T51	4578	0	0	0
T52	6540	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T75	0	1	0	0
T78	0	2	0	0
T87	0	5	0	0
T104	0	1	0	0
T135	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522259646	239973324	0	0
T1	1308	616	0	0
T2	6004	3995	0	0
T3	13615	3166	0	0
T9	31608	22614	0	0
T10	20805	14524	0	0
T11	13701	8138	0	0
T12	8124	2263	0	0
T15	10645	10551	0	0
T16	10272	594	0	0
T25	119482	119430	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	512	0	0
T2	6004	1	0	0
T3	13615	0	0	0
T9	31608	0	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T14	0	1	0	0
T15	10645	0	0	0
T16	10272	2	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T49	0	1	0	0
T54	0	1	0	0
T57	0	2	0	0
T81	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	500	0	0
T2	6004	1	0	0
T3	13615	0	0	0
T9	31608	0	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T14	0	1	0	0
T15	10645	0	0	0
T16	10272	2	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T49	0	1	0	0
T54	0	1	0	0
T57	0	2	0	0
T81	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	487	0	0
T2	6004	1	0	0
T3	13615	0	0	0
T9	31608	0	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T14	0	1	0	0
T15	10645	0	0	0
T16	10272	2	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T49	0	1	0	0
T54	0	1	0	0
T57	0	2	0	0
T81	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	479	0	0
T2	6004	1	0	0
T3	13615	0	0	0
T9	31608	0	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T14	0	1	0	0
T15	10645	0	0	0
T16	10272	2	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T49	0	1	0	0
T54	0	1	0	0
T57	0	2	0	0
T81	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	1082	0	0
T10	20805	2	0	0
T11	13701	0	0	0
T12	8124	1	0	0
T16	10272	1	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T38	42952	1	0	0
T50	4234	0	0	0
T51	4578	0	0	0
T52	0	1	0	0
T57	0	3	0	0
T75	0	2	0	0
T83	0	3	0	0
T85	0	1	0	0
T86	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	112582	0	0
T10	20805	172	0	0
T11	13701	0	0	0
T12	8124	147	0	0
T16	10272	3	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T38	42952	317	0	0
T50	4234	0	0	0
T51	4578	0	0	0
T52	0	475	0	0
T57	0	248	0	0
T75	0	156	0	0
T83	0	129	0	0
T85	0	170	0	0
T86	0	164	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	1005	0	0
T10	20805	2	0	0
T11	13701	0	0	0
T12	8124	1	0	0
T16	10272	1	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T38	42952	1	0	0
T50	4234	0	0	0
T51	4578	0	0	0
T52	0	1	0	0
T57	0	1	0	0
T75	0	1	0	0
T83	0	3	0	0
T85	0	1	0	0
T86	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	45	0	0
T24	21101	0	0	0
T33	49817	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T41	0	1	0	0
T57	13248	1	0	0
T58	25946	0	0	0
T74	1061	0	0	0
T75	43467	1	0	0
T76	2523	0	0	0
T87	22379	6	0	0
T90	0	3	0	0
T93	0	1	0	0
T104	6335	0	0	0
T134	200924	0	0	0
T136	0	1	0	0
T137	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	1472	0	0
T6	35061	347	0	0
T7	115272	285	0	0
T8	42086	329	0	0
T42	59314	183	0	0
T43	0	328	0	0
T44	47538	0	0	0
T45	56231	0	0	0
T46	78380	0	0	0
T47	903	0	0	0
T48	83121	0	0	0
T49	59578	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	1202	0	0
T6	35061	287	0	0
T7	115272	225	0	0
T8	42086	269	0	0
T42	59314	153	0	0
T43	0	268	0	0
T44	47538	0	0	0
T45	56231	0	0	0
T46	78380	0	0	0
T47	903	0	0	0
T48	83121	0	0	0
T49	59578	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522257289	522188435	0	0
T1	1308	1256	0	0
T2	6004	5949	0	0
T3	13615	13461	0	0
T9	31608	31543	0	0
T10	20805	20707	0	0
T11	13701	13602	0	0
T12	8124	8040	0	0
T15	10645	10552	0	0
T16	10272	10191	0	0
T25	119482	119431	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	522391987	0	0
T1	1308	1256	0	0
T2	6004	5949	0	0
T3	13615	13461	0	0
T9	31608	31543	0	0
T10	20805	20707	0	0
T11	13701	13602	0	0
T12	8124	8040	0	0
T15	10645	10552	0	0
T16	10272	10191	0	0
T25	119482	119431	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T9 T25 T16 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T9 T25 T16 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T9 T25 T16 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T15 T10 
159        1/1                    state_d = TimeoutSt;
           Tests:       T1 T15 T10 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T1 T15 T10 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T1 T15 T10 
172        1/1                    state_d    = Phase0St;
           Tests:       T15 T38 T84 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T15 T38 T84 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T15 T38 T84 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T15 T38 T84 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T1 T15 T10 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T15 T10 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T1 T10 T12 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T10 T12 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T9 T15 T25 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T9 T15 T25 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T9 T15 T25 
190        1/1                  esc_state_o = Phase0;
           Tests:       T9 T15 T25 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T9 T15 T25 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T9 T15 T25 
194        1/1                    state_d = IdleSt;
           Tests:       T26 T29 T30 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T26 T29 T30 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T26 T29 T30 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T9 T15 T25 
198        1/1                    state_d = Phase1St;
           Tests:       T9 T15 T25 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T9 T15 T25 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T9 T15 T25 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T9 T15 T25 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T9 T15 T25 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T9 T15 T25 
207        1/1                  esc_state_o = Phase1;
           Tests:       T9 T15 T25 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T9 T15 T25 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T9 T15 T25 
211        1/1                    state_d = IdleSt;
           Tests:       T29 T30 T68 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T30 T68 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T29 T30 T68 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T9 T15 T25 
215        1/1                    state_d = Phase2St;
           Tests:       T9 T15 T25 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T9 T15 T25 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T9 T15 T25 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T9 T15 T25 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T9 T15 T25 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T9 T15 T25 
224        1/1                  esc_state_o = Phase2;
           Tests:       T9 T15 T25 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T9 T15 T25 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T9 T15 T25 
229        1/1                    state_d = IdleSt;
           Tests:       T32 T34 T138 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T34 T138 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T32 T34 T138 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T9 T15 T25 
233        1/1                    state_d = Phase3St;
           Tests:       T9 T15 T25 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T9 T15 T25 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T9 T15 T25 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T9 T15 T25 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T9 T15 T25 
241        1/1                  esc_state_o = Phase3;
           Tests:       T9 T15 T25 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T9 T15 T25 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T9 T15 T25 
245        1/1                    state_d = IdleSt;
           Tests:       T35 T37 T139 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T37 T139 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T37 T139 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T9 T15 T25 
249        1/1                    state_d = TerminalSt;
           Tests:       T9 T15 T25 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T9 T15 T25 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T9 T15 T25 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T9 T15 T25 
259        1/1                  esc_state_o = Terminal;
           Tests:       T9 T15 T25 
260        1/1                  if (clr_i) begin
           Tests:       T9 T15 T25 
261        1/1                    state_d = IdleSt;
           Tests:       T9 T26 T38 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T9,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T39
1	1	1	Covered	T9,T25,T16

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T15,T10
1	0	1	Covered	T9,T27,T54
1	1	0	Covered	T10,T52,T14
1	1	1	Covered	T1,T15,T10

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T10
0	1	Covered	T15,T38,T84
1	0	Covered	T32,T59,T60

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T15,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T32,T59,T60

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T10
1	0	Not Covered
1	1	Covered	T15,T38,T84

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T9,T15,T25
1	Covered	T26,T27,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T26,T27
1	Covered	T9,T25,T16

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T9,T15,T25
1	Covered	T26,T38,T53

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T9,T25,T16
1	Covered	T15,T26,T38

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T9,T25,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T9,T25,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T15,T25,T26

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T15,T25,T16

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T9,T15,T25
Phase1St	198	Covered	T9,T15,T25
Phase2St	215	Covered	T9,T15,T25
Phase3St	233	Covered	T9,T15,T25
TerminalSt	249	Covered	T9,T15,T25
TimeoutSt	159	Covered	T1,T15,T10

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T6,T7,T8
IdleSt->Phase0St	152	Covered	T9,T25,T16
IdleSt->TimeoutSt	159	Covered	T1,T15,T10
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T26,T36,T61
Phase0St->Phase1St	198	Covered	T9,T15,T25
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T29,T41,T30
Phase1St->Phase2St	215	Covered	T9,T15,T25
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T32,T36,T34
Phase2St->Phase3St	233	Covered	T9,T15,T25
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T35,T37,T139
Phase3St->TerminalSt	249	Covered	T9,T15,T25
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T9,T26,T38
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T10,T12
TimeoutSt->Phase0St	172	Covered	T15,T38,T84

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T25,T16
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T15,T10
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T38,T84
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T15,T10
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T12
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T29,T30
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T9,T15,T25
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T9,T15,T25
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T30,T68
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T9,T15,T25
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T9,T15,T25
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T34,T138
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T9,T15,T25
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T9,T15,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T35,T37,T139
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T9,T15,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T9,T15,T25
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T26,T38
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T9,T15,T25
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	522575150	311	0	0
CheckAccumTrig0_A	522575150	798	0	0
CheckAccumTrig1_A	522575150	39	0	0
CheckClr_A	522575150	383	0	0
CheckEn_A	522259646	220880420	0	0
CheckPhase0_A	522575150	876	0	0
CheckPhase1_A	522575150	841	0	0
CheckPhase2_A	522575150	817	0	0
CheckPhase3_A	522575150	801	0	0
CheckTimeout0_A	522575150	1590	0	0
CheckTimeoutSt1_A	522575150	145565	0	0
CheckTimeoutSt2_A	522575150	1482	0	0
CheckTimeoutStTrig_A	522575150	65	0	0
ErrorStAllEscAsserted_A	522575150	1427	0	0
ErrorStIsTerminal_A	522575150	1157	0	0
EscStateOut_A	522257289	522188435	0	0
u_state_regs_A	522575150	522391987	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	311	0	0
T6	35061	58	0	0
T7	115272	75	0	0
T8	42086	68	0	0
T42	59314	40	0	0
T43	0	70	0	0
T44	47538	0	0	0
T45	56231	0	0	0
T46	78380	0	0	0
T47	903	0	0	0
T48	83121	0	0	0
T49	59578	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	798	0	0
T9	31608	1	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T14	0	1	0	0
T15	10645	0	0	0
T16	10272	1	0	0
T25	119482	1	0	0
T26	26808	5	0	0
T27	1247	1	0	0
T38	0	2	0	0
T50	4234	0	0	0
T53	0	2	0	0
T54	0	1	0	0
T56	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	39	0	0
T24	21101	0	0	0
T29	0	1	0	0
T32	38827	4	0	0
T33	49817	0	0	0
T35	108876	0	0	0
T36	0	1	0	0
T57	13248	0	0	0
T58	25946	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T68	0	1	0	0
T70	0	1	0	0
T73	11610	0	0	0
T74	1061	0	0	0
T75	43467	0	0	0
T76	2523	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	383	0	0
T9	31608	1	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T15	10645	0	0	0
T16	10272	0	0	0
T25	119482	0	0	0
T26	26808	4	0	0
T27	1247	0	0	0
T32	0	4	0	0
T33	0	1	0	0
T35	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T50	4234	0	0	0
T53	0	1	0	0
T76	0	1	0	0
T77	0	5	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522259646	220880420	0	0
T1	1308	604	0	0
T2	6004	3939	0	0
T3	13615	3098	0	0
T9	31608	12657	0	0
T10	20805	19555	0	0
T11	13701	8123	0	0
T12	8124	2216	0	0
T15	10645	1905	0	0
T16	10272	582	0	0
T25	119482	9651	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	876	0	0
T9	31608	1	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T14	0	1	0	0
T15	10645	1	0	0
T16	10272	1	0	0
T25	119482	1	0	0
T26	26808	4	0	0
T27	1247	1	0	0
T38	0	3	0	0
T50	4234	0	0	0
T53	0	2	0	0
T54	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	841	0	0
T9	31608	1	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T14	0	1	0	0
T15	10645	1	0	0
T16	10272	1	0	0
T25	119482	1	0	0
T26	26808	4	0	0
T27	1247	1	0	0
T38	0	3	0	0
T50	4234	0	0	0
T53	0	2	0	0
T54	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	817	0	0
T9	31608	1	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T14	0	1	0	0
T15	10645	1	0	0
T16	10272	1	0	0
T25	119482	1	0	0
T26	26808	4	0	0
T27	1247	1	0	0
T38	0	3	0	0
T50	4234	0	0	0
T53	0	2	0	0
T54	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	801	0	0
T9	31608	1	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T14	0	1	0	0
T15	10645	1	0	0
T16	10272	1	0	0
T25	119482	1	0	0
T26	26808	4	0	0
T27	1247	1	0	0
T38	0	3	0	0
T50	4234	0	0	0
T53	0	2	0	0
T54	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	1590	0	0
T1	1308	1	0	0
T2	6004	0	0	0
T3	13615	0	0	0
T9	31608	0	0	0
T10	20805	1	0	0
T11	13701	0	0	0
T12	8124	1	0	0
T14	0	3	0	0
T15	10645	1	0	0
T16	10272	0	0	0
T25	119482	0	0	0
T38	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T84	0	1	0	0
T86	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	145565	0	0
T1	1308	45	0	0
T2	6004	0	0	0
T3	13615	0	0	0
T9	31608	0	0	0
T10	20805	144	0	0
T11	13701	0	0	0
T12	8124	185	0	0
T14	0	158	0	0
T15	10645	198	0	0
T16	10272	0	0	0
T25	119482	0	0	0
T38	0	186	0	0
T82	0	69	0	0
T83	0	84	0	0
T84	0	19	0	0
T86	0	158	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	1482	0	0
T1	1308	1	0	0
T2	6004	0	0	0
T3	13615	0	0	0
T9	31608	0	0	0
T10	20805	1	0	0
T11	13701	0	0	0
T12	8124	1	0	0
T14	0	3	0	0
T15	10645	0	0	0
T16	10272	0	0	0
T25	119482	0	0	0
T59	0	2	0	0
T82	0	1	0	0
T83	0	2	0	0
T86	0	1	0	0
T87	0	6	0	0
T88	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	65	0	0
T10	20805	0	0	0
T11	13701	0	0	0
T12	8124	0	0	0
T15	10645	1	0	0
T16	10272	0	0	0
T25	119482	0	0	0
T26	26808	0	0	0
T27	1247	0	0	0
T38	42952	1	0	0
T50	4234	0	0	0
T57	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T66	0	1	0	0
T78	0	1	0	0
T84	0	1	0	0
T90	0	1	0	0
T92	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	1427	0	0
T6	35061	287	0	0
T7	115272	319	0	0
T8	42086	332	0	0
T42	59314	186	0	0
T43	0	303	0	0
T44	47538	0	0	0
T45	56231	0	0	0
T46	78380	0	0	0
T47	903	0	0	0
T48	83121	0	0	0
T49	59578	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	1157	0	0
T6	35061	227	0	0
T7	115272	259	0	0
T8	42086	272	0	0
T42	59314	156	0	0
T43	0	243	0	0
T44	47538	0	0	0
T45	56231	0	0	0
T46	78380	0	0	0
T47	903	0	0	0
T48	83121	0	0	0
T49	59578	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522257289	522188435	0	0
T1	1308	1256	0	0
T2	6004	5949	0	0
T3	13615	13461	0	0
T9	31608	31543	0	0
T10	20805	20707	0	0
T11	13701	13602	0	0
T12	8124	8040	0	0
T15	10645	10552	0	0
T16	10272	10191	0	0
T25	119482	119431	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522575150	522391987	0	0
T1	1308	1256	0	0
T2	6004	5949	0	0
T3	13615	13461	0	0
T9	31608	31543	0	0
T10	20805	20707	0	0
T11	13701	13602	0	0
T12	8124	8040	0	0
T15	10645	10552	0	0
T16	10272	10191	0	0
T25	119482	119431	0	0