Module Definition
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Module Instance : tb.dut.u_ping_timer.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.46 100.00 97.30 100.00 100.00 100.00 u_ping_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_classes[0].u_esc_timer.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.67 100.00 93.33 100.00 100.00 100.00 gen_classes[0].u_esc_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_classes[1].u_esc_timer.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.67 100.00 93.33 100.00 100.00 100.00 gen_classes[1].u_esc_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_classes[2].u_esc_timer.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.11 100.00 95.56 100.00 100.00 100.00 gen_classes[2].u_esc_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_classes[3].u_esc_timer.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.67 100.00 93.33 100.00 100.00 100.00 gen_classes[3].u_esc_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00

Line Coverage for Module : prim_sparse_fsm_flop
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Module : prim_sparse_fsm_flop
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 3100 3100 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3100 3100 0 0
T1 5 5 0 0
T2 5 5 0 0
T3 5 5 0 0
T4 5 5 0 0
T5 5 5 0 0
T9 5 5 0 0
T11 5 5 0 0
T12 5 5 0 0
T21 5 5 0 0
T22 5 5 0 0

Line Coverage for Instance : tb.dut.u_ping_timer.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_ping_timer.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 620 620 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 620 620 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 620 620 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 620 620 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 620 620 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 620 620 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 620 620 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 620 620 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 620 620 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 620 620 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0

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