Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T1 T2 T4 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T2 T4 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T2 T4 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T9 T12 
159        1/1                    state_d = TimeoutSt;
           Tests:       T3 T9 T12 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T3 T9 T12 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T3 T9 T12 
172        1/1                    state_d    = Phase0St;
           Tests:       T3 T13 T27 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T3 T13 T27 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T3 T13 T27 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T3 T13 T27 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T3 T9 T12 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T9 T12 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T3 T9 T12 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T9 T12 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T2 T3 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T2 T3 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T2 T3 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T2 T3 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
194        1/1                    state_d = IdleSt;
           Tests:       T28 T29 T30 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T29 T30 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T28 T29 T30 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T2 T3 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T3 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T2 T3 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T2 T3 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T2 T3 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
211        1/1                    state_d = IdleSt;
           Tests:       T12 T31 T32 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T31 T32 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T12 T31 T32 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T2 T3 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T3 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T2 T3 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T2 T3 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T2 T3 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T2 T3 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
229        1/1                    state_d = IdleSt;
           Tests:       T33 T34 T35 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T34 T35 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T33 T34 T35 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T2 T3 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T2 T3 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T2 T3 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T2 T3 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T2 T3 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
245        1/1                    state_d = IdleSt;
           Tests:       T36 T37 T38 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T36 T37 T38 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T36 T37 T38 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T2 T3 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T2 T3 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T2 T3 
260        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
261        1/1                    state_d = IdleSt;
           Tests:       T3 T12 T13 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T6 T10 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T6 T10 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T6 T10 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T6 T10 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T11
1	0	1	Covered	T1,T21,T22
1	1	0	Covered	T3,T11,T9
1	1	1	Covered	T3,T9,T12

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T12
0	1	Covered	T3,T13,T36
1	0	Covered	T27,T39,T40

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T9,T12
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T27,T39,T40

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T12
1	0	Covered	T41
1	1	Covered	T3,T13,T36

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T21
1	Covered	T1,T2,T12

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T42,T43,T39

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T13,T24

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T3,T12,T13

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T5,T6,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T2,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T2,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T12,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T6,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T3,T9,T12

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T5,T6,T10
IdleSt->Phase0St	152	Covered	T1,T2,T12
IdleSt->TimeoutSt	159	Covered	T3,T9,T12
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T44,T28,T29
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T12,T31,T32
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T33,T45,T34
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T36,T37,T46
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T3,T12,T13
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T3,T9,T12
TimeoutSt->Phase0St	172	Covered	T3,T13,T27

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T12
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T27
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T12
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T12
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T29,T30
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T12,T31,T32
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T33,T34,T35
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T36,T37,T38
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T12,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T10

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T10
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	924	0	0
CheckAccumTrig0_A	2147483647	2080	0	0
CheckAccumTrig1_A	2147483647	108	0	0
CheckClr_A	2147483647	925	0	0
CheckEn_A	2147483647	879080778	0	0
CheckPhase0_A	2147483647	2334	0	0
CheckPhase1_A	2147483647	2272	0	0
CheckPhase2_A	2147483647	2236	0	0
CheckPhase3_A	2147483647	2191	0	0
CheckTimeout0_A	2147483647	4621	0	0
CheckTimeoutSt1_A	2147483647	508851	0	0
CheckTimeoutSt2_A	2147483647	4295	0	0
CheckTimeoutStTrig_A	2147483647	208	0	0
ErrorStAllEscAsserted_A	2147483647	5185	0	0
ErrorStIsTerminal_A	2147483647	4225	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	924	0	0
T5	177068	294	0	0
T6	179452	206	0	0
T10	0	101	0	0
T12	121292	0	0	0
T13	68900	0	0	0
T21	226408	0	0	0
T22	3912	0	0	0
T23	245716	0	0	0
T24	275660	0	0	0
T25	29492	0	0	0
T47	0	219	0	0
T48	0	104	0	0
T49	340212	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2080	0	0
T1	4132	1	0	0
T2	21892	1	0	0
T3	33210	0	0	0
T4	118128	0	0	0
T5	132801	0	0	0
T6	44863	0	0	0
T9	64515	0	0	0
T11	38883	0	0	0
T12	121292	6	0	0
T13	51675	7	0	0
T21	226408	1	0	0
T22	3912	1	0	0
T23	122858	2	0	0
T24	137830	2	0	0
T25	7373	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T36	0	1	0	0
T39	0	4	0	0
T42	17850	1	0	0
T43	0	2	0	0
T44	0	4	0	0
T49	85053	0	0	0
T50	0	5	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	4	0	0
T55	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	108	0	0
T8	73298	0	0	0
T10	19257	0	0	0
T27	79226	1	0	0
T35	491120	0	0	0
T36	12952	0	0	0
T39	174471	1	0	0
T40	0	1	0	0
T45	0	2	0	0
T51	3972	0	0	0
T52	198357	0	0	0
T56	177630	1	0	0
T57	34005	2	0	0
T58	35529	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	3	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	6466	0	0	0
T74	26266	0	0	0
T75	56437	0	0	0
T76	3449	0	0	0
T77	36775	0	0	0
T78	39948	0	0	0
T79	49971	0	0	0
T80	18321	0	0	0
T81	16317	0	0	0
T82	97119	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	925	0	0
T3	16605	1	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T6	134589	0	0	0
T7	103945	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	90969	3	0	0
T13	68900	7	0	0
T21	169806	0	0	0
T22	2934	0	0	0
T23	245716	0	0	0
T24	206745	1	0	0
T25	22119	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T29	0	1	0	0
T31	0	4	0	0
T34	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T39	0	1	0	0
T42	53550	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T49	255159	0	0	0
T50	7702	4	0	0
T54	0	7	0	0
T73	0	1	0	0
T83	0	3	0	0
T84	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	47018	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	879080778	0	0
T1	16528	11359	0	0
T2	43784	27454	0	0
T3	66420	38842	0	0
T4	157504	7376	0	0
T5	1336	1008	0	0
T9	86020	75945	0	0
T11	51844	32681	0	0
T12	121292	20684	0	0
T21	226408	177828	0	0
T22	3912	2416	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2334	0	0
T1	4132	1	0	0
T2	21892	1	0	0
T3	33210	1	0	0
T4	118128	0	0	0
T5	132801	0	0	0
T6	44863	0	0	0
T9	64515	0	0	0
T11	38883	0	0	0
T12	121292	6	0	0
T13	51675	9	0	0
T21	226408	1	0	0
T22	3912	1	0	0
T23	122858	2	0	0
T24	137830	2	0	0
T25	7373	0	0	0
T27	0	2	0	0
T28	0	3	0	0
T36	0	2	0	0
T39	0	5	0	0
T42	17850	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T49	85053	0	0	0
T50	0	5	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	4	0	0
T55	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2272	0	0
T1	4132	1	0	0
T2	21892	1	0	0
T3	33210	1	0	0
T4	118128	0	0	0
T5	132801	0	0	0
T6	44863	0	0	0
T9	64515	0	0	0
T11	38883	0	0	0
T12	121292	5	0	0
T13	51675	9	0	0
T21	226408	1	0	0
T22	3912	1	0	0
T23	122858	2	0	0
T24	137830	2	0	0
T25	7373	0	0	0
T27	0	2	0	0
T28	0	3	0	0
T36	0	2	0	0
T39	0	5	0	0
T42	17850	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T49	85053	0	0	0
T50	0	5	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	4	0	0
T55	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2236	0	0
T1	4132	1	0	0
T2	21892	1	0	0
T3	33210	1	0	0
T4	118128	0	0	0
T5	132801	0	0	0
T6	44863	0	0	0
T9	64515	0	0	0
T11	38883	0	0	0
T12	121292	5	0	0
T13	51675	9	0	0
T21	226408	1	0	0
T22	3912	1	0	0
T23	122858	2	0	0
T24	137830	2	0	0
T25	7373	0	0	0
T27	0	2	0	0
T28	0	3	0	0
T36	0	2	0	0
T39	0	5	0	0
T42	17850	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T49	85053	0	0	0
T50	0	5	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	4	0	0
T55	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2191	0	0
T1	4132	1	0	0
T2	21892	1	0	0
T3	33210	1	0	0
T4	118128	0	0	0
T5	132801	0	0	0
T6	44863	0	0	0
T9	64515	0	0	0
T11	38883	0	0	0
T12	121292	5	0	0
T13	51675	9	0	0
T21	226408	1	0	0
T22	3912	1	0	0
T23	122858	2	0	0
T24	137830	2	0	0
T25	7373	0	0	0
T27	0	2	0	0
T28	0	3	0	0
T39	0	5	0	0
T42	17850	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T49	85053	0	0	0
T50	0	5	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	4	0	0
T55	0	1	0	0
T88	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4621	0	0
T3	66420	5	0	0
T4	157504	0	0	0
T5	177068	0	0	0
T9	86020	1	0	0
T11	51844	0	0	0
T12	121292	1	0	0
T13	68900	8	0	0
T21	226408	1	0	0
T22	3912	0	0	0
T23	245716	0	0	0
T25	0	2	0	0
T27	0	1	0	0
T28	0	2	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	9	0	0
T44	0	19	0	0
T45	0	3	0	0
T49	0	17	0	0
T50	0	1	0	0
T54	0	3	0	0
T75	0	10	0	0
T89	0	20	0	0
T90	0	2	0	0
T91	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	508851	0	0
T3	66420	892	0	0
T4	157504	0	0	0
T5	177068	0	0	0
T9	86020	330	0	0
T11	51844	0	0	0
T12	121292	15	0	0
T13	68900	1951	0	0
T21	226408	186	0	0
T22	3912	0	0	0
T23	245716	0	0	0
T25	0	290	0	0
T27	0	4	0	0
T28	0	188	0	0
T36	0	108	0	0
T39	0	2	0	0
T40	0	123	0	0
T41	0	591	0	0
T44	0	1148	0	0
T45	0	658	0	0
T49	0	3151	0	0
T50	0	15	0	0
T54	0	74	0	0
T75	0	1725	0	0
T89	0	2751	0	0
T90	0	368	0	0
T91	0	341	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4295	0	0
T3	49815	4	0	0
T4	118128	0	0	0
T5	132801	0	0	0
T6	44863	0	0	0
T7	103945	0	0	0
T9	64515	1	0	0
T11	38883	0	0	0
T12	90969	1	0	0
T13	68900	5	0	0
T21	169806	1	0	0
T22	2934	0	0	0
T23	245716	0	0	0
T24	68915	0	0	0
T25	7373	2	0	0
T28	0	1	0	0
T31	0	1	0	0
T40	0	2	0	0
T41	0	8	0	0
T42	17850	0	0	0
T44	0	19	0	0
T49	85053	17	0	0
T50	7702	1	0	0
T54	0	1	0	0
T56	0	2	0	0
T75	0	9	0	0
T87	47018	0	0	0
T89	0	22	0	0
T90	0	2	0	0
T92	0	4	0	0
T93	0	7	0	0
T94	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	208	0	0
T3	16605	1	0	0
T6	44863	0	0	0
T7	103945	0	0	0
T13	34450	2	0	0
T18	20441	0	0	0
T23	122858	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T29	0	1	0	0
T31	33955	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	2	0	0
T41	32170	1	0	0
T42	17850	0	0	0
T48	23232	0	0	0
T49	85053	0	0	0
T50	7702	0	0	0
T54	16394	2	0	0
T55	1601	0	0	0
T63	0	1	0	0
T77	0	1	0	0
T83	41108	0	0	0
T87	47018	0	0	0
T88	189600	0	0	0
T90	0	1	0	0
T94	0	2	0	0
T95	0	3	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	2	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	5	0	0
T103	0	1	0	0
T104	19343	0	0	0
T105	89174	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5185	0	0
T5	177068	1283	0	0
T6	179452	1327	0	0
T10	0	626	0	0
T12	121292	0	0	0
T13	68900	0	0	0
T21	226408	0	0	0
T22	3912	0	0	0
T23	245716	0	0	0
T24	275660	0	0	0
T25	29492	0	0	0
T47	0	1288	0	0
T48	0	661	0	0
T49	340212	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4225	0	0
T5	177068	1043	0	0
T6	179452	1087	0	0
T10	0	506	0	0
T12	121292	0	0	0
T13	68900	0	0	0
T21	226408	0	0	0
T22	3912	0	0	0
T23	245716	0	0	0
T24	275660	0	0	0
T25	29492	0	0	0
T47	0	1048	0	0
T48	0	541	0	0
T49	340212	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	16528	16136	0	0
T2	43784	43436	0	0
T3	66420	66068	0	0
T4	157504	156872	0	0
T5	380	56	0	0
T9	86020	85732	0	0
T11	51844	51504	0	0
T12	121292	120964	0	0
T21	226408	226012	0	0
T22	3912	3688	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	16528	16136	0	0
T2	43784	43436	0	0
T3	66420	66068	0	0
T4	157504	156872	0	0
T5	177068	75076	0	0
T9	86020	85732	0	0
T11	51844	51504	0	0
T12	121292	120964	0	0
T21	226408	226012	0	0
T22	3912	3688	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T12 T21 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T12 T21 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T12 T21 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T9 T21 
159        1/1                    state_d = TimeoutSt;
           Tests:       T3 T9 T21 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T3 T9 T21 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T3 T9 T21 
172        1/1                    state_d    = Phase0St;
           Tests:       T27 T39 T54 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T27 T39 T54 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T27 T39 T54 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T27 T39 T54 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T3 T9 T21 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T9 T21 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T3 T9 T21 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T9 T21 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T12 T21 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T2 T12 T21 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T2 T12 T21 
190        1/1                  esc_state_o = Phase0;
           Tests:       T2 T12 T21 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T2 T12 T21 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T2 T12 T21 
194        1/1                    state_d = IdleSt;
           Tests:       T28 T30 T106 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T30 T106 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T28 T30 T106 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T12 T21 
198        1/1                    state_d = Phase1St;
           Tests:       T2 T12 T21 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T12 T21 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T12 T21 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T12 T21 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T2 T12 T21 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T2 T12 T21 
207        1/1                  esc_state_o = Phase1;
           Tests:       T2 T12 T21 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T2 T12 T21 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T2 T12 T21 
211        1/1                    state_d = IdleSt;
           Tests:       T12 T31 T32 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T31 T32 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T12 T31 T32 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T12 T21 
215        1/1                    state_d = Phase2St;
           Tests:       T2 T12 T21 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T12 T21 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T12 T21 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T12 T21 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T2 T12 T21 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T2 T12 T21 
224        1/1                  esc_state_o = Phase2;
           Tests:       T2 T12 T21 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T2 T12 T21 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T2 T12 T21 
229        1/1                    state_d = IdleSt;
           Tests:       T33 T34 T35 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T34 T35 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T33 T34 T35 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T12 T21 
233        1/1                    state_d = Phase3St;
           Tests:       T2 T12 T21 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T12 T21 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T12 T21 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T2 T12 T21 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T2 T12 T21 
241        1/1                  esc_state_o = Phase3;
           Tests:       T2 T12 T21 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T2 T12 T21 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T2 T12 T21 
245        1/1                    state_d = IdleSt;
           Tests:       T107 T108 T109 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T107 T108 T109 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T107 T108 T109 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T12 T21 
249        1/1                    state_d = TerminalSt;
           Tests:       T2 T12 T21 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T12 T21 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T12 T21 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T2 T12 T21 
259        1/1                  esc_state_o = Terminal;
           Tests:       T2 T12 T21 
260        1/1                  if (clr_i) begin
           Tests:       T2 T12 T21 
261        1/1                    state_d = IdleSt;
           Tests:       T12 T24 T50 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T6 T10 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T6 T10 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T6 T10 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T6 T10 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T9

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T12,T21

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T9
1	0	1	Covered	T21,T22,T39
1	1	0	Covered	T11,T9,T21
1	1	1	Covered	T3,T9,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T21
0	1	Covered	T54,T41,T94
1	0	Covered	T27,T39,T40

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T9,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T27,T39,T40

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T21
1	0	Not Covered
1	1	Covered	T54,T41,T94

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T21,T24,T42
1	Covered	T2,T12,T22

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T12,T21
1	Covered	T42,T39,T28

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T12,T22
1	Covered	T21,T24,T39

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T12,T21
1	Covered	T27,T73,T74

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T5,T6,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T2,T12,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T2,T22,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T21,T22,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T2,T22,T23

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T6,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T12,T21
Phase1St	198	Covered	T2,T12,T21
Phase2St	215	Covered	T2,T12,T21
Phase3St	233	Covered	T2,T12,T21
TerminalSt	249	Covered	T2,T12,T21
TimeoutSt	159	Covered	T3,T9,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T6,T10
IdleSt->Phase0St	152	Covered	T2,T12,T21
IdleSt->TimeoutSt	159	Covered	T3,T9,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T28,T30,T45
Phase0St->Phase1St	198	Covered	T2,T12,T21
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T12,T31,T32
Phase1St->Phase2St	215	Covered	T2,T12,T21
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T33,T34,T35
Phase2St->Phase3St	233	Covered	T2,T12,T21
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T46,T107,T108
Phase3St->TerminalSt	249	Covered	T2,T12,T21
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T12,T24,T50
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T9,T21
TimeoutSt->Phase0St	172	Covered	T27,T39,T54

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T21
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T27,T39,T54
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T30,T106
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T12,T21
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T12,T21
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T12,T31,T32
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T12,T21
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T12,T21
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T33,T34,T35
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T12,T21
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T12,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T107,T108,T109
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T12,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T12,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T24,T50
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T12,T21
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T10

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T10
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	551568653	204	0	0
CheckAccumTrig0_A	551568653	730	0	0
CheckAccumTrig1_A	551568653	44	0	0
CheckClr_A	551568653	330	0	0
CheckEn_A	551396352	202422358	0	0
CheckPhase0_A	551568653	814	0	0
CheckPhase1_A	551568653	789	0	0
CheckPhase2_A	551568653	776	0	0
CheckPhase3_A	551568653	760	0	0
CheckTimeout0_A	551568653	1398	0	0
CheckTimeoutSt1_A	551568653	165729	0	0
CheckTimeoutSt2_A	551568653	1295	0	0
CheckTimeoutStTrig_A	551568653	56	0	0
ErrorStAllEscAsserted_A	551568653	1339	0	0
ErrorStIsTerminal_A	551568653	1099	0	0
EscStateOut_A	551394821	551327306	0	0
u_state_regs_A	551568653	551399471	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	204	0	0
T5	44267	66	0	0
T6	44863	44	0	0
T10	0	25	0	0
T12	30323	0	0	0
T13	17225	0	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T47	0	51	0	0
T48	0	18	0	0
T49	85053	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	730	0	0
T2	10946	1	0	0
T3	16605	0	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	3	0	0
T13	17225	0	0	0
T21	56602	1	0	0
T22	978	1	0	0
T23	0	1	0	0
T24	0	2	0	0
T27	0	1	0	0
T39	0	3	0	0
T42	0	1	0	0
T50	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	44	0	0
T8	73298	0	0	0
T10	19257	0	0	0
T27	79226	1	0	0
T36	12952	0	0	0
T39	174471	1	0	0
T40	0	1	0	0
T45	0	2	0	0
T51	3972	0	0	0
T52	198357	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T73	6466	0	0	0
T74	26266	0	0	0
T75	56437	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	330	0	0
T6	44863	0	0	0
T12	30323	2	0	0
T13	17225	0	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	1	0	0
T25	7373	0	0	0
T27	0	1	0	0
T28	0	2	0	0
T31	0	4	0	0
T39	0	1	0	0
T42	17850	0	0	0
T49	85053	0	0	0
T50	0	1	0	0
T54	0	3	0	0
T73	0	1	0	0
T83	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551396352	202422358	0	0
T1	4132	2807	0	0
T2	10946	2057	0	0
T3	16605	6267	0	0
T4	39376	1838	0	0
T5	334	252	0	0
T9	21505	16079	0	0
T11	12961	12875	0	0
T12	30323	597	0	0
T21	56602	8322	0	0
T22	978	598	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	814	0	0
T2	10946	1	0	0
T3	16605	0	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	3	0	0
T13	17225	0	0	0
T21	56602	1	0	0
T22	978	1	0	0
T23	0	1	0	0
T24	0	2	0	0
T27	0	2	0	0
T39	0	4	0	0
T42	0	1	0	0
T50	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	789	0	0
T2	10946	1	0	0
T3	16605	0	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	2	0	0
T13	17225	0	0	0
T21	56602	1	0	0
T22	978	1	0	0
T23	0	1	0	0
T24	0	2	0	0
T27	0	2	0	0
T39	0	4	0	0
T42	0	1	0	0
T50	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	776	0	0
T2	10946	1	0	0
T3	16605	0	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	2	0	0
T13	17225	0	0	0
T21	56602	1	0	0
T22	978	1	0	0
T23	0	1	0	0
T24	0	2	0	0
T27	0	2	0	0
T39	0	4	0	0
T42	0	1	0	0
T50	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	760	0	0
T2	10946	1	0	0
T3	16605	0	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	2	0	0
T13	17225	0	0	0
T21	56602	1	0	0
T22	978	1	0	0
T23	0	1	0	0
T24	0	2	0	0
T27	0	2	0	0
T39	0	4	0	0
T42	0	1	0	0
T50	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	1398	0	0
T3	16605	2	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	1	0	0
T11	12961	0	0	0
T12	30323	0	0	0
T13	17225	0	0	0
T21	56602	1	0	0
T22	978	0	0	0
T23	61429	0	0	0
T27	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T49	0	7	0	0
T50	0	1	0	0
T54	0	1	0	0
T75	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	165729	0	0
T3	16605	411	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	330	0	0
T11	12961	0	0	0
T12	30323	0	0	0
T13	17225	0	0	0
T21	56602	186	0	0
T22	978	0	0	0
T23	61429	0	0	0
T27	0	4	0	0
T39	0	2	0	0
T41	0	60	0	0
T49	0	1391	0	0
T50	0	15	0	0
T54	0	40	0	0
T75	0	684	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	1295	0	0
T3	16605	2	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	1	0	0
T11	12961	0	0	0
T12	30323	0	0	0
T13	17225	0	0	0
T21	56602	1	0	0
T22	978	0	0	0
T23	61429	0	0	0
T31	0	1	0	0
T40	0	1	0	0
T49	0	7	0	0
T50	0	1	0	0
T75	0	4	0	0
T89	0	2	0	0
T92	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	56	0	0
T18	20441	0	0	0
T31	33955	0	0	0
T38	0	1	0	0
T41	32170	1	0	0
T48	23232	0	0	0
T54	16394	1	0	0
T55	1601	0	0	0
T63	0	1	0	0
T77	0	1	0	0
T83	41108	0	0	0
T88	189600	0	0	0
T94	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	2	0	0
T103	0	1	0	0
T104	19343	0	0	0
T105	89174	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	1339	0	0
T5	44267	351	0	0
T6	44863	319	0	0
T10	0	164	0	0
T12	30323	0	0	0
T13	17225	0	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T47	0	329	0	0
T48	0	176	0	0
T49	85053	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	1099	0	0
T5	44267	291	0	0
T6	44863	259	0	0
T10	0	134	0	0
T12	30323	0	0	0
T13	17225	0	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T47	0	269	0	0
T48	0	146	0	0
T49	85053	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551394821	551327306	0	0
T1	4132	4034	0	0
T2	10946	10859	0	0
T3	16605	16517	0	0
T4	39376	39218	0	0
T5	95	14	0	0
T9	21505	21433	0	0
T11	12961	12876	0	0
T12	30323	30241	0	0
T21	56602	56503	0	0
T22	978	922	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	551399471	0	0
T1	4132	4034	0	0
T2	10946	10859	0	0
T3	16605	16517	0	0
T4	39376	39218	0	0
T5	44267	18769	0	0
T9	21505	21433	0	0
T11	12961	12876	0	0
T12	30323	30241	0	0
T21	56602	56503	0	0
T22	978	922	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T4 T12 T13 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T4 T12 T13 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T4 T12 T13 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T12 T13 
159        1/1                    state_d = TimeoutSt;
           Tests:       T3 T12 T13 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T3 T12 T13 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T3 T12 T13 
172        1/1                    state_d    = Phase0St;
           Tests:       T13 T29 T94 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T13 T29 T94 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T13 T29 T94 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T13 T29 T94 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T3 T12 T13 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T12 T13 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T3 T12 T25 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T12 T25 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T12 T13 T23 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T12 T13 T23 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T12 T13 T23 
190        1/1                  esc_state_o = Phase0;
           Tests:       T12 T13 T23 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T12 T13 T23 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T12 T13 T23 
194        1/1                    state_d = IdleSt;
           Tests:       T29 T35 T61 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T35 T61 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T29 T35 T61 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T12 T13 T23 
198        1/1                    state_d = Phase1St;
           Tests:       T12 T13 T23 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T13 T23 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T13 T23 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T12 T13 T23 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T12 T13 T23 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T12 T13 T23 
207        1/1                  esc_state_o = Phase1;
           Tests:       T12 T13 T23 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T12 T13 T23 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T12 T13 T23 
211        1/1                    state_d = IdleSt;
           Tests:       T110 T106 T111 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T110 T106 T111 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T110 T106 T111 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T12 T13 T23 
215        1/1                    state_d = Phase2St;
           Tests:       T12 T13 T23 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T13 T23 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T13 T23 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T12 T13 T23 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T12 T13 T23 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T12 T13 T23 
224        1/1                  esc_state_o = Phase2;
           Tests:       T12 T13 T23 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T12 T13 T23 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T12 T13 T23 
229        1/1                    state_d = IdleSt;
           Tests:       T112 T110 T102 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T112 T110 T102 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T112 T110 T102 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T12 T13 T23 
233        1/1                    state_d = Phase3St;
           Tests:       T12 T13 T23 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T13 T23 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T12 T13 T23 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T12 T13 T23 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T12 T13 T23 
241        1/1                  esc_state_o = Phase3;
           Tests:       T12 T13 T23 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T12 T13 T23 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T12 T13 T23 
245        1/1                    state_d = IdleSt;
           Tests:       T36 T37 T102 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T36 T37 T102 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T36 T37 T102 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T12 T13 T23 
249        1/1                    state_d = TerminalSt;
           Tests:       T12 T13 T23 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T13 T23 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T12 T13 T23 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T12 T13 T23 
259        1/1                  esc_state_o = Terminal;
           Tests:       T12 T13 T23 
260        1/1                  if (clr_i) begin
           Tests:       T12 T13 T23 
261        1/1                    state_d = IdleSt;
           Tests:       T12 T13 T50 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T6 T10 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T6 T10 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T6 T10 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T6 T10 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T3,T4,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T12,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T12,T13
1	0	1	Covered	T50,T39,T44
1	1	0	Covered	T3,T12,T43
1	1	1	Covered	T3,T12,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T13
0	1	Covered	T13,T29,T94
1	0	Covered	T57,T61,T62

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T12,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T57,T61,T62

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T13
1	0	Not Covered
1	1	Covered	T13,T29,T94

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T12,T13,T23
1	Covered	T12,T50,T36

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T12,T13,T23
1	Covered	T28,T40,T32

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12,T13,T23
1	Covered	T43,T54,T113

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12,T50,T43
1	Covered	T12,T13,T23

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T5,T6,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T12,T13,T43

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T23,T43,T28

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T12,T13,T50

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T12,T23,T43

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T6,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T12,T13,T23
Phase1St	198	Covered	T12,T13,T23
Phase2St	215	Covered	T12,T13,T23
Phase3St	233	Covered	T12,T13,T23
TerminalSt	249	Covered	T12,T13,T23
TimeoutSt	159	Covered	T3,T12,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T6,T10
IdleSt->Phase0St	152	Covered	T12,T13,T23
IdleSt->TimeoutSt	159	Covered	T3,T12,T13
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T44,T29,T35
Phase0St->Phase1St	198	Covered	T12,T13,T23
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T45,T97,T110
Phase1St->Phase2St	215	Covered	T12,T13,T23
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T45,T112,T110
Phase2St->Phase3St	233	Covered	T12,T13,T23
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T36,T37,T46
Phase3St->TerminalSt	249	Covered	T12,T13,T23
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T12,T13,T50
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T12,T25
TimeoutSt->Phase0St	172	Covered	T13,T29,T94

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T29,T94
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T25
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T35,T61
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T12,T13,T23
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T12,T13,T23
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T110,T106,T111
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T12,T13,T23
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T12,T13,T23
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T112,T110,T102
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T12,T13,T23
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T12,T13,T23
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T36,T37,T102
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T12,T13,T23
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T12,T13,T23
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T13,T50
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T12,T13,T23
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T10

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T10
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	551568653	244	0	0
CheckAccumTrig0_A	551568653	456	0	0
CheckAccumTrig1_A	551568653	21	0	0
CheckClr_A	551568653	210	0	0
CheckEn_A	551396352	221515276	0	0
CheckPhase0_A	551568653	508	0	0
CheckPhase1_A	551568653	494	0	0
CheckPhase2_A	551568653	481	0	0
CheckPhase3_A	551568653	466	0	0
CheckTimeout0_A	551568653	1359	0	0
CheckTimeoutSt1_A	551568653	124236	0	0
CheckTimeoutSt2_A	551568653	1284	0	0
CheckTimeoutStTrig_A	551568653	52	0	0
ErrorStAllEscAsserted_A	551568653	1244	0	0
ErrorStIsTerminal_A	551568653	1004	0	0
EscStateOut_A	551394821	551327306	0	0
u_state_regs_A	551568653	551399471	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	244	0	0
T5	44267	67	0	0
T6	44863	48	0	0
T10	0	28	0	0
T12	30323	0	0	0
T13	17225	0	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T47	0	61	0	0
T48	0	40	0	0
T49	85053	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	456	0	0
T6	44863	0	0	0
T12	30323	2	0	0
T13	17225	4	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	1	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T28	0	3	0	0
T36	0	1	0	0
T42	17850	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T49	85053	0	0	0
T50	0	3	0	0
T54	0	4	0	0
T55	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	21	0	0
T35	491120	0	0	0
T57	34005	1	0	0
T58	35529	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T76	3449	0	0	0
T77	36775	0	0	0
T78	39948	0	0	0
T79	49971	0	0	0
T80	18321	0	0	0
T81	16317	0	0	0
T82	97119	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	210	0	0
T6	44863	0	0	0
T12	30323	1	0	0
T13	17225	4	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T28	0	1	0	0
T29	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T42	17850	0	0	0
T44	0	1	0	0
T49	85053	0	0	0
T50	0	2	0	0
T54	0	3	0	0
T86	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551396352	221515276	0	0
T1	4132	2836	0	0
T2	10946	10858	0	0
T3	16605	11054	0	0
T4	39376	1842	0	0
T5	334	252	0	0
T9	21505	21432	0	0
T11	12961	12875	0	0
T12	30323	4318	0	0
T21	56602	56502	0	0
T22	978	602	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	508	0	0
T6	44863	0	0	0
T12	30323	2	0	0
T13	17225	5	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	1	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T28	0	3	0	0
T36	0	1	0	0
T42	17850	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T49	85053	0	0	0
T50	0	3	0	0
T54	0	4	0	0
T55	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	494	0	0
T6	44863	0	0	0
T12	30323	2	0	0
T13	17225	5	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	1	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T28	0	3	0	0
T36	0	1	0	0
T42	17850	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T49	85053	0	0	0
T50	0	3	0	0
T54	0	4	0	0
T55	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	481	0	0
T6	44863	0	0	0
T12	30323	2	0	0
T13	17225	5	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	1	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T28	0	3	0	0
T36	0	1	0	0
T42	17850	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T49	85053	0	0	0
T50	0	3	0	0
T54	0	4	0	0
T55	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	466	0	0
T6	44863	0	0	0
T12	30323	2	0	0
T13	17225	5	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	1	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T28	0	3	0	0
T42	17850	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T49	85053	0	0	0
T50	0	3	0	0
T54	0	4	0	0
T55	0	1	0	0
T88	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	1359	0	0
T3	16605	1	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	1	0	0
T13	17225	1	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T25	0	1	0	0
T40	0	1	0	0
T44	0	4	0	0
T49	0	8	0	0
T54	0	1	0	0
T75	0	1	0	0
T89	0	9	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	124236	0	0
T3	16605	160	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	15	0	0
T13	17225	336	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T25	0	145	0	0
T40	0	123	0	0
T44	0	244	0	0
T49	0	1378	0	0
T54	0	20	0	0
T75	0	173	0	0
T89	0	1193	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	1284	0	0
T3	16605	1	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	1	0	0
T13	17225	0	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T25	0	1	0	0
T40	0	1	0	0
T44	0	4	0	0
T49	0	8	0	0
T54	0	1	0	0
T75	0	1	0	0
T89	0	9	0	0
T94	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	52	0	0
T6	44863	0	0	0
T7	103945	0	0	0
T13	17225	1	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T29	0	1	0	0
T35	0	1	0	0
T42	17850	0	0	0
T49	85053	0	0	0
T50	7702	0	0	0
T87	47018	0	0	0
T90	0	1	0	0
T94	0	1	0	0
T95	0	2	0	0
T96	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	5	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	1244	0	0
T5	44267	294	0	0
T6	44863	324	0	0
T10	0	152	0	0
T12	30323	0	0	0
T13	17225	0	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T47	0	302	0	0
T48	0	172	0	0
T49	85053	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	1004	0	0
T5	44267	234	0	0
T6	44863	264	0	0
T10	0	122	0	0
T12	30323	0	0	0
T13	17225	0	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T47	0	242	0	0
T48	0	142	0	0
T49	85053	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551394821	551327306	0	0
T1	4132	4034	0	0
T2	10946	10859	0	0
T3	16605	16517	0	0
T4	39376	39218	0	0
T5	95	14	0	0
T9	21505	21433	0	0
T11	12961	12876	0	0
T12	30323	30241	0	0
T21	56602	56503	0	0
T22	978	922	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	551399471	0	0
T1	4132	4034	0	0
T2	10946	10859	0	0
T3	16605	16517	0	0
T4	39376	39218	0	0
T5	44267	18769	0	0
T9	21505	21433	0	0
T11	12961	12876	0	0
T12	30323	30241	0	0
T21	56602	56503	0	0
T22	978	922	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T11 T12 T13 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T11 T12 T13 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T11 T12 T13 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T13 T75 
159        1/1                    state_d = TimeoutSt;
           Tests:       T3 T13 T75 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T3 T13 T75 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T3 T13 T75 
172        1/1                    state_d    = Phase0St;
           Tests:       T13 T75 T28 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T13 T75 T28 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T13 T75 T28 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T13 T75 T28 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T3 T13 T75 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T13 T75 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T3 T13 T44 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T13 T44 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T11 T12 T13 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T11 T12 T13 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T11 T12 T13 
190        1/1                  esc_state_o = Phase0;
           Tests:       T11 T12 T13 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T11 T12 T13 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T11 T12 T13 
194        1/1                    state_d = IdleSt;
           Tests:       T114 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T114 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T114 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T11 T12 T13 
198        1/1                    state_d = Phase1St;
           Tests:       T11 T12 T13 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T12 T13 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T11 T12 T13 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T11 T12 T13 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T11 T12 T13 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T11 T12 T13 
207        1/1                  esc_state_o = Phase1;
           Tests:       T11 T12 T13 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T11 T12 T13 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T11 T12 T13 
211        1/1                    state_d = IdleSt;
           Tests:       T29 T115 T35 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T115 T35 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T29 T115 T35 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T11 T12 T13 
215        1/1                    state_d = Phase2St;
           Tests:       T11 T12 T13 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T12 T13 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T11 T12 T13 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T11 T12 T13 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T11 T12 T13 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T11 T12 T13 
224        1/1                  esc_state_o = Phase2;
           Tests:       T11 T12 T13 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T11 T12 T13 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T11 T12 T13 
229        1/1                    state_d = IdleSt;
           Tests:       T116 T117 T118 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T116 T117 T118 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T116 T117 T118 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T11 T12 T13 
233        1/1                    state_d = Phase3St;
           Tests:       T11 T12 T13 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T12 T13 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T11 T12 T13 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T11 T12 T13 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T11 T12 T13 
241        1/1                  esc_state_o = Phase3;
           Tests:       T11 T12 T13 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T11 T12 T13 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T11 T12 T13 
245        1/1                    state_d = IdleSt;
           Tests:       T119 T120 T121 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T119 T120 T121 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T119 T120 T121 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T11 T12 T13 
249        1/1                    state_d = TerminalSt;
           Tests:       T11 T12 T13 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T12 T13 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T11 T12 T13 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T11 T12 T13 
259        1/1                  esc_state_o = Terminal;
           Tests:       T11 T12 T13 
260        1/1                  if (clr_i) begin
           Tests:       T11 T12 T13 
261        1/1                    state_d = IdleSt;
           Tests:       T13 T44 T54 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T6 T10 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T6 T10 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T6 T10 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T6 T10 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T3,T11,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T11,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T11,T12,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T11
1	0	1	Covered	T87,T52,T122
1	1	0	Covered	T3,T23,T25
1	1	1	Covered	T3,T13,T75

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T13,T75
0	1	Covered	T13,T75,T91
1	0	Covered	T28,T123,T124

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T13,T75
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T28,T123,T124

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T13,T75
1	0	Not Covered
1	1	Covered	T13,T75,T91

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T52,T75,T44

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T12,T52,T75
1	Covered	T11,T13,T28

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T122,T104,T40

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T13,T52
1	Covered	T12,T53,T54

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T5,T6,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T12,T53,T122

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T11,T13,T52

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T11,T12,T122

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T11,T13,T122

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T6,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T11,T12,T13
Phase1St	198	Covered	T11,T12,T13
Phase2St	215	Covered	T11,T12,T13
Phase3St	233	Covered	T11,T12,T13
TerminalSt	249	Covered	T11,T12,T13
TimeoutSt	159	Covered	T3,T13,T75

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T6,T10
IdleSt->Phase0St	152	Covered	T11,T12,T13
IdleSt->TimeoutSt	159	Covered	T3,T13,T75
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T45,T46,T97
Phase0St->Phase1St	198	Covered	T11,T12,T13
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T29,T115,T35
Phase1St->Phase2St	215	Covered	T11,T12,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T116,T117,T118
Phase2St->Phase3St	233	Covered	T11,T12,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T119,T120,T121
Phase3St->TerminalSt	249	Covered	T11,T12,T13
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T13,T44,T28
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T13,T44
TimeoutSt->Phase0St	172	Covered	T13,T75,T28

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T75
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T75,T28
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T75
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T44
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T114
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T11,T12,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T11,T12,T13
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T115,T35
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T11,T12,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T11,T12,T13
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T116,T117,T118
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T11,T12,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T11,T12,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T119,T120,T121
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T11,T12,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T11,T12,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T44,T54
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T11,T12,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T10

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T10
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	551568653	260	0	0
CheckAccumTrig0_A	551568653	439	0	0
CheckAccumTrig1_A	551568653	17	0	0
CheckClr_A	551568653	180	0	0
CheckEn_A	551396352	239834274	0	0
CheckPhase0_A	551568653	498	0	0
CheckPhase1_A	551568653	483	0	0
CheckPhase2_A	551568653	477	0	0
CheckPhase3_A	551568653	470	0	0
CheckTimeout0_A	551568653	534	0	0
CheckTimeoutSt1_A	551568653	65388	0	0
CheckTimeoutSt2_A	551568653	465	0	0
CheckTimeoutStTrig_A	551568653	48	0	0
ErrorStAllEscAsserted_A	551568653	1316	0	0
ErrorStIsTerminal_A	551568653	1076	0	0
EscStateOut_A	551394821	551327306	0	0
u_state_regs_A	551568653	551399471	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	260	0	0
T5	44267	92	0	0
T6	44863	75	0	0
T10	0	18	0	0
T12	30323	0	0	0
T13	17225	0	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T47	0	59	0	0
T48	0	16	0	0
T49	85053	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	439	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	1	0	0
T12	30323	1	0	0
T13	17225	3	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T40	0	1	0	0
T44	0	3	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T104	0	1	0	0
T122	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	17	0	0
T18	20441	0	0	0
T28	227996	1	0	0
T41	32170	0	0	0
T48	23232	0	0	0
T54	16394	0	0	0
T55	1601	0	0	0
T83	41108	0	0	0
T104	19343	0	0	0
T105	89174	0	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	2920	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	180	0	0
T6	44863	0	0	0
T7	103945	0	0	0
T13	17225	3	0	0
T15	0	1	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T29	0	2	0	0
T42	17850	0	0	0
T44	0	1	0	0
T49	85053	0	0	0
T50	7702	0	0	0
T54	0	1	0	0
T85	0	2	0	0
T87	47018	0	0	0
T91	0	1	0	0
T104	0	1	0	0
T115	0	1	0	0
T133	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551396352	239834274	0	0
T1	4132	2866	0	0
T2	10946	7276	0	0
T3	16605	11076	0	0
T4	39376	1850	0	0
T5	334	252	0	0
T9	21505	19223	0	0
T11	12961	3479	0	0
T12	30323	2461	0	0
T21	56602	56502	0	0
T22	978	610	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	498	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	1	0	0
T12	30323	1	0	0
T13	17225	4	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T28	0	1	0	0
T44	0	3	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T75	0	1	0	0
T122	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	483	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	1	0	0
T12	30323	1	0	0
T13	17225	4	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T28	0	1	0	0
T44	0	3	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T75	0	1	0	0
T122	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	477	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	1	0	0
T12	30323	1	0	0
T13	17225	4	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T28	0	1	0	0
T44	0	3	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T75	0	1	0	0
T122	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	470	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	1	0	0
T12	30323	1	0	0
T13	17225	4	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T28	0	1	0	0
T44	0	3	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T75	0	1	0	0
T122	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	534	0	0
T3	16605	1	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	0	0	0
T13	17225	4	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T28	0	2	0	0
T41	0	2	0	0
T44	0	1	0	0
T45	0	3	0	0
T75	0	1	0	0
T89	0	8	0	0
T90	0	2	0	0
T91	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	65388	0	0
T3	16605	251	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	0	0	0
T13	17225	1021	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T28	0	188	0	0
T41	0	141	0	0
T44	0	79	0	0
T45	0	658	0	0
T75	0	151	0	0
T89	0	1142	0	0
T90	0	368	0	0
T91	0	341	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	465	0	0
T3	16605	1	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	0	0	0
T13	17225	3	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T28	0	1	0	0
T34	0	1	0	0
T41	0	2	0	0
T44	0	1	0	0
T45	0	3	0	0
T89	0	8	0	0
T90	0	2	0	0
T91	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	48	0	0
T6	44863	0	0	0
T7	103945	0	0	0
T13	17225	1	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T42	17850	0	0	0
T49	85053	0	0	0
T50	7702	0	0	0
T63	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T87	47018	0	0	0
T91	0	1	0	0
T110	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	1316	0	0
T5	44267	330	0	0
T6	44863	352	0	0
T10	0	146	0	0
T12	30323	0	0	0
T13	17225	0	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T47	0	345	0	0
T48	0	143	0	0
T49	85053	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	1076	0	0
T5	44267	270	0	0
T6	44863	292	0	0
T10	0	116	0	0
T12	30323	0	0	0
T13	17225	0	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T47	0	285	0	0
T48	0	113	0	0
T49	85053	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551394821	551327306	0	0
T1	4132	4034	0	0
T2	10946	10859	0	0
T3	16605	16517	0	0
T4	39376	39218	0	0
T5	95	14	0	0
T9	21505	21433	0	0
T11	12961	12876	0	0
T12	30323	30241	0	0
T21	56602	56503	0	0
T22	978	922	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	551399471	0	0
T1	4132	4034	0	0
T2	10946	10859	0	0
T3	16605	16517	0	0
T4	39376	39218	0	0
T5	44267	18769	0	0
T9	21505	21433	0	0
T11	12961	12876	0	0
T12	30323	30241	0	0
T21	56602	56503	0	0
T22	978	922	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T1 T12 T13 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T12 T13 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T12 T13 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T13 T25 
159        1/1                    state_d = TimeoutSt;
           Tests:       T3 T13 T25 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T3 T13 T25 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T3 T13 T25 
172        1/1                    state_d    = Phase0St;
           Tests:       T3 T13 T36 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T3 T13 T36 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T3 T13 T36 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T3 T13 T36 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T3 T13 T25 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T13 T25 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T13 T25 T49 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T25 T49 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T12 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T3 T12 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T3 T12 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T3 T12 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T3 T12 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T3 T12 
194        1/1                    state_d = IdleSt;
           Tests:       T61 T138 T125 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T61 T138 T125 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T61 T138 T125 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T12 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T3 T12 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T12 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T3 T12 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T12 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T3 T12 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T3 T12 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T3 T12 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T3 T12 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T3 T12 
211        1/1                    state_d = IdleSt;
           Tests:       T34 T139 T140 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T139 T140 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T34 T139 T140 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T12 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T3 T12 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T12 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T3 T12 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T12 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T3 T12 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T3 T12 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T3 T12 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T3 T12 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T3 T12 
229        1/1                    state_d = IdleSt;
           Tests:       T141 T142 T143 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T141 T142 T143 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T141 T142 T143 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T12 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T3 T12 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T12 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T12 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T3 T12 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T3 T12 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T3 T12 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T3 T12 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T3 T12 
245        1/1                    state_d = IdleSt;
           Tests:       T38 T125 T144 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T38 T125 T144 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T38 T125 T144 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T12 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T3 T12 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T12 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T3 T12 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T3 T12 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T3 T12 
260        1/1                  if (clr_i) begin
           Tests:       T1 T3 T12 
261        1/1                    state_d = IdleSt;
           Tests:       T3 T13 T50 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T6 T10 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T6 T10 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T6 T10 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T6 T10 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T3,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T12,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T11
1	0	1	Covered	T1,T87,T39
1	1	0	Covered	T3,T12,T23
1	1	1	Covered	T3,T13,T25

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T13,T25
0	1	Covered	T3,T13,T36
1	0	Covered	T56,T90,T57

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T13,T25
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T56,T90,T57

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T13,T25
1	0	Covered	T41
1	1	Covered	T3,T13,T36

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T13
1	Covered	T1,T51,T56

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T43,T39,T52

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T13,T50,T54

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T13,T50
1	Covered	T3,T12,T13

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T5,T6,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T13,T51

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T3,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T6,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T12
Phase1St	198	Covered	T1,T3,T12
Phase2St	215	Covered	T1,T3,T12
Phase3St	233	Covered	T1,T3,T12
TerminalSt	249	Covered	T1,T3,T12
TimeoutSt	159	Covered	T3,T13,T25

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T6,T10
IdleSt->Phase0St	152	Covered	T1,T12,T13
IdleSt->TimeoutSt	159	Covered	T3,T13,T25
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T28,T35,T61
Phase0St->Phase1St	198	Covered	T1,T3,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T34,T139,T66
Phase1St->Phase2St	215	Covered	T1,T3,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T141,T142,T145
Phase2St->Phase3St	233	Covered	T1,T3,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T38,T125,T144
Phase3St->TerminalSt	249	Covered	T1,T3,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T13,T50
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T13,T25,T49
TimeoutSt->Phase0St	172	Covered	T3,T13,T36

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T25
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T36
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T25
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T25,T49
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T61,T138,T125
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T12,T13
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T34,T139,T140
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T12,T13
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T141,T142,T143
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T12,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T38,T125,T144
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T12,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T13,T50
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T10

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T10
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	551568653	216	0	0
CheckAccumTrig0_A	551568653	455	0	0
CheckAccumTrig1_A	551568653	26	0	0
CheckClr_A	551568653	205	0	0
CheckEn_A	551396352	215308870	0	0
CheckPhase0_A	551568653	514	0	0
CheckPhase1_A	551568653	506	0	0
CheckPhase2_A	551568653	502	0	0
CheckPhase3_A	551568653	495	0	0
CheckTimeout0_A	551568653	1330	0	0
CheckTimeoutSt1_A	551568653	153498	0	0
CheckTimeoutSt2_A	551568653	1251	0	0
CheckTimeoutStTrig_A	551568653	52	0	0
ErrorStAllEscAsserted_A	551568653	1286	0	0
ErrorStIsTerminal_A	551568653	1046	0	0
EscStateOut_A	551394821	551327306	0	0
u_state_regs_A	551568653	551399471	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	216	0	0
T5	44267	69	0	0
T6	44863	39	0	0
T10	0	30	0	0
T12	30323	0	0	0
T13	17225	0	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T47	0	48	0	0
T48	0	30	0	0
T49	85053	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	455	0	0
T1	4132	1	0	0
T2	10946	0	0	0
T3	16605	0	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	1	0	0
T13	0	3	0	0
T21	56602	0	0	0
T22	978	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	26	0	0
T20	142866	0	0	0
T56	177630	1	0	0
T57	0	1	0	0
T61	0	2	0	0
T85	25525	0	0	0
T90	0	1	0	0
T93	23705	0	0	0
T103	0	1	0	0
T111	0	1	0	0
T113	9068	0	0	0
T139	0	1	0	0
T141	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	16134	0	0	0
T149	14997	0	0	0
T150	182059	0	0	0
T151	647302	0	0	0
T152	117226	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	205	0	0
T3	16605	1	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	0	0	0
T13	17225	3	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T34	0	2	0	0
T36	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T50	0	1	0	0
T54	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551396352	215308870	0	0
T1	4132	2850	0	0
T2	10946	7263	0	0
T3	16605	10445	0	0
T4	39376	1846	0	0
T5	334	252	0	0
T9	21505	19211	0	0
T11	12961	3452	0	0
T12	30323	13308	0	0
T21	56602	56502	0	0
T22	978	606	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	514	0	0
T1	4132	1	0	0
T2	10946	0	0	0
T3	16605	1	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	1	0	0
T13	0	4	0	0
T21	56602	0	0	0
T22	978	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	506	0	0
T1	4132	1	0	0
T2	10946	0	0	0
T3	16605	1	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	1	0	0
T13	0	4	0	0
T21	56602	0	0	0
T22	978	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	502	0	0
T1	4132	1	0	0
T2	10946	0	0	0
T3	16605	1	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	1	0	0
T13	0	4	0	0
T21	56602	0	0	0
T22	978	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	495	0	0
T1	4132	1	0	0
T2	10946	0	0	0
T3	16605	1	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	1	0	0
T13	0	4	0	0
T21	56602	0	0	0
T22	978	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	1330	0	0
T3	16605	1	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	0	0	0
T13	17225	3	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T25	0	1	0	0
T36	0	1	0	0
T41	0	6	0	0
T44	0	14	0	0
T49	0	2	0	0
T54	0	1	0	0
T75	0	4	0	0
T89	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	153498	0	0
T3	16605	70	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	0	0	0
T13	17225	594	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T25	0	145	0	0
T36	0	108	0	0
T41	0	390	0	0
T44	0	825	0	0
T49	0	382	0	0
T54	0	14	0	0
T75	0	717	0	0
T89	0	416	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	1251	0	0
T6	44863	0	0	0
T7	103945	0	0	0
T13	17225	2	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	1	0	0
T41	0	6	0	0
T42	17850	0	0	0
T44	0	14	0	0
T49	85053	2	0	0
T50	7702	0	0	0
T56	0	2	0	0
T75	0	4	0	0
T87	47018	0	0	0
T89	0	3	0	0
T93	0	7	0	0
T94	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	52	0	0
T3	16605	1	0	0
T4	39376	0	0	0
T5	44267	0	0	0
T9	21505	0	0	0
T11	12961	0	0	0
T12	30323	0	0	0
T13	17225	1	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T45	0	1	0	0
T54	0	1	0	0
T78	0	1	0	0
T95	0	1	0	0
T153	0	2	0	0
T154	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	1286	0	0
T5	44267	308	0	0
T6	44863	332	0	0
T10	0	164	0	0
T12	30323	0	0	0
T13	17225	0	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T47	0	312	0	0
T48	0	170	0	0
T49	85053	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	1046	0	0
T5	44267	248	0	0
T6	44863	272	0	0
T10	0	134	0	0
T12	30323	0	0	0
T13	17225	0	0	0
T21	56602	0	0	0
T22	978	0	0	0
T23	61429	0	0	0
T24	68915	0	0	0
T25	7373	0	0	0
T47	0	252	0	0
T48	0	140	0	0
T49	85053	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551394821	551327306	0	0
T1	4132	4034	0	0
T2	10946	10859	0	0
T3	16605	16517	0	0
T4	39376	39218	0	0
T5	95	14	0	0
T9	21505	21433	0	0
T11	12961	12876	0	0
T12	30323	30241	0	0
T21	56602	56503	0	0
T22	978	922	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551568653	551399471	0	0
T1	4132	4034	0	0
T2	10946	10859	0	0
T3	16605	16517	0	0
T4	39376	39218	0	0
T5	44267	18769	0	0
T9	21505	21433	0	0
T11	12961	12876	0	0
T12	30323	30241	0	0
T21	56602	56503	0	0
T22	978	922	0	0