Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49553592	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

23483611

1

T1

1091

T2

122

T3

77

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	11672384	1			T1	1012		T2	73		T3	25
values[0x0]	30618229	1			T1	1046		T2	207		T3	140
values[0x1]	30746590	1			T1	1086		T2	173		T3	177

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43116421	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

29920782

1

T1

1366

T2

167

T3

113

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	232859	1			T1	12		T3	1		T9	16
valid_sources[0x01]	232829	1			T1	19		T9	19		T10	24
valid_sources[0x02]	234427	1			T1	10		T2	2		T9	21
valid_sources[0x03]	685652	1			T1	10		T2	2		T3	1
valid_sources[0x04]	231473	1			T1	4		T9	21		T10	8
valid_sources[0x05]	231984	1			T1	6		T2	5		T9	19
valid_sources[0x06]	239237	1			T1	8		T2	1		T3	1
valid_sources[0x07]	245628	1			T1	16		T2	4		T9	15
valid_sources[0x08]	264462	1			T1	16		T9	12		T11	36
valid_sources[0x09]	628983	1			T1	4		T2	6		T3	4
valid_sources[0x0a]	233103	1			T1	5		T3	3		T9	18
valid_sources[0x0b]	239366	1			T1	19		T3	1		T9	19
valid_sources[0x0c]	234326	1			T1	6		T2	2		T3	2
valid_sources[0x0d]	251049	1			T1	8		T2	4		T3	1
valid_sources[0x0e]	459411	1			T1	10		T3	2		T9	19
valid_sources[0x0f]	533202	1			T1	3		T3	3		T9	19
valid_sources[0x10]	273943	1			T1	20		T2	5		T3	3
valid_sources[0x11]	238333	1			T1	8		T2	2		T3	1
valid_sources[0x12]	235920	1			T1	6		T2	2		T3	1
valid_sources[0x13]	229591	1			T1	12		T3	2		T9	21
valid_sources[0x14]	234612	1			T1	18		T9	16		T10	28
valid_sources[0x15]	229392	1			T1	28		T9	17		T10	74
valid_sources[0x16]	228676	1			T1	12		T3	1		T9	15
valid_sources[0x17]	262204	1			T1	31		T2	8		T3	1
valid_sources[0x18]	232796	1			T1	5		T3	2		T9	30
valid_sources[0x19]	236150	1			T1	8		T2	1		T9	29
valid_sources[0x1a]	682891	1			T1	19		T2	6		T9	16
valid_sources[0x1b]	484480	1			T1	6		T3	1		T9	21
valid_sources[0x1c]	245920	1			T1	20		T3	2		T9	11
valid_sources[0x1d]	234255	1			T1	18		T2	6		T3	2
valid_sources[0x1e]	230479	1			T1	32		T2	1		T3	5
valid_sources[0x1f]	234523	1			T1	14		T2	5		T3	1
valid_sources[0x20]	231451	1			T1	28		T2	4		T3	1
valid_sources[0x21]	230228	1			T1	1		T2	2		T3	1
valid_sources[0x22]	233016	1			T1	16		T3	1		T9	22
valid_sources[0x23]	576650	1			T1	5		T2	6		T3	2
valid_sources[0x24]	254299	1			T1	30		T2	1		T9	20
valid_sources[0x25]	233099	1			T1	11		T9	30		T10	82
valid_sources[0x26]	236731	1			T1	7		T2	11		T9	32
valid_sources[0x27]	244698	1			T1	20		T9	17		T10	7
valid_sources[0x28]	231481	1			T1	19		T9	28		T10	50
valid_sources[0x29]	234287	1			T1	7		T2	1		T3	1
valid_sources[0x2a]	238435	1			T1	17		T2	5		T9	18
valid_sources[0x2b]	228910	1			T1	13		T3	1		T9	21
valid_sources[0x2c]	233102	1			T9	23		T10	92		T4	5
valid_sources[0x2d]	232172	1			T1	8		T2	10		T9	11
valid_sources[0x2e]	238465	1			T1	11		T9	29		T10	22
valid_sources[0x2f]	236940	1			T1	17		T3	2		T9	17
valid_sources[0x30]	531016	1			T1	6		T3	1		T9	15
valid_sources[0x31]	606057	1			T1	18		T3	3		T9	21
valid_sources[0x32]	236678	1			T1	6		T2	6		T3	3
valid_sources[0x33]	641599	1			T1	14		T9	9		T10	10
valid_sources[0x34]	266201	1			T1	20		T2	2		T3	3
valid_sources[0x35]	233093	1			T1	1		T2	3		T3	1
valid_sources[0x36]	231656	1			T1	23		T2	1		T9	23
valid_sources[0x37]	242079	1			T1	26		T2	1		T3	3
valid_sources[0x38]	233746	1			T1	5		T2	3		T9	18
valid_sources[0x39]	432255	1			T1	18		T3	2		T9	28
valid_sources[0x3a]	230148	1			T1	14		T3	1		T9	15
valid_sources[0x3b]	233306	1			T1	1		T3	1		T9	18
valid_sources[0x3c]	234394	1			T1	4		T9	21		T10	8
valid_sources[0x3d]	230940	1			T1	4		T2	8		T3	4
valid_sources[0x3e]	231224	1			T1	11		T2	2		T3	1
valid_sources[0x3f]	231454	1			T1	20		T2	2		T3	1
valid_sources[0x40]	235385	1			T1	20		T3	1		T9	16
valid_sources[0x41]	238077	1			T1	5		T2	1		T3	2
valid_sources[0x42]	247621	1			T1	5		T3	1		T9	29
valid_sources[0x43]	235634	1			T1	5		T3	1		T9	18
valid_sources[0x44]	231090	1			T1	16		T3	2		T9	20
valid_sources[0x45]	231883	1			T1	16		T2	4		T3	2
valid_sources[0x46]	642867	1			T1	25		T3	2		T9	26
valid_sources[0x47]	262325	1			T1	40		T2	3		T9	16
valid_sources[0x48]	231082	1			T1	7		T2	3		T3	4
valid_sources[0x49]	245015	1			T1	29		T2	5		T3	2
valid_sources[0x4a]	231384	1			T1	13		T9	14		T10	36
valid_sources[0x4b]	234161	1			T1	7		T3	1		T9	19
valid_sources[0x4c]	230587	1			T1	19		T2	2		T3	1
valid_sources[0x4d]	235311	1			T1	7		T9	20		T4	2
valid_sources[0x4e]	259362	1			T1	4		T3	1		T9	24
valid_sources[0x4f]	229592	1			T1	1		T2	10		T3	1
valid_sources[0x50]	232141	1			T1	20		T3	1		T9	18
valid_sources[0x51]	232617	1			T1	1		T2	6		T9	28
valid_sources[0x52]	240338	1			T1	10		T3	2		T9	18
valid_sources[0x53]	626006	1			T1	6		T3	2		T9	15
valid_sources[0x54]	231670	1			T1	1		T3	4		T9	18
valid_sources[0x55]	243696	1			T1	11		T2	3		T3	3
valid_sources[0x56]	232123	1			T1	26		T2	24		T3	1
valid_sources[0x57]	229362	1			T1	22		T3	2		T9	15
valid_sources[0x58]	250522	1			T1	5		T3	2		T9	22
valid_sources[0x59]	241238	1			T1	18		T3	2		T9	14
valid_sources[0x5a]	235763	1			T3	2		T9	22		T10	59
valid_sources[0x5b]	622849	1			T1	11		T2	3		T3	1
valid_sources[0x5c]	230071	1			T1	5		T9	21		T10	48
valid_sources[0x5d]	230542	1			T1	5		T3	1		T9	28
valid_sources[0x5e]	693397	1			T1	2		T3	1		T9	28
valid_sources[0x5f]	229251	1			T1	5		T2	2		T3	2
valid_sources[0x60]	243708	1			T1	26		T9	19		T10	44
valid_sources[0x61]	233115	1			T1	3		T2	13		T3	1
valid_sources[0x62]	236058	1			T1	11		T9	19		T10	14
valid_sources[0x63]	230092	1			T1	15		T3	2		T9	22
valid_sources[0x64]	231797	1			T1	8		T3	1		T9	19
valid_sources[0x65]	237374	1			T1	17		T2	13		T9	22
valid_sources[0x66]	259331	1			T1	26		T3	3		T9	14
valid_sources[0x67]	235161	1			T1	11		T9	17		T10	52
valid_sources[0x68]	232146	1			T1	12		T2	6		T9	13
valid_sources[0x69]	231653	1			T1	3		T3	1		T9	18
valid_sources[0x6a]	230749	1			T1	6		T9	17		T10	59
valid_sources[0x6b]	233728	1			T1	7		T9	21		T10	45
valid_sources[0x6c]	234454	1			T1	34		T2	2		T3	1
valid_sources[0x6d]	230942	1			T1	12		T3	2		T9	14
valid_sources[0x6e]	236812	1			T1	16		T9	14		T10	56
valid_sources[0x6f]	574445	1			T1	25		T9	28		T10	20
valid_sources[0x70]	232272	1			T1	16		T9	17		T10	12
valid_sources[0x71]	235413	1			T1	10		T2	3		T3	2
valid_sources[0x72]	237408	1			T1	33		T2	2		T3	3
valid_sources[0x73]	232400	1			T1	14		T3	2		T9	14
valid_sources[0x74]	229664	1			T1	28		T3	1		T9	18
valid_sources[0x75]	231783	1			T1	25		T3	1		T9	16
valid_sources[0x76]	232452	1			T1	10		T3	1		T9	20
valid_sources[0x77]	233343	1			T1	10		T3	3		T9	18
valid_sources[0x78]	232229	1			T1	26		T2	3		T3	2
valid_sources[0x79]	597916	1			T1	11		T2	3		T3	2
valid_sources[0x7a]	507684	1			T1	15		T2	2		T3	1
valid_sources[0x7b]	238796	1			T1	1		T3	2		T9	12
valid_sources[0x7c]	229785	1			T1	3		T9	28		T10	65
valid_sources[0x7d]	231601	1			T1	9		T9	27		T10	87
valid_sources[0x7e]	235116	1			T1	16		T3	3		T9	14
valid_sources[0x7f]	240047	1			T1	25		T3	1		T9	26
valid_sources[0x80]	236786	1			T9	17		T10	17		T11	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5590875

1

T1

516

T2

37

T3

12

values[0x0]

all_enables

biggest_size

11419742

1

T1

373

T2

61

T3

43

values[0x1]

all_enables

biggest_size

6472994

1

T1

202

T2

24

T3

22