Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	100.00	100.00	86.49			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00		96.12			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	86.49			86.49

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.65	100.00	100.00	94.59			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00		96.12			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	94.59			94.59

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	100.00	100.00	86.49			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00		96.12			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	86.49			86.49

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	100.00	89.19			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00		96.12			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	89.19			89.19

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T12,T10
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T13,T45
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13861	0	0
DisabledNoTrigBkwd_A	2147483647	632667	0	0
DisabledNoTrigFwd_A	2147483647	1211876668	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13861	0	0
T3	2907	534	0	0
T4	64644	0	0	0
T5	20239	0	0	0
T9	48781	0	0	0
T10	54848	0	0	0
T11	42218	0	0	0
T12	37890	0	0	0
T13	9086	1446	0	0
T14	16870	0	0	0
T17	27112	0	0	0
T18	5414	0	0	0
T28	17536	0	0	0
T45	3521	1136	0	0
T47	4065	0	0	0
T53	0	680	0	0
T57	0	291	0	0
T80	0	321	0	0
T88	47949	0	0	0
T89	13966	0	0	0
T99	57405	0	0	0
T100	55255	0	0	0
T126	1093	291	0	0
T135	0	394	0	0
T143	7470	0	0	0
T229	0	643	0	0
T248	0	304	0	0
T249	0	850	0	0
T250	0	679	0	0
T251	0	697	0	0
T252	0	836	0	0
T253	0	1486	0	0
T254	0	438	0	0
T255	0	276	0	0
T256	0	372	0	0
T257	0	777	0	0
T258	0	1410	0	0
T259	110092	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	632667	0	0
T1	14143	16	0	0
T2	19766	0	0	0
T3	2907	8	0	0
T4	96966	0	0	0
T5	60717	0	0	0
T6	71736	0	0	0
T9	48781	7	0	0
T10	82272	882	0	0
T11	63327	20	0	0
T12	75780	95	0	0
T13	9086	32	0	0
T14	16870	0	0	0
T15	30080	18	0	0
T17	40668	12	0	0
T18	8121	0	0	0
T20	30231	3	0	0
T25	14207	0	0	0
T43	0	4	0	0
T45	10563	21	0	0
T46	0	9	0	0
T47	8130	10	0	0
T53	1413	9	0	0
T54	22882	2	0	0
T55	0	11	0	0
T56	0	11	0	0
T57	0	8	0	0
T59	0	1	0	0
T60	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1211876668	0	0
T1	56572	48525	0	0
T2	79064	27374	0	0
T3	11628	8777	0	0
T4	129288	77200	0	0
T9	195124	148013	0	0
T10	109696	83780	0	0
T11	84436	65765	0	0
T12	151560	76774	0	0
T13	18172	11030	0	0
T18	10828	8683	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T4
1	1	Covered	T1,T3,T9

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T135,T249
1	1	Covered	T1,T3,T9

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T9

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	543226663	5281	0	0
DisabledNoTrigBkwd_A	543226663	134424	0	0
DisabledNoTrigFwd_A	543226663	292732929	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	5281	0	0
T3	2907	534	0	0
T4	32322	0	0	0
T9	48781	0	0	0
T10	27424	0	0	0
T11	21109	0	0	0
T12	37890	0	0	0
T13	4543	0	0	0
T14	8435	0	0	0
T17	13556	0	0	0
T18	2707	0	0	0
T80	0	321	0	0
T135	0	394	0	0
T229	0	643	0	0
T249	0	850	0	0
T253	0	1486	0	0
T255	0	276	0	0
T257	0	777	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	134424	0	0
T1	14143	16	0	0
T2	19766	0	0	0
T3	2907	8	0	0
T4	32322	0	0	0
T9	48781	7	0	0
T10	27424	0	0	0
T11	21109	20	0	0
T12	37890	57	0	0
T13	4543	0	0	0
T15	0	14	0	0
T17	0	9	0	0
T18	2707	0	0	0
T20	0	3	0	0
T47	0	10	0	0
T54	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	292732929	0	0
T1	14143	6303	0	0
T2	19766	2569	0	0
T3	2907	2170	0	0
T4	32322	19300	0	0
T9	48781	1946	0	0
T10	27424	27363	0	0
T11	21109	2657	0	0
T12	37890	582	0	0
T13	4543	2738	0	0
T18	2707	802	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T9 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T10,T14,T17
1	1	Covered	T2,T12,T13

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T45,T53
1	1	Covered	T2,T12,T13

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T12,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	543226663	5773	0	0
DisabledNoTrigBkwd_A	543226663	176984	0	0
DisabledNoTrigFwd_A	543226663	315315583	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	5773	0	0
T4	32322	0	0	0
T5	20239	0	0	0
T10	27424	0	0	0
T11	21109	0	0	0
T13	4543	1446	0	0
T14	8435	0	0	0
T17	13556	0	0	0
T18	2707	0	0	0
T45	3521	1136	0	0
T47	4065	0	0	0
T53	0	680	0	0
T57	0	291	0	0
T254	0	438	0	0
T256	0	372	0	0
T258	0	1410	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	176984	0	0
T4	32322	0	0	0
T5	20239	0	0	0
T10	27424	0	0	0
T11	21109	0	0	0
T12	37890	38	0	0
T13	4543	32	0	0
T14	8435	0	0	0
T15	0	2	0	0
T17	13556	3	0	0
T18	2707	0	0	0
T45	3521	21	0	0
T46	0	6	0	0
T53	0	9	0	0
T55	0	5	0	0
T56	0	7	0	0
T57	0	8	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	315315583	0	0
T1	14143	14074	0	0
T2	19766	2576	0	0
T3	2907	2184	0	0
T4	32322	19300	0	0
T9	48781	48689	0	0
T10	27424	27363	0	0
T11	21109	21036	0	0
T12	37890	586	0	0
T13	4543	2749	0	0
T18	2707	2627	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T9 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T13,T10
1	0	Covered	T12,T14,T17
1	1	Covered	T10,T14,T20

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T126,T248,T250
1	1	Covered	T10,T14,T20

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T15,T55

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	543226663	1971	0	0
DisabledNoTrigBkwd_A	543226663	146148	0	0
DisabledNoTrigFwd_A	543226663	313353950	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	1971	0	0
T28	17536	0	0	0
T88	47949	0	0	0
T89	13966	0	0	0
T99	57405	0	0	0
T100	55255	0	0	0
T107	92314	0	0	0
T126	1093	291	0	0
T143	7470	0	0	0
T248	0	304	0	0
T250	0	679	0	0
T251	0	697	0	0
T259	110092	0	0	0
T260	116990	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	146148	0	0
T4	32322	0	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T10	27424	882	0	0
T11	21109	0	0	0
T14	8435	0	0	0
T15	0	2	0	0
T17	13556	0	0	0
T18	2707	0	0	0
T43	0	4	0	0
T45	3521	0	0	0
T46	0	3	0	0
T47	4065	0	0	0
T55	0	6	0	0
T56	0	4	0	0
T59	0	1	0	0
T60	0	3	0	0
T125	0	8	0	0
T126	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	313353950	0	0
T1	14143	14074	0	0
T2	19766	19635	0	0
T3	2907	2202	0	0
T4	32322	19300	0	0
T9	48781	48689	0	0
T10	27424	1691	0	0
T11	21109	21036	0	0
T12	37890	37803	0	0
T13	4543	2768	0	0
T18	2707	2627	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T9 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T13
1	0	Covered	T12,T10,T14
1	1	Covered	T14,T17,T15

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T252
1	1	Covered	T14,T17,T15

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T15,T55

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	543226663	836	0	0
DisabledNoTrigBkwd_A	543226663	175111	0	0
DisabledNoTrigFwd_A	543226663	290474206	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	836	0	0
T33	510500	0	0	0
T35	77211	0	0	0
T38	121090	0	0	0
T146	10969	0	0	0
T252	1618	836	0	0
T261	125314	0	0	0
T262	54638	0	0	0
T263	583610	0	0	0
T264	10037	0	0	0
T265	21829	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	175111	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T15	30080	33	0	0
T17	13556	2	0	0
T20	30231	0	0	0
T25	14207	0	0	0
T42	0	286	0	0
T45	3521	0	0	0
T46	0	1	0	0
T47	4065	0	0	0
T53	1413	0	0	0
T54	22882	0	0	0
T55	0	4	0	0
T56	0	8	0	0
T58	0	5	0	0
T87	0	57	0	0
T99	0	16	0	0
T143	0	7	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	290474206	0	0
T1	14143	14074	0	0
T2	19766	2594	0	0
T3	2907	2221	0	0
T4	32322	19300	0	0
T9	48781	48689	0	0
T10	27424	27363	0	0
T11	21109	21036	0	0
T12	37890	37803	0	0
T13	4543	2775	0	0
T18	2707	2627	0	0