Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00		96.12			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00		96.12			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.78	100.00	95.56	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00		96.12			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.78	100.00	95.56	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00		96.12			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T1 T2 T3 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T2 T3 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T2 T3 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T12 T14 
159        1/1                    state_d = TimeoutSt;
           Tests:       T1 T12 T14 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T1 T12 T14 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T1 T12 T14 
172        1/1                    state_d    = Phase0St;
           Tests:       T1 T12 T17 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T12 T17 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T1 T12 T17 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T12 T17 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T1 T12 T14 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T12 T14 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T14 T17 T15 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T14 T17 T15 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T3 T9 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T3 T9 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T3 T9 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T3 T9 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
194        1/1                    state_d = IdleSt;
           Tests:       T30 T31 T32 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T30 T31 T32 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T30 T31 T32 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T3 T9 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T3 T9 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T3 T9 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T3 T9 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T3 T9 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T3 T9 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
211        1/1                    state_d = IdleSt;
           Tests:       T15 T33 T34 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T15 T33 T34 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T15 T33 T34 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T3 T9 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T3 T9 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T3 T9 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T3 T9 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T3 T9 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T3 T9 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
229        1/1                    state_d = IdleSt;
           Tests:       T35 T36 T32 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T36 T32 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T36 T32 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T3 T9 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T3 T9 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T3 T9 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T3 T9 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T3 T9 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
245        1/1                    state_d = IdleSt;
           Tests:       T37 T38 T34 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T37 T38 T34 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T37 T38 T34 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T3 T9 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T3 T9 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T3 T9 
260        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
261        1/1                    state_d = IdleSt;
           Tests:       T1 T10 T11 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T39,T40,T41
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T12,T11
1	0	1	Covered	T3,T13,T10
1	1	0	Covered	T12,T14,T17
1	1	1	Covered	T1,T12,T14

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T14
0	1	Covered	T12,T17,T42
1	0	Covered	T1,T43,T44

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T12,T14
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T43,T44

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T14
1	0	Not Covered
1	1	Covered	T12,T17,T42

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T9,T12
1	Covered	T3,T13,T45

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T9,T11,T46

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T9,T12
1	Covered	T1,T47,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T12,T10,T11

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T12

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T9
Phase1St	198	Covered	T1,T3,T9
Phase2St	215	Covered	T1,T3,T9
Phase3St	233	Covered	T1,T3,T9
TerminalSt	249	Covered	T1,T3,T9
TimeoutSt	159	Covered	T1,T12,T14

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T4,T7,T8
IdleSt->Phase0St	152	Covered	T1,T3,T9
IdleSt->TimeoutSt	159	Covered	T1,T12,T14
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T48,T30,T49
Phase0St->Phase1St	198	Covered	T1,T3,T9
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T15,T33,T50
Phase1St->Phase2St	215	Covered	T1,T3,T9
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T35,T36,T32
Phase2St->Phase3St	233	Covered	T1,T3,T9
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T37,T38,T34
Phase3St->TerminalSt	249	Covered	T1,T3,T9
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T10,T11
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T14,T17,T15
TimeoutSt->Phase0St	172	Covered	T1,T12,T17

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T14
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T17
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T14,T17,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T31,T32
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T9
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T9,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T15,T33,T34
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T9
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T9,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T35,T36,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T9
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T9,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T37,T38,T34
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T9
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T9,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T10,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T9
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	844	0	0
CheckAccumTrig0_A	2147483647	2111	0	0
CheckAccumTrig1_A	2147483647	113	0	0
CheckClr_A	2147483647	1008	0	0
CheckEn_A	2147483647	970476367	0	0
CheckPhase0_A	2147483647	2400	0	0
CheckPhase1_A	2147483647	2346	0	0
CheckPhase2_A	2147483647	2297	0	0
CheckPhase3_A	2147483647	2246	0	0
CheckTimeout0_A	2147483647	2692	0	0
CheckTimeoutSt1_A	2147483647	355923	0	0
CheckTimeoutSt2_A	2147483647	2317	0	0
CheckTimeoutStTrig_A	2147483647	243	0	0
ErrorStAllEscAsserted_A	2147483647	4411	0	0
ErrorStIsTerminal_A	2147483647	3571	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	844	0	0
T4	129288	127	0	0
T5	80956	0	0	0
T6	143472	0	0	0
T7	0	248	0	0
T8	0	133	0	0
T14	33740	0	0	0
T15	120320	0	0	0
T17	54224	0	0	0
T20	120924	0	0	0
T45	14084	0	0	0
T47	16260	0	0	0
T51	0	115	0	0
T52	0	221	0	0
T53	5652	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2111	0	0
T1	14143	1	0	0
T2	19766	0	0	0
T3	2907	1	0	0
T4	96966	0	0	0
T5	40478	0	0	0
T6	35868	0	0	0
T7	46276	0	0	0
T9	48781	1	0	0
T10	82272	4	0	0
T11	63327	3	0	0
T12	37890	1	0	0
T13	9086	1	0	0
T14	16870	0	0	0
T15	30080	3	0	0
T16	2007	0	0	0
T17	27112	2	0	0
T18	8121	0	0	0
T20	0	1	0	0
T25	14207	0	0	0
T45	7042	1	0	0
T46	0	2	0	0
T47	8130	1	0	0
T53	0	1	0	0
T54	22882	2	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	113	0	0
T1	14143	1	0	0
T2	19766	0	0	0
T3	2907	0	0	0
T4	32322	0	0	0
T9	48781	0	0	0
T10	27424	0	0	0
T11	21109	0	0	0
T12	37890	0	0	0
T13	4543	0	0	0
T18	2707	0	0	0
T43	63618	1	0	0
T44	0	1	0	0
T50	0	2	0	0
T61	0	2	0	0
T62	457269	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	2	0	0
T66	0	1	0	0
T67	0	2	0	0
T68	0	2	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	4	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	178936	0	0	0
T79	80516	0	0	0
T80	2656	0	0	0
T81	48485	0	0	0
T82	100061	0	0	0
T83	132078	0	0	0
T84	39006	0	0	0
T85	445386	0	0	0
T86	116738	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1008	0	0
T1	14143	1	0	0
T2	19766	0	0	0
T3	2907	0	0	0
T4	64644	0	0	0
T5	40478	0	0	0
T6	71736	0	0	0
T9	48781	0	0	0
T10	54848	3	0	0
T11	42218	2	0	0
T12	37890	0	0	0
T13	4543	0	0	0
T14	8435	0	0	0
T15	30080	2	0	0
T17	27112	3	0	0
T18	5414	0	0	0
T20	30231	0	0	0
T25	14207	0	0	0
T36	0	1	0	0
T37	0	8	0	0
T42	0	1	0	0
T43	0	3	0	0
T45	7042	0	0	0
T47	8130	0	0	0
T50	0	4	0	0
T53	1413	0	0	0
T54	22882	2	0	0
T59	0	1	0	0
T60	0	4	0	0
T87	0	1	0	0
T88	0	2	0	0
T89	0	2	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	970476367	0	0
T1	56572	43874	0	0
T2	79064	27369	0	0
T3	11628	8777	0	0
T4	2708	2436	0	0
T9	195124	148010	0	0
T10	109696	83777	0	0
T11	84436	65762	0	0
T12	151560	76772	0	0
T13	18172	11030	0	0
T18	10828	8680	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2400	0	0
T1	14143	2	0	0
T2	19766	0	0	0
T3	2907	1	0	0
T4	96966	0	0	0
T5	60717	0	0	0
T6	71736	0	0	0
T9	48781	1	0	0
T10	82272	4	0	0
T11	63327	3	0	0
T12	75780	2	0	0
T13	9086	1	0	0
T14	16870	0	0	0
T15	30080	3	0	0
T17	40668	4	0	0
T18	8121	0	0	0
T20	30231	1	0	0
T25	14207	0	0	0
T42	0	1	0	0
T45	10563	1	0	0
T46	0	2	0	0
T47	8130	1	0	0
T53	1413	1	0	0
T54	22882	2	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2346	0	0
T1	14143	2	0	0
T2	19766	0	0	0
T3	2907	1	0	0
T4	96966	0	0	0
T5	60717	0	0	0
T6	71736	0	0	0
T9	48781	1	0	0
T10	82272	4	0	0
T11	63327	3	0	0
T12	75780	2	0	0
T13	9086	1	0	0
T14	16870	0	0	0
T15	30080	2	0	0
T17	40668	4	0	0
T18	8121	0	0	0
T20	30231	1	0	0
T25	14207	0	0	0
T42	0	1	0	0
T45	10563	1	0	0
T46	0	2	0	0
T47	8130	1	0	0
T53	1413	1	0	0
T54	22882	2	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2297	0	0
T1	14143	2	0	0
T2	19766	0	0	0
T3	2907	1	0	0
T4	96966	0	0	0
T5	60717	0	0	0
T6	71736	0	0	0
T9	48781	1	0	0
T10	82272	4	0	0
T11	63327	3	0	0
T12	75780	2	0	0
T13	9086	1	0	0
T14	16870	0	0	0
T15	30080	2	0	0
T17	40668	4	0	0
T18	8121	0	0	0
T20	30231	1	0	0
T25	14207	0	0	0
T42	0	1	0	0
T45	10563	1	0	0
T46	0	2	0	0
T47	8130	1	0	0
T53	1413	1	0	0
T54	22882	2	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2246	0	0
T1	14143	2	0	0
T2	19766	0	0	0
T3	2907	1	0	0
T4	96966	0	0	0
T5	60717	0	0	0
T6	71736	0	0	0
T9	48781	1	0	0
T10	82272	4	0	0
T11	63327	3	0	0
T12	75780	2	0	0
T13	9086	1	0	0
T14	16870	0	0	0
T15	30080	2	0	0
T17	40668	4	0	0
T18	8121	0	0	0
T20	30231	1	0	0
T25	14207	0	0	0
T42	0	1	0	0
T45	10563	1	0	0
T46	0	2	0	0
T47	8130	1	0	0
T53	1413	1	0	0
T54	22882	2	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2692	0	0
T1	14143	1	0	0
T2	19766	0	0	0
T3	2907	0	0	0
T4	64644	0	0	0
T5	20239	0	0	0
T7	46276	0	0	0
T8	17970	0	0	0
T9	48781	0	0	0
T10	54848	0	0	0
T11	42218	0	0	0
T12	75780	1	0	0
T13	9086	0	0	0
T14	8435	5	0	0
T15	0	3	0	0
T16	2007	2	0	0
T17	13556	5	0	0
T18	5414	0	0	0
T42	0	4	0	0
T43	0	30	0	0
T45	3521	0	0	0
T46	30825	0	0	0
T55	37046	0	0	0
T58	0	1	0	0
T90	0	4	0	0
T95	0	5	0	0
T96	0	15	0	0
T97	0	13	0	0
T98	0	8	0	0
T99	0	2	0	0
T100	0	7	0	0
T101	0	2	0	0
T102	0	5	0	0
T103	0	1	0	0
T104	0	7	0	0
T105	11002	0	0	0
T106	24889	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	355923	0	0
T1	14143	1	0	0
T2	19766	0	0	0
T3	2907	0	0	0
T4	64644	0	0	0
T5	20239	0	0	0
T7	46276	0	0	0
T8	17970	0	0	0
T9	48781	0	0	0
T10	54848	0	0	0
T11	42218	0	0	0
T12	75780	101	0	0
T13	9086	0	0	0
T14	8435	438	0	0
T15	0	241	0	0
T16	2007	162	0	0
T17	13556	1878	0	0
T18	5414	0	0	0
T42	0	1309	0	0
T43	0	1510	0	0
T45	3521	0	0	0
T46	30825	0	0	0
T55	37046	0	0	0
T58	0	377	0	0
T90	0	19	0	0
T95	0	312	0	0
T96	0	2389	0	0
T97	0	3159	0	0
T98	0	1661	0	0
T99	0	1331	0	0
T100	0	961	0	0
T101	0	299	0	0
T102	0	962	0	0
T103	0	489	0	0
T104	0	1148	0	0
T105	11002	0	0	0
T106	24889	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2317	0	0
T5	60717	0	0	0
T6	107604	0	0	0
T7	46276	0	0	0
T8	17970	0	0	0
T14	25305	5	0	0
T15	90240	3	0	0
T16	2007	2	0	0
T17	40668	2	0	0
T20	90693	0	0	0
T25	42621	0	0	0
T43	0	29	0	0
T45	10563	0	0	0
T46	30825	0	0	0
T47	12195	0	0	0
T49	0	4	0	0
T53	4239	0	0	0
T55	37046	0	0	0
T56	41826	0	0	0
T57	1019	0	0	0
T58	0	1	0	0
T90	0	3	0	0
T95	0	5	0	0
T96	0	15	0	0
T97	0	13	0	0
T98	0	8	0	0
T99	0	1	0	0
T100	0	10	0	0
T101	0	2	0	0
T102	0	5	0	0
T103	0	1	0	0
T104	0	8	0	0
T105	11002	0	0	0
T106	24889	0	0	0
T107	0	7	0	0
T108	0	1	0	0
T109	0	12	0	0
T110	63529	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	243	0	0
T4	32322	0	0	0
T5	40478	0	0	0
T6	35868	0	0	0
T10	27424	0	0	0
T11	21109	0	0	0
T12	37890	1	0	0
T13	4543	0	0	0
T14	8435	0	0	0
T15	30080	0	0	0
T17	27112	3	0	0
T18	2707	0	0	0
T20	30231	0	0	0
T25	14207	0	0	0
T32	0	3	0	0
T33	0	5	0	0
T35	0	1	0	0
T42	12449	3	0	0
T45	7042	0	0	0
T47	4065	0	0	0
T49	0	4	0	0
T53	1413	0	0	0
T54	22882	0	0	0
T58	13515	0	0	0
T59	4720	0	0	0
T62	0	9	0	0
T65	0	1	0	0
T90	0	2	0	0
T97	92945	0	0	0
T99	0	2	0	0
T101	0	1	0	0
T104	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	5	0	0
T114	0	1	0	0
T115	0	2	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4411	0	0
T4	129288	623	0	0
T5	80956	0	0	0
T6	143472	0	0	0
T7	0	1274	0	0
T8	0	671	0	0
T14	33740	0	0	0
T15	120320	0	0	0
T17	54224	0	0	0
T20	120924	0	0	0
T45	14084	0	0	0
T47	16260	0	0	0
T51	0	632	0	0
T52	0	1211	0	0
T53	5652	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3571	0	0
T4	129288	503	0	0
T5	80956	0	0	0
T6	143472	0	0	0
T7	0	1034	0	0
T8	0	551	0	0
T14	33740	0	0	0
T15	120320	0	0	0
T17	54224	0	0	0
T20	120924	0	0	0
T45	14084	0	0	0
T47	16260	0	0	0
T51	0	512	0	0
T52	0	971	0	0
T53	5652	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	56572	56296	0	0
T2	79064	78540	0	0
T3	11628	11340	0	0
T4	684	416	0	0
T9	195124	194756	0	0
T10	109696	109452	0	0
T11	84436	84144	0	0
T12	151560	151212	0	0
T13	18172	17788	0	0
T18	10828	10508	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	56572	56296	0	0
T2	79064	78540	0	0
T3	11628	11340	0	0
T4	129288	77200	0	0
T9	195124	194756	0	0
T10	109696	109452	0	0
T11	84436	84144	0	0
T12	151560	151212	0	0
T13	18172	17788	0	0
T18	10828	10508	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T10 T15 T55 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T10 T15 T55 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T10 T15 T55 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T16 T95 T42 
159        1/1                    state_d = TimeoutSt;
           Tests:       T16 T95 T42 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T16 T95 T42 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T16 T95 T42 
172        1/1                    state_d    = Phase0St;
           Tests:       T42 T43 T112 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T42 T43 T112 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T42 T43 T112 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T42 T43 T112 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T16 T95 T42 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T16 T95 T42 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T16 T95 T97 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T16 T95 T97 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T15 T55 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T10 T15 T55 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T10 T15 T55 
190        1/1                  esc_state_o = Phase0;
           Tests:       T10 T15 T55 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T10 T15 T55 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T10 T15 T55 
194        1/1                    state_d = IdleSt;
           Tests:       T30 T119 T120 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T30 T119 T120 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T30 T119 T120 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T15 T55 
198        1/1                    state_d = Phase1St;
           Tests:       T10 T15 T55 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T15 T55 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T15 T55 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T15 T55 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T10 T15 T55 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T10 T15 T55 
207        1/1                  esc_state_o = Phase1;
           Tests:       T10 T15 T55 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T10 T15 T55 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T10 T15 T55 
211        1/1                    state_d = IdleSt;
           Tests:       T15 T121 T122 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T15 T121 T122 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T15 T121 T122 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T15 T55 
215        1/1                    state_d = Phase2St;
           Tests:       T10 T55 T46 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T55 T46 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T55 T46 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T55 T46 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T10 T55 T46 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T10 T55 T46 
224        1/1                  esc_state_o = Phase2;
           Tests:       T10 T55 T46 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T10 T55 T46 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T10 T55 T46 
229        1/1                    state_d = IdleSt;
           Tests:       T35 T123 T119 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T123 T119 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T123 T119 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T55 T46 
233        1/1                    state_d = Phase3St;
           Tests:       T10 T55 T46 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T55 T46 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T55 T46 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T10 T55 T46 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T10 T55 T46 
241        1/1                  esc_state_o = Phase3;
           Tests:       T10 T55 T46 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T10 T55 T46 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T10 T55 T46 
245        1/1                    state_d = IdleSt;
           Tests:       T71 T123 T124 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T71 T123 T124 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T71 T123 T124 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T55 T46 
249        1/1                    state_d = TerminalSt;
           Tests:       T10 T55 T46 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T55 T46 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T10 T55 T46 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T10 T55 T46 
259        1/1                  esc_state_o = Terminal;
           Tests:       T10 T55 T46 
260        1/1                  if (clr_i) begin
           Tests:       T10 T55 T46 
261        1/1                    state_d = IdleSt;
           Tests:       T10 T42 T59 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T10,T15,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T15,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T13,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T10,T15,T55

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T15,T16
1	0	1	Covered	T10,T20,T55
1	1	0	Covered	T12,T14,T17
1	1	1	Covered	T16,T95,T42

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T16,T95,T42
0	1	Covered	T42,T112,T33
1	0	Covered	T43,T50,T63

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T16,T95,T42
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T43,T50,T63

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T95,T42
1	0	Not Covered
1	1	Covered	T42,T112,T33

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T15,T56
1	Covered	T55,T46,T60

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T15,T55
1	Covered	T42,T59,T99

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T55,T46
1	Covered	T125,T92,T33

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T55,T46,T42
1	Covered	T10,T56,T43

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T10,T15,T56

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T10,T15,T46

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T55,T46,T42

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T15,T55,T46

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T10,T15,T55
Phase1St	198	Covered	T10,T15,T55
Phase2St	215	Covered	T10,T55,T46
Phase3St	233	Covered	T10,T55,T46
TerminalSt	249	Covered	T10,T55,T46
TimeoutSt	159	Covered	T16,T95,T42

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T7,T8
IdleSt->Phase0St	152	Covered	T10,T15,T55
IdleSt->TimeoutSt	159	Covered	T16,T95,T42
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T30,T50,T32
Phase0St->Phase1St	198	Covered	T10,T15,T55
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T15,T50,T31
Phase1St->Phase2St	215	Covered	T10,T55,T46
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T35,T123,T119
Phase2St->Phase3St	233	Covered	T10,T55,T46
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T71,T123,T124
Phase3St->TerminalSt	249	Covered	T10,T55,T46
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T10,T42,T59
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T16,T95,T97
TimeoutSt->Phase0St	172	Covered	T42,T43,T112

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T15,T55
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T95,T42
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T42,T43,T112
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T16,T95,T42
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T95,T97
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T119,T120
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T10,T15,T55
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T15,T55
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T15,T121,T122
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T10,T55,T46
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T10,T15,T55
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T35,T123,T119
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T10,T55,T46
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T55,T46
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T71,T123,T124
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T10,T55,T46
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T55,T46
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T42,T59
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T55,T46
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	543226663	185	0	0
CheckAccumTrig0_A	543226663	465	0	0
CheckAccumTrig1_A	543226663	28	0	0
CheckClr_A	543226663	229	0	0
CheckEn_A	542902733	243096490	0	0
CheckPhase0_A	543226663	533	0	0
CheckPhase1_A	543226663	521	0	0
CheckPhase2_A	543226663	506	0	0
CheckPhase3_A	543226663	501	0	0
CheckTimeout0_A	543226663	519	0	0
CheckTimeoutSt1_A	543226663	65795	0	0
CheckTimeoutSt2_A	543226663	433	0	0
CheckTimeoutStTrig_A	543226663	55	0	0
ErrorStAllEscAsserted_A	543226663	1090	0	0
ErrorStIsTerminal_A	543226663	880	0	0
EscStateOut_A	542900546	542833363	0	0
u_state_regs_A	543226663	543070428	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	185	0	0
T4	32322	25	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T7	0	54	0	0
T8	0	23	0	0
T14	8435	0	0	0
T15	30080	0	0	0
T17	13556	0	0	0
T20	30231	0	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T51	0	32	0	0
T52	0	51	0	0
T53	1413	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	465	0	0
T4	32322	0	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T10	27424	4	0	0
T11	21109	0	0	0
T14	8435	0	0	0
T15	0	1	0	0
T17	13556	0	0	0
T18	2707	0	0	0
T45	3521	0	0	0
T46	0	1	0	0
T47	4065	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T99	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	28	0	0
T28	17536	0	0	0
T43	63618	1	0	0
T50	0	2	0	0
T52	179893	0	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T71	0	2	0	0
T87	209227	0	0	0
T88	47949	0	0	0
T98	79053	0	0	0
T125	8206	0	0	0
T126	1093	0	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	2	0	0
T131	117922	0	0	0
T132	97463	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	229	0	0
T4	32322	0	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T10	27424	3	0	0
T11	21109	0	0	0
T14	8435	0	0	0
T15	0	1	0	0
T17	13556	0	0	0
T18	2707	0	0	0
T30	0	1	0	0
T42	0	1	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T49	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T90	0	2	0	0
T92	0	1	0	0
T133	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542902733	243096490	0	0
T1	14143	14073	0	0
T2	19766	19633	0	0
T3	2907	2202	0	0
T4	677	609	0	0
T9	48781	48688	0	0
T10	27424	1691	0	0
T11	21109	21035	0	0
T12	37890	37802	0	0
T13	4543	2768	0	0
T18	2707	2626	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	533	0	0
T4	32322	0	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T10	27424	4	0	0
T11	21109	0	0	0
T14	8435	0	0	0
T15	0	1	0	0
T17	13556	0	0	0
T18	2707	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	3521	0	0	0
T46	0	1	0	0
T47	4065	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T125	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	521	0	0
T4	32322	0	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T10	27424	4	0	0
T11	21109	0	0	0
T14	8435	0	0	0
T17	13556	0	0	0
T18	2707	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	3521	0	0	0
T46	0	1	0	0
T47	4065	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	506	0	0
T4	32322	0	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T10	27424	4	0	0
T11	21109	0	0	0
T14	8435	0	0	0
T17	13556	0	0	0
T18	2707	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	3521	0	0	0
T46	0	1	0	0
T47	4065	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	501	0	0
T4	32322	0	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T10	27424	4	0	0
T11	21109	0	0	0
T14	8435	0	0	0
T17	13556	0	0	0
T18	2707	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	3521	0	0	0
T46	0	1	0	0
T47	4065	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	519	0	0
T7	46276	0	0	0
T8	17970	0	0	0
T16	2007	1	0	0
T42	0	1	0	0
T43	0	4	0	0
T46	30825	0	0	0
T55	37046	0	0	0
T56	41826	0	0	0
T57	1019	0	0	0
T90	0	2	0	0
T95	0	2	0	0
T97	0	5	0	0
T98	0	2	0	0
T100	0	1	0	0
T102	0	4	0	0
T104	0	7	0	0
T105	11002	0	0	0
T106	24889	0	0	0
T110	63529	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	65795	0	0
T7	46276	0	0	0
T8	17970	0	0	0
T16	2007	81	0	0
T42	0	87	0	0
T43	0	585	0	0
T46	30825	0	0	0
T55	37046	0	0	0
T56	41826	0	0	0
T57	1019	0	0	0
T90	0	14	0	0
T95	0	119	0	0
T97	0	1340	0	0
T98	0	380	0	0
T100	0	121	0	0
T102	0	789	0	0
T104	0	1148	0	0
T105	11002	0	0	0
T106	24889	0	0	0
T110	63529	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	433	0	0
T7	46276	0	0	0
T8	17970	0	0	0
T16	2007	1	0	0
T43	0	3	0	0
T46	30825	0	0	0
T49	0	4	0	0
T55	37046	0	0	0
T56	41826	0	0	0
T57	1019	0	0	0
T90	0	2	0	0
T95	0	2	0	0
T97	0	5	0	0
T98	0	2	0	0
T100	0	1	0	0
T102	0	4	0	0
T104	0	7	0	0
T105	11002	0	0	0
T106	24889	0	0	0
T110	63529	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	55	0	0
T26	78670	0	0	0
T27	15095	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T42	12449	1	0	0
T58	13515	0	0	0
T59	4720	0	0	0
T60	34116	0	0	0
T62	0	3	0	0
T65	0	1	0	0
T97	92945	0	0	0
T112	0	1	0	0
T113	0	1	0	0
T115	0	1	0	0
T118	0	1	0	0
T134	33620	0	0	0
T135	2699	0	0	0
T136	105790	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	1090	0	0
T4	32322	148	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T7	0	318	0	0
T8	0	171	0	0
T14	8435	0	0	0
T15	30080	0	0	0
T17	13556	0	0	0
T20	30231	0	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T51	0	169	0	0
T52	0	284	0	0
T53	1413	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	880	0	0
T4	32322	118	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T7	0	258	0	0
T8	0	141	0	0
T14	8435	0	0	0
T15	30080	0	0	0
T17	13556	0	0	0
T20	30231	0	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T51	0	139	0	0
T52	0	224	0	0
T53	1413	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542900546	542833363	0	0
T1	14143	14074	0	0
T2	19766	19635	0	0
T3	2907	2835	0	0
T4	171	104	0	0
T9	48781	48689	0	0
T10	27424	27363	0	0
T11	21109	21036	0	0
T12	37890	37803	0	0
T13	4543	4447	0	0
T18	2707	2627	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	543070428	0	0
T1	14143	14074	0	0
T2	19766	19635	0	0
T3	2907	2835	0	0
T4	32322	19300	0	0
T9	48781	48689	0	0
T10	27424	27363	0	0
T11	21109	21036	0	0
T12	37890	37803	0	0
T13	4543	4447	0	0
T18	2707	2627	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T15 T55 T46 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T15 T55 T46 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T15 T55 T46 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T14 T17 T42 
159        1/1                    state_d = TimeoutSt;
           Tests:       T14 T17 T42 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T14 T17 T42 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T14 T17 T42 
172        1/1                    state_d    = Phase0St;
           Tests:       T17 T42 T101 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T17 T42 T101 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T17 T42 T101 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T17 T42 T101 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T14 T17 T42 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T14 T17 T42 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T14 T97 T99 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T14 T97 T99 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T17 T15 T55 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T17 T15 T55 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T17 T15 T55 
190        1/1                  esc_state_o = Phase0;
           Tests:       T17 T15 T55 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T17 T15 T55 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T17 T15 T55 
194        1/1                    state_d = IdleSt;
           Tests:       T31 T32 T117 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T32 T117 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T31 T32 T117 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T17 T15 T55 
198        1/1                    state_d = Phase1St;
           Tests:       T17 T15 T55 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T17 T15 T55 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T17 T15 T55 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T17 T15 T55 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T17 T15 T55 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T17 T15 T55 
207        1/1                  esc_state_o = Phase1;
           Tests:       T17 T15 T55 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T17 T15 T55 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T17 T15 T55 
211        1/1                    state_d = IdleSt;
           Tests:       T137 T138 T139 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T137 T138 T139 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T137 T138 T139 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T17 T15 T55 
215        1/1                    state_d = Phase2St;
           Tests:       T17 T15 T55 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T17 T15 T55 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T17 T15 T55 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T17 T15 T55 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T17 T15 T55 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T17 T15 T55 
224        1/1                  esc_state_o = Phase2;
           Tests:       T17 T15 T55 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T17 T15 T55 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T17 T15 T55 
229        1/1                    state_d = IdleSt;
           Tests:       T130 T140 T141 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T130 T140 T141 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T130 T140 T141 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T17 T15 T55 
233        1/1                    state_d = Phase3St;
           Tests:       T17 T15 T55 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T17 T15 T55 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T17 T15 T55 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T17 T15 T55 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T17 T15 T55 
241        1/1                  esc_state_o = Phase3;
           Tests:       T17 T15 T55 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T17 T15 T55 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T17 T15 T55 
245        1/1                    state_d = IdleSt;
           Tests:       T115 T130 T142 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T115 T130 T142 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T115 T130 T142 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T17 T15 T55 
249        1/1                    state_d = TerminalSt;
           Tests:       T17 T15 T55 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T17 T15 T55 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T17 T15 T55 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T17 T15 T55 
259        1/1                  esc_state_o = Terminal;
           Tests:       T17 T15 T55 
260        1/1                  if (clr_i) begin
           Tests:       T17 T15 T55 
261        1/1                    state_d = IdleSt;
           Tests:       T17 T15 T42 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T14,T17,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T14,T17,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T55,T46

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T17,T15
1	0	1	Covered	T46,T56,T131
1	1	0	Covered	T12,T17,T15
1	1	1	Covered	T14,T17,T42

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T42
0	1	Covered	T17,T101,T111
1	0	Covered	T42,T90,T93

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T14,T17,T42
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T42,T90,T93

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T42
1	0	Not Covered
1	1	Covered	T17,T101,T111

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T55,T42
1	Covered	T17,T46,T56

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T15,T46
1	Covered	T15,T55,T58

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T15,T55
1	Covered	T15,T143,T103

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T15,T55
1	Covered	T42,T99,T144

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T15,T42,T58

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T15,T55,T46

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T17,T15,T42

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T17,T15,T55

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T17,T15,T55
Phase1St	198	Covered	T17,T15,T55
Phase2St	215	Covered	T17,T15,T55
Phase3St	233	Covered	T17,T15,T55
TerminalSt	249	Covered	T17,T15,T55
TimeoutSt	159	Covered	T14,T17,T42

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T7,T8
IdleSt->Phase0St	152	Covered	T15,T55,T46
IdleSt->TimeoutSt	159	Covered	T14,T17,T42
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T49,T31,T32
Phase0St->Phase1St	198	Covered	T17,T15,T55
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T33,T137,T142
Phase1St->Phase2St	215	Covered	T17,T15,T55
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T49,T130,T140
Phase2St->Phase3St	233	Covered	T17,T15,T55
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T115,T64,T130
Phase3St->TerminalSt	249	Covered	T17,T15,T55
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T17,T15,T42
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T14,T97,T99
TimeoutSt->Phase0St	172	Covered	T17,T42,T101

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T55,T46
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T17,T42
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T42,T101
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T14,T17,T42
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T14,T97,T99
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T31,T32,T117
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T17,T15,T55
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T17,T15,T55
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T137,T138,T139
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T17,T15,T55
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T17,T15,T55
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T130,T140,T141
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T17,T15,T55
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T17,T15,T55
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T115,T130,T142
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T17,T15,T55
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T17,T15,T55
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T15,T42
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T17,T15,T55
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	543226663	185	0	0
CheckAccumTrig0_A	543226663	446	0	0
CheckAccumTrig1_A	543226663	24	0	0
CheckClr_A	543226663	206	0	0
CheckEn_A	542902733	229827764	0	0
CheckPhase0_A	543226663	514	0	0
CheckPhase1_A	543226663	503	0	0
CheckPhase2_A	543226663	495	0	0
CheckPhase3_A	543226663	483	0	0
CheckTimeout0_A	543226663	724	0	0
CheckTimeoutSt1_A	543226663	91091	0	0
CheckTimeoutSt2_A	543226663	630	0	0
CheckTimeoutStTrig_A	543226663	62	0	0
ErrorStAllEscAsserted_A	543226663	1188	0	0
ErrorStIsTerminal_A	543226663	978	0	0
EscStateOut_A	542900546	542833363	0	0
u_state_regs_A	543226663	543070428	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	185	0	0
T4	32322	28	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T7	0	51	0	0
T8	0	27	0	0
T14	8435	0	0	0
T15	30080	0	0	0
T17	13556	0	0	0
T20	30231	0	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T51	0	26	0	0
T52	0	53	0	0
T53	1413	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	446	0	0
T7	46276	0	0	0
T8	17970	0	0	0
T15	30080	2	0	0
T16	2007	0	0	0
T25	14207	0	0	0
T42	0	1	0	0
T46	30825	1	0	0
T54	22882	0	0	0
T55	37046	1	0	0
T56	0	1	0	0
T58	0	2	0	0
T87	0	1	0	0
T99	0	1	0	0
T105	11002	0	0	0
T106	24889	0	0	0
T107	0	1	0	0
T143	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	24	0	0
T26	78670	0	0	0
T27	15095	0	0	0
T42	12449	1	0	0
T58	13515	0	0	0
T59	4720	0	0	0
T60	34116	0	0	0
T62	0	1	0	0
T74	0	1	0	0
T90	0	1	0	0
T93	0	6	0	0
T97	92945	0	0	0
T117	0	3	0	0
T130	0	1	0	0
T134	33620	0	0	0
T135	2699	0	0	0
T136	105790	0	0	0
T137	0	1	0	0
T142	0	1	0	0
T145	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	206	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T15	30080	1	0	0
T17	13556	1	0	0
T20	30231	0	0	0
T25	14207	0	0	0
T42	0	1	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T49	0	1	0	0
T53	1413	0	0	0
T54	22882	0	0	0
T58	0	2	0	0
T90	0	1	0	0
T93	0	11	0	0
T112	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542902733	229827764	0	0
T1	14143	14073	0	0
T2	19766	2593	0	0
T3	2907	2221	0	0
T4	677	609	0	0
T9	48781	48688	0	0
T10	27424	27362	0	0
T11	21109	21035	0	0
T12	37890	37802	0	0
T13	4543	2775	0	0
T18	2707	2626	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	514	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T15	30080	2	0	0
T17	13556	1	0	0
T20	30231	0	0	0
T25	14207	0	0	0
T42	0	2	0	0
T45	3521	0	0	0
T46	0	1	0	0
T47	4065	0	0	0
T53	1413	0	0	0
T54	22882	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T58	0	2	0	0
T87	0	1	0	0
T99	0	1	0	0
T143	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	503	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T15	30080	2	0	0
T17	13556	1	0	0
T20	30231	0	0	0
T25	14207	0	0	0
T42	0	2	0	0
T45	3521	0	0	0
T46	0	1	0	0
T47	4065	0	0	0
T53	1413	0	0	0
T54	22882	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T58	0	2	0	0
T87	0	1	0	0
T99	0	1	0	0
T143	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	495	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T15	30080	2	0	0
T17	13556	1	0	0
T20	30231	0	0	0
T25	14207	0	0	0
T42	0	2	0	0
T45	3521	0	0	0
T46	0	1	0	0
T47	4065	0	0	0
T53	1413	0	0	0
T54	22882	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T58	0	2	0	0
T87	0	1	0	0
T99	0	1	0	0
T143	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	483	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T15	30080	2	0	0
T17	13556	1	0	0
T20	30231	0	0	0
T25	14207	0	0	0
T42	0	2	0	0
T45	3521	0	0	0
T46	0	1	0	0
T47	4065	0	0	0
T53	1413	0	0	0
T54	22882	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T58	0	2	0	0
T87	0	1	0	0
T99	0	1	0	0
T143	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	724	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T14	8435	2	0	0
T15	30080	0	0	0
T17	13556	1	0	0
T20	30231	0	0	0
T25	14207	0	0	0
T42	0	1	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T53	1413	0	0	0
T90	0	2	0	0
T97	0	1	0	0
T99	0	1	0	0
T100	0	6	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	91091	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T14	8435	159	0	0
T15	30080	0	0	0
T17	13556	744	0	0
T20	30231	0	0	0
T25	14207	0	0	0
T42	0	96	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T53	1413	0	0	0
T90	0	5	0	0
T97	0	255	0	0
T99	0	788	0	0
T100	0	840	0	0
T101	0	299	0	0
T102	0	173	0	0
T103	0	489	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	630	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T14	8435	2	0	0
T15	30080	0	0	0
T17	13556	0	0	0
T20	30231	0	0	0
T25	14207	0	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T53	1413	0	0	0
T90	0	1	0	0
T93	0	1	0	0
T97	0	1	0	0
T99	0	1	0	0
T100	0	6	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	62	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T15	30080	0	0	0
T17	13556	1	0	0
T20	30231	0	0	0
T25	14207	0	0	0
T33	0	1	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T49	0	2	0	0
T53	1413	0	0	0
T54	22882	0	0	0
T62	0	4	0	0
T101	0	1	0	0
T104	0	1	0	0
T111	0	1	0	0
T113	0	1	0	0
T115	0	1	0	0
T148	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	1188	0	0
T4	32322	163	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T7	0	350	0	0
T8	0	165	0	0
T14	8435	0	0	0
T15	30080	0	0	0
T17	13556	0	0	0
T20	30231	0	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T51	0	185	0	0
T52	0	325	0	0
T53	1413	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	978	0	0
T4	32322	133	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T7	0	290	0	0
T8	0	135	0	0
T14	8435	0	0	0
T15	30080	0	0	0
T17	13556	0	0	0
T20	30231	0	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T51	0	155	0	0
T52	0	265	0	0
T53	1413	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542900546	542833363	0	0
T1	14143	14074	0	0
T2	19766	19635	0	0
T3	2907	2835	0	0
T4	171	104	0	0
T9	48781	48689	0	0
T10	27424	27363	0	0
T11	21109	21036	0	0
T12	37890	37803	0	0
T13	4543	4447	0	0
T18	2707	2627	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	543070428	0	0
T1	14143	14074	0	0
T2	19766	19635	0	0
T3	2907	2835	0	0
T4	32322	19300	0	0
T9	48781	48689	0	0
T10	27424	27363	0	0
T11	21109	21036	0	0
T12	37890	37803	0	0
T13	4543	4447	0	0
T18	2707	2627	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T1 T3 T9 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T3 T9 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T3 T9 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T14 T17 
159        1/1                    state_d = TimeoutSt;
           Tests:       T1 T14 T17 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T1 T14 T17 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T1 T14 T17 
172        1/1                    state_d    = Phase0St;
           Tests:       T1 T17 T42 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T17 T42 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T1 T17 T42 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T17 T42 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T1 T14 T17 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T14 T17 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T14 T17 T15 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T14 T17 T15 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T3 T9 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T3 T9 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T3 T9 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T3 T9 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
194        1/1                    state_d = IdleSt;
           Tests:       T63 T117 T149 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T63 T117 T149 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T63 T117 T149 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T3 T9 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T3 T9 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T3 T9 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T3 T9 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T3 T9 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T3 T9 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
211        1/1                    state_d = IdleSt;
           Tests:       T33 T34 T67 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T34 T67 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T33 T34 T67 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T3 T9 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T3 T9 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T3 T9 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T3 T9 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T3 T9 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T3 T9 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
229        1/1                    state_d = IdleSt;
           Tests:       T32 T34 T150 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T34 T150 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T32 T34 T150 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T3 T9 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T3 T9 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T3 T9 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T3 T9 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T3 T9 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
245        1/1                    state_d = IdleSt;
           Tests:       T37 T38 T34 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T37 T38 T34 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T37 T38 T34 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T3 T9 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T3 T9 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T3 T9 
260        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
261        1/1                    state_d = IdleSt;
           Tests:       T1 T11 T17 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T9

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T40,T41,T151
1	1	1	Covered	T1,T3,T9

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T12,T11
1	0	1	Covered	T3,T20,T105
1	1	0	Covered	T14,T95,T96
1	1	1	Covered	T1,T14,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T17
0	1	Covered	T17,T42,T99
1	0	Covered	T1,T44,T61

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T14,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T44,T61

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T17
1	0	Not Covered
1	1	Covered	T17,T42,T99

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T9,T12
1	Covered	T3,T54,T56

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T9,T11,T58

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T9,T12
1	Covered	T1,T47,T55

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T12,T11,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T12

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T9
Phase1St	198	Covered	T1,T3,T9
Phase2St	215	Covered	T1,T3,T9
Phase3St	233	Covered	T1,T3,T9
TerminalSt	249	Covered	T1,T3,T9
TimeoutSt	159	Covered	T1,T14,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T7,T8
IdleSt->Phase0St	152	Covered	T1,T3,T9
IdleSt->TimeoutSt	159	Covered	T1,T14,T17
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T48,T49,T31
Phase0St->Phase1St	198	Covered	T1,T3,T9
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T33,T31,T34
Phase1St->Phase2St	215	Covered	T1,T3,T9
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T32,T34,T150
Phase2St->Phase3St	233	Covered	T1,T3,T9
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T37,T38,T34
Phase3St->TerminalSt	249	Covered	T1,T3,T9
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T11,T17
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T14,T17,T15
TimeoutSt->Phase0St	172	Covered	T1,T17,T42

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T9
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T14,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T42
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T14,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T14,T17,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T63,T117,T149
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T9
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T9,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T33,T34,T67
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T9
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T9,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T34,T150
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T9
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T9,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T37,T38,T34
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T9
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T9,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T11,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T9
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	543226663	247	0	0
CheckAccumTrig0_A	543226663	762	0	0
CheckAccumTrig1_A	543226663	36	0	0
CheckClr_A	543226663	359	0	0
CheckEn_A	542902733	244516868	0	0
CheckPhase0_A	543226663	838	0	0
CheckPhase1_A	543226663	817	0	0
CheckPhase2_A	543226663	801	0	0
CheckPhase3_A	543226663	775	0	0
CheckTimeout0_A	543226663	851	0	0
CheckTimeoutSt1_A	543226663	120215	0	0
CheckTimeoutSt2_A	543226663	749	0	0
CheckTimeoutStTrig_A	543226663	62	0	0
ErrorStAllEscAsserted_A	543226663	1086	0	0
ErrorStIsTerminal_A	543226663	876	0	0
EscStateOut_A	542900546	542833363	0	0
u_state_regs_A	543226663	543070428	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	247	0	0
T4	32322	39	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T7	0	78	0	0
T8	0	36	0	0
T14	8435	0	0	0
T15	30080	0	0	0
T17	13556	0	0	0
T20	30231	0	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T51	0	28	0	0
T52	0	66	0	0
T53	1413	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	762	0	0
T1	14143	1	0	0
T2	19766	0	0	0
T3	2907	1	0	0
T4	32322	0	0	0
T9	48781	1	0	0
T10	27424	0	0	0
T11	21109	3	0	0
T12	37890	1	0	0
T13	4543	0	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	2707	0	0	0
T20	0	1	0	0
T47	0	1	0	0
T54	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	36	0	0
T1	14143	1	0	0
T2	19766	0	0	0
T3	2907	0	0	0
T4	32322	0	0	0
T9	48781	0	0	0
T10	27424	0	0	0
T11	21109	0	0	0
T12	37890	0	0	0
T13	4543	0	0	0
T18	2707	0	0	0
T44	0	1	0	0
T61	0	2	0	0
T64	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T73	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	359	0	0
T1	14143	1	0	0
T2	19766	0	0	0
T3	2907	0	0	0
T4	32322	0	0	0
T9	48781	0	0	0
T10	27424	0	0	0
T11	21109	2	0	0
T12	37890	0	0	0
T13	4543	0	0	0
T17	0	1	0	0
T18	2707	0	0	0
T37	0	8	0	0
T43	0	3	0	0
T54	0	2	0	0
T60	0	2	0	0
T88	0	2	0	0
T89	0	1	0	0
T91	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542902733	244516868	0	0
T1	14143	1655	0	0
T2	19766	2568	0	0
T3	2907	2170	0	0
T4	677	609	0	0
T9	48781	1946	0	0
T10	27424	27362	0	0
T11	21109	2657	0	0
T12	37890	582	0	0
T13	4543	2738	0	0
T18	2707	802	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	838	0	0
T1	14143	2	0	0
T2	19766	0	0	0
T3	2907	1	0	0
T4	32322	0	0	0
T9	48781	1	0	0
T10	27424	0	0	0
T11	21109	3	0	0
T12	37890	1	0	0
T13	4543	0	0	0
T15	0	1	0	0
T17	0	2	0	0
T18	2707	0	0	0
T20	0	1	0	0
T47	0	1	0	0
T54	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	817	0	0
T1	14143	2	0	0
T2	19766	0	0	0
T3	2907	1	0	0
T4	32322	0	0	0
T9	48781	1	0	0
T10	27424	0	0	0
T11	21109	3	0	0
T12	37890	1	0	0
T13	4543	0	0	0
T15	0	1	0	0
T17	0	2	0	0
T18	2707	0	0	0
T20	0	1	0	0
T47	0	1	0	0
T54	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	801	0	0
T1	14143	2	0	0
T2	19766	0	0	0
T3	2907	1	0	0
T4	32322	0	0	0
T9	48781	1	0	0
T10	27424	0	0	0
T11	21109	3	0	0
T12	37890	1	0	0
T13	4543	0	0	0
T15	0	1	0	0
T17	0	2	0	0
T18	2707	0	0	0
T20	0	1	0	0
T47	0	1	0	0
T54	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	775	0	0
T1	14143	2	0	0
T2	19766	0	0	0
T3	2907	1	0	0
T4	32322	0	0	0
T9	48781	1	0	0
T10	27424	0	0	0
T11	21109	3	0	0
T12	37890	1	0	0
T13	4543	0	0	0
T15	0	1	0	0
T17	0	2	0	0
T18	2707	0	0	0
T20	0	1	0	0
T47	0	1	0	0
T54	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	851	0	0
T1	14143	1	0	0
T2	19766	0	0	0
T3	2907	0	0	0
T4	32322	0	0	0
T9	48781	0	0	0
T10	27424	0	0	0
T11	21109	0	0	0
T12	37890	0	0	0
T13	4543	0	0	0
T14	0	1	0	0
T15	0	3	0	0
T17	0	2	0	0
T18	2707	0	0	0
T42	0	1	0	0
T43	0	14	0	0
T95	0	3	0	0
T96	0	4	0	0
T97	0	2	0	0
T98	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	120215	0	0
T1	14143	1	0	0
T2	19766	0	0	0
T3	2907	0	0	0
T4	32322	0	0	0
T9	48781	0	0	0
T10	27424	0	0	0
T11	21109	0	0	0
T12	37890	0	0	0
T13	4543	0	0	0
T14	0	88	0	0
T15	0	241	0	0
T17	0	930	0	0
T18	2707	0	0	0
T42	0	771	0	0
T43	0	442	0	0
T95	0	193	0	0
T96	0	689	0	0
T97	0	395	0	0
T98	0	1281	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	749	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T14	8435	1	0	0
T15	30080	3	0	0
T17	13556	1	0	0
T20	30231	0	0	0
T25	14207	0	0	0
T43	0	14	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T53	1413	0	0	0
T95	0	3	0	0
T96	0	4	0	0
T97	0	2	0	0
T98	0	6	0	0
T107	0	7	0	0
T108	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	62	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T15	30080	0	0	0
T17	13556	1	0	0
T20	30231	0	0	0
T25	14207	0	0	0
T33	0	2	0	0
T42	0	1	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T49	0	1	0	0
T53	1413	0	0	0
T54	22882	0	0	0
T62	0	1	0	0
T99	0	1	0	0
T113	0	2	0	0
T114	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	1086	0	0
T4	32322	158	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T7	0	291	0	0
T8	0	171	0	0
T14	8435	0	0	0
T15	30080	0	0	0
T17	13556	0	0	0
T20	30231	0	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T51	0	141	0	0
T52	0	325	0	0
T53	1413	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	876	0	0
T4	32322	128	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T7	0	231	0	0
T8	0	141	0	0
T14	8435	0	0	0
T15	30080	0	0	0
T17	13556	0	0	0
T20	30231	0	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T51	0	111	0	0
T52	0	265	0	0
T53	1413	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542900546	542833363	0	0
T1	14143	14074	0	0
T2	19766	19635	0	0
T3	2907	2835	0	0
T4	171	104	0	0
T9	48781	48689	0	0
T10	27424	27363	0	0
T11	21109	21036	0	0
T12	37890	37803	0	0
T13	4543	4447	0	0
T18	2707	2627	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	543070428	0	0
T1	14143	14074	0	0
T2	19766	19635	0	0
T3	2907	2835	0	0
T4	32322	19300	0	0
T9	48781	48689	0	0
T10	27424	27363	0	0
T11	21109	21036	0	0
T12	37890	37803	0	0
T13	4543	4447	0	0
T18	2707	2627	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T13 T17 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T13 T17 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T13 T17 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T17 
159        1/1                    state_d = TimeoutSt;
           Tests:       T12 T14 T17 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T12 T14 T17 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T12 T14 T17 
172        1/1                    state_d    = Phase0St;
           Tests:       T12 T17 T42 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T12 T17 T42 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T12 T17 T42 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T12 T17 T42 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T12 T14 T17 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T17 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T14 T17 T16 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T14 T17 T16 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T12 T13 T17 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T12 T13 T17 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T12 T13 T17 
190        1/1                  esc_state_o = Phase0;
           Tests:       T12 T13 T17 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T12 T13 T17 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T12 T13 T17 
194        1/1                    state_d = IdleSt;
           Tests:       T31 T71 T152 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T71 T152 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T31 T71 T152 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T12 T13 T17 
198        1/1                    state_d = Phase1St;
           Tests:       T12 T13 T17 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T13 T17 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T13 T17 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T12 T13 T17 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T12 T13 T17 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T12 T13 T17 
207        1/1                  esc_state_o = Phase1;
           Tests:       T12 T13 T17 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T12 T13 T17 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T12 T13 T17 
211        1/1                    state_d = IdleSt;
           Tests:       T67 T119 T153 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T67 T119 T153 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T67 T119 T153 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T12 T13 T17 
215        1/1                    state_d = Phase2St;
           Tests:       T12 T13 T17 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T13 T17 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T13 T17 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T12 T13 T17 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T12 T13 T17 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T12 T13 T17 
224        1/1                  esc_state_o = Phase2;
           Tests:       T12 T13 T17 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T12 T13 T17 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T12 T13 T17 
229        1/1                    state_d = IdleSt;
           Tests:       T36 T32 T67 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T36 T32 T67 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T36 T32 T67 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T12 T13 T17 
233        1/1                    state_d = Phase3St;
           Tests:       T12 T13 T17 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T13 T17 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T12 T13 T17 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T12 T13 T17 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T12 T13 T17 
241        1/1                  esc_state_o = Phase3;
           Tests:       T12 T13 T17 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T12 T13 T17 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T12 T13 T17 
245        1/1                    state_d = IdleSt;
           Tests:       T154 T155 T21 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T154 T155 T21 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T154 T155 T21 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T12 T13 T17 
249        1/1                    state_d = TerminalSt;
           Tests:       T12 T13 T17 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T13 T17 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T12 T13 T17 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T12 T13 T17 
259        1/1                  esc_state_o = Terminal;
           Tests:       T12 T13 T17 
260        1/1                  if (clr_i) begin
           Tests:       T12 T13 T17 
261        1/1                    state_d = IdleSt;
           Tests:       T17 T15 T60 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T2,T12,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T12,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T39
1	1	1	Covered	T2,T13,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T14,T17
1	0	1	Covered	T13,T45,T53
1	1	0	Covered	T14,T15,T56
1	1	1	Covered	T12,T14,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T17
0	1	Covered	T12,T17,T42
1	0	Covered	T62,T65,T67

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T14,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T62,T65,T67

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T17
1	0	Not Covered
1	1	Covered	T12,T17,T42

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T12,T17,T15
1	Covered	T13,T45,T53

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T12,T13,T17
1	Covered	T46,T42,T60

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12,T13,T17
1	Covered	T15,T56,T59

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T13,T45,T53
1	Covered	T12,T17,T55

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T12,T13,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T13,T17,T45

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T12,T13,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T13,T17,T45

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T12,T13,T17
Phase1St	198	Covered	T12,T13,T17
Phase2St	215	Covered	T12,T13,T17
Phase3St	233	Covered	T12,T13,T17
TerminalSt	249	Covered	T12,T13,T17
TimeoutSt	159	Covered	T12,T14,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T7,T8
IdleSt->Phase0St	152	Covered	T13,T17,T45
IdleSt->TimeoutSt	159	Covered	T12,T14,T17
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T49,T31,T156
Phase0St->Phase1St	198	Covered	T12,T13,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T67,T119,T153
Phase1St->Phase2St	215	Covered	T12,T13,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T36,T32,T67
Phase2St->Phase3St	233	Covered	T12,T13,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T154,T155,T21
Phase3St->TerminalSt	249	Covered	T12,T13,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T17,T15,T60
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T14,T17,T16
TimeoutSt->Phase0St	172	Covered	T12,T17,T42

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T13,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T17,T42
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T14,T17,T16
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T31,T71,T152
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T12,T13,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T12,T17,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T67,T119,T153
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T12,T13,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T12,T17,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T36,T32,T67
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T12,T13,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T12,T17,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T154,T155,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T12,T13,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T17,T15,T55
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T15,T60
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T12,T13,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	543226663	227	0	0
CheckAccumTrig0_A	543226663	438	0	0
CheckAccumTrig1_A	543226663	25	0	0
CheckClr_A	543226663	214	0	0
CheckEn_A	542902733	253035245	0	0
CheckPhase0_A	543226663	515	0	0
CheckPhase1_A	543226663	505	0	0
CheckPhase2_A	543226663	495	0	0
CheckPhase3_A	543226663	487	0	0
CheckTimeout0_A	543226663	598	0	0
CheckTimeoutSt1_A	543226663	78822	0	0
CheckTimeoutSt2_A	543226663	505	0	0
CheckTimeoutStTrig_A	543226663	64	0	0
ErrorStAllEscAsserted_A	543226663	1047	0	0
ErrorStIsTerminal_A	543226663	837	0	0
EscStateOut_A	542900546	542833363	0	0
u_state_regs_A	543226663	543070428	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	227	0	0
T4	32322	35	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T7	0	65	0	0
T8	0	47	0	0
T14	8435	0	0	0
T15	30080	0	0	0
T17	13556	0	0	0
T20	30231	0	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T51	0	29	0	0
T52	0	51	0	0
T53	1413	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	438	0	0
T4	32322	0	0	0
T5	20239	0	0	0
T10	27424	0	0	0
T11	21109	0	0	0
T13	4543	1	0	0
T14	8435	0	0	0
T15	0	1	0	0
T17	13556	1	0	0
T18	2707	0	0	0
T45	3521	1	0	0
T46	0	1	0	0
T47	4065	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	25	0	0
T62	457269	1	0	0
T65	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T78	178936	0	0	0
T79	80516	0	0	0
T80	2656	0	0	0
T81	48485	0	0	0
T82	100061	0	0	0
T83	132078	0	0	0
T84	39006	0	0	0
T85	445386	0	0	0
T86	116738	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	214	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T15	30080	1	0	0
T17	13556	2	0	0
T20	30231	0	0	0
T25	14207	0	0	0
T36	0	1	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T50	0	4	0	0
T53	1413	0	0	0
T54	22882	0	0	0
T60	0	1	0	0
T87	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542902733	253035245	0	0
T1	14143	14073	0	0
T2	19766	2575	0	0
T3	2907	2184	0	0
T4	677	609	0	0
T9	48781	48688	0	0
T10	27424	27362	0	0
T11	21109	21035	0	0
T12	37890	586	0	0
T13	4543	2749	0	0
T18	2707	2626	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	515	0	0
T4	32322	0	0	0
T5	20239	0	0	0
T10	27424	0	0	0
T11	21109	0	0	0
T12	37890	1	0	0
T13	4543	1	0	0
T14	8435	0	0	0
T15	0	1	0	0
T17	13556	2	0	0
T18	2707	0	0	0
T45	3521	1	0	0
T46	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	505	0	0
T4	32322	0	0	0
T5	20239	0	0	0
T10	27424	0	0	0
T11	21109	0	0	0
T12	37890	1	0	0
T13	4543	1	0	0
T14	8435	0	0	0
T15	0	1	0	0
T17	13556	2	0	0
T18	2707	0	0	0
T45	3521	1	0	0
T46	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	495	0	0
T4	32322	0	0	0
T5	20239	0	0	0
T10	27424	0	0	0
T11	21109	0	0	0
T12	37890	1	0	0
T13	4543	1	0	0
T14	8435	0	0	0
T15	0	1	0	0
T17	13556	2	0	0
T18	2707	0	0	0
T45	3521	1	0	0
T46	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	487	0	0
T4	32322	0	0	0
T5	20239	0	0	0
T10	27424	0	0	0
T11	21109	0	0	0
T12	37890	1	0	0
T13	4543	1	0	0
T14	8435	0	0	0
T15	0	1	0	0
T17	13556	2	0	0
T18	2707	0	0	0
T45	3521	1	0	0
T46	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	598	0	0
T4	32322	0	0	0
T5	20239	0	0	0
T10	27424	0	0	0
T11	21109	0	0	0
T12	37890	1	0	0
T13	4543	0	0	0
T14	8435	2	0	0
T16	0	1	0	0
T17	13556	2	0	0
T18	2707	0	0	0
T42	0	1	0	0
T43	0	12	0	0
T45	3521	0	0	0
T58	0	1	0	0
T96	0	11	0	0
T97	0	5	0	0
T99	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	78822	0	0
T4	32322	0	0	0
T5	20239	0	0	0
T10	27424	0	0	0
T11	21109	0	0	0
T12	37890	101	0	0
T13	4543	0	0	0
T14	8435	191	0	0
T16	0	81	0	0
T17	13556	204	0	0
T18	2707	0	0	0
T42	0	355	0	0
T43	0	483	0	0
T45	3521	0	0	0
T58	0	377	0	0
T96	0	1700	0	0
T97	0	1169	0	0
T99	0	543	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	505	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T14	8435	2	0	0
T15	30080	0	0	0
T16	0	1	0	0
T17	13556	1	0	0
T20	30231	0	0	0
T25	14207	0	0	0
T43	0	12	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T53	1413	0	0	0
T58	0	1	0	0
T96	0	11	0	0
T97	0	5	0	0
T100	0	3	0	0
T101	0	1	0	0
T109	0	12	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	64	0	0
T4	32322	0	0	0
T5	20239	0	0	0
T10	27424	0	0	0
T11	21109	0	0	0
T12	37890	1	0	0
T13	4543	0	0	0
T14	8435	0	0	0
T17	13556	1	0	0
T18	2707	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T42	0	1	0	0
T45	3521	0	0	0
T49	0	1	0	0
T62	0	1	0	0
T90	0	2	0	0
T99	0	1	0	0
T113	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	1047	0	0
T4	32322	154	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T7	0	315	0	0
T8	0	164	0	0
T14	8435	0	0	0
T15	30080	0	0	0
T17	13556	0	0	0
T20	30231	0	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T51	0	137	0	0
T52	0	277	0	0
T53	1413	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	837	0	0
T4	32322	124	0	0
T5	20239	0	0	0
T6	35868	0	0	0
T7	0	255	0	0
T8	0	134	0	0
T14	8435	0	0	0
T15	30080	0	0	0
T17	13556	0	0	0
T20	30231	0	0	0
T45	3521	0	0	0
T47	4065	0	0	0
T51	0	107	0	0
T52	0	217	0	0
T53	1413	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542900546	542833363	0	0
T1	14143	14074	0	0
T2	19766	19635	0	0
T3	2907	2835	0	0
T4	171	104	0	0
T9	48781	48689	0	0
T10	27424	27363	0	0
T11	21109	21036	0	0
T12	37890	37803	0	0
T13	4543	4447	0	0
T18	2707	2627	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	543226663	543070428	0	0
T1	14143	14074	0	0
T2	19766	19635	0	0
T3	2907	2835	0	0
T4	32322	19300	0	0
T9	48781	48689	0	0
T10	27424	27363	0	0
T11	21109	21036	0	0
T12	37890	37803	0	0
T13	4543	4447	0	0
T18	2707	2627	0	0