Module Definition
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Module Instance : tb.dut.u_alert_handler_lpg_ctrl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_map[0].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[10].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[11].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[12].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[13].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[14].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[15].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[16].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[17].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[18].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[19].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[1].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[20].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[21].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[22].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[23].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[24].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[25].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[26].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[27].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[28].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[29].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[2].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[30].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[31].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[32].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[33].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[34].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[35].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[36].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[37].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[38].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[39].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[3].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[40].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[41].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[42].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[43].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[44].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[45].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[46].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[47].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[48].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[49].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[4].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[50].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[51].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[52].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[53].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[54].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[55].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[56].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[57].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[58].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[59].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[5].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[60].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[61].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[62].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[63].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[64].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[6].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[7].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[8].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[9].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_lpgs[0].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[0].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[10].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[10].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[11].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[11].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[12].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[12].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[13].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[13].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[14].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[14].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[15].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[15].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[16].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[16].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[17].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[17].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[18].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[18].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[19].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[19].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[1].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[1].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[20].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[20].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[21].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[21].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[22].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[22].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[23].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[23].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[2].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[2].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[3].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[3].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[4].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[4].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[5].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[5].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[6].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[6].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[7].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[7].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[8].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[8].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[9].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[9].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00

Line Coverage for Module : alert_handler_lpg_ctrl
Line No.TotalCoveredPercent
TOTAL313096.77
CONT_ASSIGN5411100.00
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CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
ALWAYS787685.71

53 // Otherwise, the output may have any value other than On. 54 24/24 assign lpg_init_trig[k] = mubi4_or_hi(synced_lpg_cg_en[k], synced_lpg_rst_en[k]); Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  55 end 56 57 ////////////////////////////////// 58 // LPG to Alert Channel Mapping // 59 ////////////////////////////////// 60 61 // select the correct lpg for the alert channel at index j and buffer the multibit signal for each 62 // alert channel. 63 for (genvar j=0; j < NAlerts; j++) begin : gen_alert_map 64 prim_mubi4_sync #( 65 .AsyncOn(0) // no sync flops 66 ) u_prim_mubi4_sync_lpg_en ( 67 .clk_i, 68 .rst_ni, 69 .mubi_i(lpg_init_trig[LpgMap[j]]), 70 .mubi_o({alert_init_trig_o[j]}) 71 ); 72 end 73 74 // explicitly read all unused lpg triggers to avoid lint errors. 75 logic [NLpg-1:0] lpg_used; 76 logic unused_lpg_init_trig; 77 always_comb begin 78 1/1 lpg_used = '0; Tests: T1 T2 T3  79 1/1 unused_lpg_init_trig = 1'b0; Tests: T1 T2 T3  80 1/1 for (int j=0; j < NAlerts; j++) begin Tests: T1 T2 T3  81 1/1 lpg_used[LpgMap[j]] |= 1'b1; Tests: T1 T2 T3  82 end 83 1/1 for (int k=0; k < NLpg; k++) begin Tests: T1 T2 T3  84 1/1 if (!lpg_used) begin Tests: T1 T2 T3  85 0/1 ==> unused_lpg_init_trig ^= ^lpg_init_trig[k]; 86 end MISSING_ELSE

Branch Coverage for Module : alert_handler_lpg_ctrl
Line No.TotalCoveredPercent
Branches 2 1 50.00
IF 84 2 1 50.00


84 if (!lpg_used) begin -1- 85 unused_lpg_init_trig ^= ^lpg_init_trig[k]; ==> 86 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl
Line No.TotalCoveredPercent
TOTAL3030100.00
CONT_ASSIGN5411100.00
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CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
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CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
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CONT_ASSIGN5411100.00
ALWAYS7866100.00

53 // Otherwise, the output may have any value other than On. 54 24/24 assign lpg_init_trig[k] = mubi4_or_hi(synced_lpg_cg_en[k], synced_lpg_rst_en[k]); Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  55 end 56 57 ////////////////////////////////// 58 // LPG to Alert Channel Mapping // 59 ////////////////////////////////// 60 61 // select the correct lpg for the alert channel at index j and buffer the multibit signal for each 62 // alert channel. 63 for (genvar j=0; j < NAlerts; j++) begin : gen_alert_map 64 prim_mubi4_sync #( 65 .AsyncOn(0) // no sync flops 66 ) u_prim_mubi4_sync_lpg_en ( 67 .clk_i, 68 .rst_ni, 69 .mubi_i(lpg_init_trig[LpgMap[j]]), 70 .mubi_o({alert_init_trig_o[j]}) 71 ); 72 end 73 74 // explicitly read all unused lpg triggers to avoid lint errors. 75 logic [NLpg-1:0] lpg_used; 76 logic unused_lpg_init_trig; 77 always_comb begin 78 1/1 lpg_used = '0; Tests: T1 T2 T3  79 1/1 unused_lpg_init_trig = 1'b0; Tests: T1 T2 T3  80 1/1 for (int j=0; j < NAlerts; j++) begin Tests: T1 T2 T3  81 1/1 lpg_used[LpgMap[j]] |= 1'b1; Tests: T1 T2 T3  82 end 83 1/1 for (int k=0; k < NLpg; k++) begin Tests: T1 T2 T3  84 1/1 if (!lpg_used) begin Tests: T1 T2 T3  85 excluded unused_lpg_init_trig ^= ^lpg_init_trig[k]; Exclude Annotation: VC_COV_UNR 86 end MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl
Line No.TotalCoveredPercent
Branches 1 1 100.00
IF 84 1 1 100.00


84 if (!lpg_used) begin -1- 85 unused_lpg_init_trig ^= ^lpg_init_trig[k]; ==> (Excluded) Exclude Annotation: VC_COV_UNR 86 end MISSING_ELSE ==>

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3

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